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1. 发明授权

US08283960B2 Minimal bubble voltage regulator 有权
标题翻译：最小气泡电压调节器
公开(公告)号：US08283960B2
公开(公告)日：2012-10-09
申请号：US12430829
申请日：2009-04-27
申请人： Hanh-Phuc Le , Robert P. Masleid , David Greenhill
发明人： Hanh-Phuc Le , Robert P. Masleid , David Greenhill
IPC分类号： H03H11/26
CPC分类号： G05F1/46
摘要： A digital voltage regulator including a dual rail delay chain having large size, feed forward cross-coupled inverters that interconnect the two rails. Stages of the delay chain include a dual-ended output that provides a data signal and a substantially simultaneous data complement signal to a flip-flop component associated with a sampling circuit. In use, the enhanced resolution delay chain and the reduced metastability window flop-flop increase the precision of the digital voltage regulator.
摘要翻译：一种数字电压调节器，包括具有大尺寸的双轨延迟链，其互连两个导轨的前馈交叉耦合逆变器。延迟链的阶段包括双端输出，其向与采样电路相关联的触发器组件提供数据信号和基本上同时的数据补码信号。在使用中，增强分辨率延迟链和降低的亚稳态窗触发器提高了数字电压调节器的精度。

2. 发明申请

US20100271099A1 FINE GRAIN TIMING 有权
标题翻译：精细时序
公开(公告)号：US20100271099A1
公开(公告)日：2010-10-28
申请号：US12430854
申请日：2009-04-27
申请人： Hanh-Phuc Le , Robert P. Masleid , David Greenhill
发明人： Hanh-Phuc Le , Robert P. Masleid , David Greenhill
IPC分类号： H03H11/26
CPC分类号： H03K5/131
摘要： A dual rail delay chain having cross-coupled inverters that interconnect the two rails. Delay chain embodiments include cross-coupled inverters that are part of a feed forward signal path between the two rails and are of a larger size than inverters associated with the two rails. The large size feed forward cross-coupled inverters contribute to an enhanced resolution of the delay chain.
摘要翻译：具有互连两个导轨的交叉耦合逆变器的双轨延迟链。延迟链实施例包括交叉耦合的反相器，其是两个轨道之间的前馈信号路径的一部分，并且具有比与两个轨道相关联的逆变器更大的尺寸。大尺寸前馈交叉耦合逆变器有助于提高延迟链的分辨率。

3. 发明授权

US08198931B2 Fine grain timing 有权
标题翻译：细粒时间
公开(公告)号：US08198931B2
公开(公告)日：2012-06-12
申请号：US12430854
申请日：2009-04-27
申请人： Hanh-Phuc Le , Robert P. Masleid , David Greenhill
发明人： Hanh-Phuc Le , Robert P. Masleid , David Greenhill
IPC分类号： H03H11/26
CPC分类号： H03K5/131
摘要： A dual rail delay chain having cross-coupled inverters that interconnect the two rails. Delay chain embodiments include cross-coupled inverters that are part of a feed forward signal path between the two rails and are of a larger size than inverters associated with the two rails. The large size feed forward cross-coupled inverters contribute to an enhanced resolution of the delay chain.
摘要翻译：具有互连两个导轨的交叉耦合逆变器的双轨延迟链。延迟链实施例包括交叉耦合的反相器，其是两个轨道之间的前馈信号路径的一部分，并且具有比与两个轨道相关联的逆变器更大的尺寸。大尺寸前馈交叉耦合逆变器有助于提高延迟链的分辨率。

4. 发明申请

US20100271100A1 MINIMAL BUBBLE VOLTAGE REGULATOR 有权
标题翻译：最小泡压稳压器
公开(公告)号：US20100271100A1
公开(公告)日：2010-10-28
申请号：US12430829
申请日：2009-04-27
申请人： Hanh-Phuc Le , Robert P. Masleid , David Greenhill
发明人： Hanh-Phuc Le , Robert P. Masleid , David Greenhill
IPC分类号： H03H11/26
CPC分类号： G05F1/46
摘要： A digital voltage regulator including a dual rail delay chain having large size, feed forward cross-coupled inverters that interconnect the two rails. Stages of the delay chain include a dual-ended output that provides a data signal and a substantially simultaneous data complement signal to a flip-flop component associated with a sampling circuit. In use, the enhanced resolution delay chain and the reduced metastability window flop-flop increase the precision of the digital voltage regulator.
摘要翻译：一种数字电压调节器，包括具有大尺寸的双轨延迟链，其互连两个导轨的前馈交叉耦合逆变器。延迟链的阶段包括双端输出，其向与采样电路相关联的触发器组件提供数据信号和基本上同时的数据补码信号。在使用中，增强分辨率延迟链和降低的亚稳态窗触发器提高了数字电压调节器的精度。

5. 发明申请

US20100271085A1 DELAY CHAIN INITIALIZATION 有权
标题翻译：延迟链初始化
公开(公告)号：US20100271085A1
公开(公告)日：2010-10-28
申请号：US12430846
申请日：2009-04-27
申请人： Hanh-Phuc Le , Robert P. Masleid
发明人： Hanh-Phuc Le , Robert P. Masleid
IPC分类号： H03L7/00
CPC分类号： H03K5/131
摘要： A delay chain initialization circuit that converts a singled-sided signal to a dual sided-signal. The dual-sided delay chain including a data rail and a complement rail. Each of the data rail and data complement rail include inverter chains that are interconnected through cross-coupled inverter pairs. The delay chain initialization circuit being adapted to produce, at an output, a data signal and a data complement signal that are substantially simultaneous.
摘要翻译：延迟链初始化电路，其将单面信号转换为双面信号。双面延迟链包括数据轨和互补轨。数据轨道和数据补充轨道中的每一条都包括通过交叉耦合的逆变器对互连的逆变器链。延迟链初始化电路适于在输出端产生基本同时的数据信号和数据补码信号。

6. 发明授权

US08179165B2 Precision sampling circuit 有权
标题翻译：精密采样电路
公开(公告)号：US08179165B2
公开(公告)日：2012-05-15
申请号：US12430840
申请日：2009-04-27
申请人： Hanh-Phuc Le , Robert P. Masleid
发明人： Hanh-Phuc Le , Robert P. Masleid
IPC分类号： G11C27/02
CPC分类号： H03K5/131
摘要： A sampling circuit including a number of state elements or flip-flops. The state elements or flip-flops are each clocked by a signal that causes them to sample their inputs at a predetermined time. In sampling a plurality of digital inputs, a captured delay chain value is stored by the sampling circuit. Each flip-flop holds one bit and together the total number of bits represent this captured delay chain value. Each flip-flop is provided with a data and a data complement signal as an input, the data and data complement signal being substantially simultaneous. In operation each flip-flop includes a direct connection of the data and data complement signals to a pair of transistors that further operate to capture the logical value carried by the input.
摘要翻译：包括多个状态元件或触发器的采样电路。状态元件或触发器每个都由一个信号进行计时，该信号使得它们在预定的时间对其输入进行采样。在对多个数字输入进行采样时，所采集的延迟链值由采样电路存储。每个触发器保持一位，并且总共的位数表示该捕获的延迟链值。每个触发器被提供有数据和数据补码信号作为输入，数据和数据补码信号基本上同时进行。在操作中，每个触发器包括将数据和数据补码信号直接连接到一对晶体管，其进一步操作以捕获由输入携带的逻辑值。

7. 发明申请

US20100271076A1 PRECISION SAMPLING CIRCUIT 有权
标题翻译：精密采样电路
公开(公告)号：US20100271076A1
公开(公告)日：2010-10-28
申请号：US12430840
申请日：2009-04-27
申请人： Hanh-Phuc Le , Robert P. Masleid
发明人： Hanh-Phuc Le , Robert P. Masleid
IPC分类号： H03K5/00
CPC分类号： H03K5/131
摘要： A sampling circuit including a number of state elements or flip-flops. The state elements or flip-flops are each clocked by a signal that causes them to sample their inputs at a predetermined time. In sampling a plurality of digital inputs, a captured delay chain value is stored by the sampling circuit. Each flip-flop holds one bit and together the total number of bits represent this captured delay chain value. Each flip-flop is provided with a data and a data complement signal as an input, the data and data complement signal being substantially simultaneous. In operation each flip-flop includes a direct connection of the data and data complement signals to a pair of transistors that further operate to capture the logical value carried by the input.
摘要翻译：包括多个状态元件或触发器的采样电路。状态元件或触发器每个都由一个信号进行计时，该信号使得它们在预定的时间对其输入进行采样。在对多个数字输入进行采样时，所采集的延迟链值由采样电路存储。每个触发器保持一位，并且总共的位数表示该捕获的延迟链值。每个触发器被提供有数据和数据补码信号作为输入，数据和数据补码信号基本上同时进行。在操作中，每个触发器包括将数据和数据补码信号直接连接到进一步操作以捕获由输入携带的逻辑值的一对晶体管。

8. 发明授权

US08242823B2 Delay chain initialization 有权
标题翻译：延迟链初始化
公开(公告)号：US08242823B2
公开(公告)日：2012-08-14
申请号：US12430846
申请日：2009-04-27
申请人： Hanh-Phuc Le , Robert P. Masleid
发明人： Hanh-Phuc Le , Robert P. Masleid
IPC分类号： H03L7/00
CPC分类号： H03K5/131
摘要： A delay chain initialization circuit that converts a singled-sided signal to a dual sided-signal. The dual-sided delay chain including a data rail and a complement rail. Each of the data rail and data complement rail include inverter chains that are interconnected through cross-coupled inverter pairs. The delay chain initialization circuit being adapted to produce, at an output, a data signal and a data complement signal that are substantially simultaneous.
摘要翻译：延迟链初始化电路，其将单面信号转换为双面信号。双面延迟链包括数据轨和互补轨。数据轨道和数据补充轨道中的每一条都包括通过交叉耦合的逆变器对互连的逆变器链。延迟链初始化电路适于在输出端产生基本同时的数据信号和数据补码信号。

9. 发明申请

US20100127749A1 PRECISION PULSE GENERATOR 有权
标题翻译：精密脉冲发生器
公开(公告)号：US20100127749A1
公开(公告)日：2010-05-27
申请号：US12277864
申请日：2008-11-25
申请人： Robert P. Masleid , David Greenhill
发明人： Robert P. Masleid , David Greenhill
IPC分类号： H03K3/00
CPC分类号： H03K3/355 , H03K3/011 , H03K3/012 , H03K2005/00293
摘要： A pulse generator circuit. The pulse generator circuit includes a precharge circuit coupled to receive a clock signal alternating between a first logic level and a second logic level, a storage circuit having a storage node, wherein the precharge circuit is configured to precharge the storage node when the clock signal is at the first logic level, a logic circuit having an output, a first input node coupled to receive the clock signal, and a second input node coupled to the storage node and configured to produce a pulse at the second logic level responsive to the clock signal transitioning to the second logic level, and a discharge circuit configured to discharge the storage node at a predetermined delay time subsequent to the clock signal transitioning to the second logic level, wherein the output of the logic circuit transitions to the first logic level responsive to discharging the storage node.
摘要翻译：脉冲发生器电路。所述脉冲发生器电路包括预充电电路，其被耦合以接收在第一逻辑电平和第二逻辑电平之间交替的时钟信号，具有存储节点的存储电路，其中所述预充电电路被配置为当所述时钟信号为在第一逻辑电平处，具有输出的逻辑电路，被耦合以接收时钟信号的第一输入节点和耦合到存储节点的第二输入节点，并且被配置为响应于时钟信号产生处于第二逻辑电平的脉冲转换到第二逻辑电平的放电电路，以及放电电路，被配置为在时钟信号转换到第二逻辑电平之后的预定延迟时间对存储节点放电，其中逻辑电路的输出响应于放电而转变到第一逻辑电平存储节点。

10. 发明授权

US08686778B2 Integrated pulse-control and enable latch circuit 有权
标题翻译：集成脉冲控制和使能锁存电路
公开(公告)号：US08686778B2
公开(公告)日：2014-04-01
申请号：US12546529
申请日：2009-08-24
申请人： Jason M. Hart , Robert P. Masleid
发明人： Jason M. Hart , Robert P. Masleid
IPC分类号： G01R29/02 , H03K9/08 , H03K5/01 , H03K3/017 , H03K5/04 , H03K7/08 , H03K3/00 , H03K3/289
CPC分类号： H03K3/356113 , G06F1/06 , G06F1/10
摘要： The described embodiments provide a configurable clock circuit. The clock circuit includes a control and enable circuit and a clock distribution circuit. During operation, when a signal on an enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a clock mode, the control and enable circuit generates an enable signal on a control output to enable a signal on a clock input to propagate through the clock distribution circuit to the clock output. Alternatively, when a signal on the enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a pulse mode, the control and enable circuit generates a pulsed control signal on the control output to control a length of a pulse generated from the clock input on a clock output by the clock distribution circuit.
摘要翻译：所描述的实施例提供了可配置的时钟电路。时钟电路包括控制和使能电路和时钟分配电路。在操作期间，当控制和使能电路的使能输入上的信号被确认并且控制和使能电路被配置为时钟模式时，控制和使能电路在控制输出上产生使能信号，以使得能够在时钟输入通过时钟分配电路传播到时钟输出。或者，当控制和使能电路的使能输入上的信号被确认并且控制和使能电路被配置为脉冲模式时，控制和使能电路在控制输出上产生脉冲控制信号以控制一个由时钟分配电路输出的时钟上的时钟输入产生的脉冲。

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