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1. 发明授权

US06784502B2 Method of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and integrated circuits 有权
标题翻译：形成触点的方法，接触线的方法，操作集成电路的方法和集成电路
公开(公告)号：US06784502B2
公开(公告)日：2004-08-31
申请号：US09512978
申请日：2000-02-24
申请人： Robert Kerr , Brian Shirley , Luan C. Tran , Tyler A. Lowrey
发明人： Robert Kerr , Brian Shirley , Luan C. Tran , Tyler A. Lowrey
IPC分类号： H01L2976
CPC分类号： H01L27/10897 , H01L21/76895 , H01L23/535 , H01L27/10891 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and related integrated circuitry constructions are described. In one embodiment, a plurality of conductive lines are formed over a substrate and diffusion regions are formed within the substrate elevationally below the lines. The individual diffusion regions are disposed proximate individual conductive line portions and collectively define therewith individual contact pads with which electrical connection is desired. Insulative material is formed over the conductive line portions and diffusion regions, with contact openings being formed therethrough to expose portions of the individual contact pads. Conductive contacts are formed within the contact openings and in electrical connection with the individual contact pads. In a preferred embodiment, the substrate and diffusion regions provide a pn junction which is configured for biasing into a reverse-biased diode configuration. In operation, the pn junction is sufficiently biased to preclude electrical shorting between the conductive line and the substrate for selected magnitudes of electrical current provided through the conductive line and the conductive material forming the conductive contacts.
摘要翻译：描述形成触点的方法，接触线的方法，操作集成电路的方法以及相关的集成电路结构。在一个实施例中，多个导电线形成在衬底之上，扩散区形成在衬底正下方的线下方。单独的扩散区域设置在各个导电线部分附近，并且与其共同地限定需要电连接的各个接触焊盘。绝缘材料形成在导电线部分和扩散区域上，其中接触开口穿过其形成以暴露各个接触焊盘的部分。导电触点形成在接触开口内并与各个接触垫电连接。在优选实施例中，衬底和扩散区域提供pn结，其被配置为偏置成反向偏置二极管配置。在操作中，pn结被充分地偏置，以防止导电线和衬底之间的电短路，用于通过导电线和形成导电触点的导电材料提供的选定大小的电流。

2. 发明授权

US06380023B2 Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and integrated circuits 失效
标题翻译：形成触点的方法，接触线的方法，操作集成电路的方法和集成电路
公开(公告)号：US06380023B2
公开(公告)日：2002-04-30
申请号：US09146115
申请日：1998-09-02
申请人： Robert Kerr , Brian Shirley , Luan C. Tran , Tyler A. Lowrey
发明人： Robert Kerr , Brian Shirley , Luan C. Tran , Tyler A. Lowrey
IPC分类号： H01L218234
CPC分类号： H01L27/10897 , H01L21/76895 , H01L23/535 , H01L27/10891 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and related integrated circuitry constructions are described. In one embodiment, a plurality of conductive lines are formed over a substrate and diffusion regions are formed within the substrate elevationally below the lines. The individual diffusion regions are disposed proximate individual conductive line portions and collectively define therewith individual contact pads with which electrical connection is desired. Insulative material is formed over the conductive line portions and diffusion regions, with contact openings being formed therethrough to expose portions of the individual contact pads. Conductive contacts are formed within the contact openings and in electrical connection with the individual contact pads. In a preferred embodiment, the substrate and diffusion regions provide a pn junction which is configured for biasing into a reverse-biased diode configuration. In operation, the pn junction is sufficiently biased to preclude electrical shorting between the conductive line and the substrate for selected magnitudes of electrical current provided through the conductive line and the conductive material forming the conductive contacts.
摘要翻译：描述形成触点的方法，接触线的方法，操作集成电路的方法以及相关的集成电路结构。在一个实施例中，多个导电线形成在衬底之上，扩散区形成在衬底正下方的线下方。单独的扩散区域设置在各个导电线部分附近，并且与其共同地限定需要电连接的各个接触焊盘。绝缘材料形成在导电线部分和扩散区域上，其中接触开口穿过其形成以暴露各个接触焊盘的部分。导电触点形成在接触开口内并与各个接触垫电连接。在优选实施例中，衬底和扩散区域提供pn结，其被配置为偏置成反向偏置二极管配置。在操作中，pn结被充分地偏置，以防止导电线和衬底之间的电短路，用于通过导电线和形成导电触点的导电材料提供的选定大小的电流。

3. 发明授权

US06790663B2 Methods of contacting lines and methods of forming an electrical contact in a semiconductor device 有权
标题翻译：接触线的方法和在半导体器件中形成电接触的方法
公开(公告)号：US06790663B2
公开(公告)日：2004-09-14
申请号：US10098659
申请日：2002-03-12
申请人： Robert Kerr , Brian Shirley , Luan C. Tran , Tyler A. Lowrey
发明人： Robert Kerr , Brian Shirley , Luan C. Tran , Tyler A. Lowrey
IPC分类号： H01L214763
CPC分类号： H01L27/10897 , H01L21/76895 , H01L23/535 , H01L27/10891 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and related integrated circuitry constructions are described. In one embodiment, a plurality of conductive lines are formed over a substrate and diffusion regions are formed within the substrate elevationally below the lines. The individual diffusion regions are disposed proximate individual conductive line portions and collectively define therewith individual contact pads with which electrical connection is desired. Insulative material is formed over the conductive line portions and diffusion regions, with contact openings being formed therethrough to expose portions of the individual contact pads. Conductive contacts are formed within the contact openings and in electrical connection with the individual contact pads. In a preferred embodiment, the substrate and diffusion regions provide a pn junction which is configured for biasing into a reverse-biased diode configuration. In operation, the pn junction is sufficiently biased to preclude electrical shorting between the conductive line and the substrate for selected magnitudes of electrical current provided through the conductive line and the conductive material forming the conductive contacts.
摘要翻译：描述形成触点的方法，接触线的方法，操作集成电路的方法以及相关的集成电路结构。在一个实施例中，多个导电线形成在衬底之上，扩散区形成在衬底正下方的线下方。单独的扩散区域设置在各个导电线部分附近，并且与其共同地限定需要电连接的各个接触焊盘。绝缘材料形成在导电线部分和扩散区域上，其中接触开口穿过其形成以暴露各个接触焊盘的部分。导电触点形成在接触开口内并与各个接触垫电连接。在优选实施例中，衬底和扩散区域提供pn结，其被配置为偏置成反向偏置二极管配置。在操作中，pn结被充分地偏置，以防止导电线和衬底之间的电短路，用于通过导电线和形成导电触点的导电材料提供的选定大小的电流。

4. 发明授权

US06600190B2 Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions 有权
标题翻译：形成电容器的方法，形成电容器 - 位线存储器电路的方法以及相关的集成电路结构
公开(公告)号：US06600190B2
公开(公告)日：2003-07-29
申请号：US09730865
申请日：2000-12-05
申请人： Tyler A. Lowrey , Luan C. Tran , Alan R. Reinberg , D. Mark Durcan
发明人： Tyler A. Lowrey , Luan C. Tran , Alan R. Reinberg , D. Mark Durcan
IPC分类号： H01L27108
CPC分类号： H01L28/90 , H01L27/10814 , H01L27/10852 , H01L27/10894 , H01L28/84 , H01L28/91
摘要： Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material.
摘要翻译：描述形成电容器的方法，形成电容器 - 位线存储器电路的方法以及相关的集成电路结构。在一个实施例中，形成在最上表面上具有最上表面和上覆绝缘材料的电容器存储节点。随后，电容器电介质功能区域从可覆盖的电容器存储节点的至少一部分可操作地从上覆的绝缘材料离散形成。在电容器电介质功能区域和上覆绝缘材料上形成电池电极层。

5. 发明授权

US06599800B2 Methods of forming capacitors, and methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions 有权
标题翻译：形成电容器的方法以及形成电容器对位线存储器电路的方法以及相关的集成电路结构
公开(公告)号：US06599800B2
公开(公告)日：2003-07-29
申请号：US09954340
申请日：2001-09-14
申请人： Tyler A. Lowrey , Luan C. Tran , Alan R. Reinberg , Mark Durcan
发明人： Tyler A. Lowrey , Luan C. Tran , Alan R. Reinberg , Mark Durcan
IPC分类号： A01L218242
CPC分类号： H01L28/90 , H01L27/10814 , H01L27/10852 , H01L27/10894 , H01L28/84 , H01L28/91
摘要： Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material.
摘要翻译：描述形成电容器的方法，形成电容器 - 位线存储器电路的方法以及相关的集成电路结构。在一个实施例中，形成在最上表面上具有最上表面和上覆绝缘材料的电容器存储节点。随后，电容器电介质功能区域从可覆盖的电容器存储节点的至少一部分可操作地从上覆的绝缘材料离散形成。在电容器电介质功能区域和上覆绝缘材料上形成电池电极层。

6. 发明授权

US06548390B1 SEMICONDUCTOR PROCESSING METHODS OF FORMING CONTACT OPENINGS, METHODS OF FORMING MEMORY CIRCUITRY, METHODS OF FORMING ELECTRICAL CONNECTIONS, AND METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMORY (DRAM) CIRCUITRY 有权
公开(公告)号：US06548390B1
公开(公告)日：2003-04-15
申请号：US10153830
申请日：2002-05-21
申请人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
发明人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
IPC分类号： H01L2144
CPC分类号： H01L27/10888 , H01L21/32051 , H01L21/76895 , H01L21/76897 , H01L27/10855 , H01L27/10885
摘要： Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.

7. 发明授权

US06455407B2 Methods of forming memory circuitry, methods of forming electrical connections, and methods of forming dynamic random access memory (DRAM) circuitry 有权
标题翻译：形成存储器电路的方法，形成电连接的方法以及形成动态随机存取存储器（DRAM）电路的方法
公开(公告)号：US06455407B2
公开(公告)日：2002-09-24
申请号：US09765236
申请日：2001-01-16
申请人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
发明人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
IPC分类号： H01L214763
CPC分类号： H01L27/10888 , H01L21/32051 , H01L21/76895 , H01L21/76897 , H01L27/10855 , H01L27/10885
摘要： Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.
摘要翻译：描述形成接触开口，存储器电路和动态随机存取存储器（DRAM）电路的方法。在一个实施方案中，字线阵列和位线形成在衬底表面上并由中间绝缘层隔开。位线的导电部分向外露出，并且在衬底和位线的暴露的导电部分上形成一层材料。材料层的选定部分与中间层的部分一起被去除，足以使（a）暴露衬底表面的选定区域，并且（b）重新暴露位线的导电部分。随后形成导电材料以将暴露的衬底区域与各个位线的相关联的导电部分电连接。

8. 发明授权

US06335270B1 Semiconductor processing methods of forming contact openings, methods of forming memory circuitry, methods of forming electrical connections, and methods of forming dynamic random access memory (DRAM) circuitry 有权
公开(公告)号：US06335270B1
公开(公告)日：2002-01-01
申请号：US09848863
申请日：2001-05-03
申请人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
发明人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
IPC分类号： H01L2144
摘要： Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.

9. 发明授权

US06489226B2 SEMICONDUCTOR PROCESSING METHODS OF FORMING CONTACT OPENINGS, METHODS OF FORMING MEMORY CIRCUITRY, METHODS OF FORMING ELECTRICAL CONNECTIONS, AND METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMORY (DRAM) CIRCUITRY 有权
标题翻译：形成接触开口的半导体处理方法，形成存储器电路的方法，形成电连接的方法以及形成动态随机存取存储器（DRAM）电路的方法
公开(公告)号：US06489226B2
公开(公告)日：2002-12-03
申请号：US09995373
申请日：2001-11-26
申请人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
发明人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
IPC分类号： H01L2144
CPC分类号： H01L27/10888 , H01L21/32051 , H01L21/76895 , H01L21/76897 , H01L27/10855 , H01L27/10885
摘要： Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.
摘要翻译：描述形成接触开口，存储器电路和动态随机存取存储器（DRAM）电路的方法。在一个实施方案中，字线阵列和位线形成在衬底表面上并由中间绝缘层隔开。位线的导电部分向外露出，并且在衬底和位线的暴露的导电部分上形成一层材料。材料层的选定部分与中间层的部分一起被去除，足以使（a）暴露衬底表面的选定区域，并且（b）重新暴露位线的导电部分。随后形成导电材料以将暴露的衬底区域与各个位线的相关联的导电部分电连接。

10. 发明授权

US06391756B1 Semiconductor processing methods of forming contact openings 有权
标题翻译：形成接触开口的半导体加工方法
公开(公告)号：US06391756B1
公开(公告)日：2002-05-21
申请号：US09387040
申请日：1999-08-31
申请人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
发明人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
IPC分类号： H01L2144
CPC分类号： H01L27/10888 , H01L21/32051 , H01L21/76895 , H01L21/76897 , H01L27/10855 , H01L27/10885
摘要： Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.
摘要翻译：描述形成接触开口，存储器电路和动态随机存取存储器（DRAM）电路的方法。在一个实施方案中，字线阵列和位线形成在衬底表面上并由中间绝缘层隔开。位线的导电部分向外露出，并且在衬底和位线的暴露的导电部分上形成一层材料。材料层的选定部分与中间层的部分一起被移除，足以使（a）暴露衬底表面的选定区域，并且（b）重新暴露位线的导电部分。随后形成导电材料以将暴露的衬底区域与各个位线的相关联的导电部分电连接。

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