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1. 发明授权

US5651103A Mail handling apparatus and process for printing an image column-by-column in real time 失效
标题翻译：实时打印图像的邮件处理装置和处理
公开(公告)号：US5651103A
公开(公告)日：1997-07-22
申请号：US554179
申请日：1995-11-06
申请人： Robert G. Arsenault , Steven J. Pauly , Sungwon Moh , David N. Long
发明人： Robert G. Arsenault , Steven J. Pauly , Sungwon Moh , David N. Long
IPC分类号： B41J5/30 , G06F3/12 , G07B17/00 , G06K15/00
CPC分类号： G07B17/00508 , G07B2017/00532 , G07B2017/00645
摘要： An apparatus for producing an image in a mail handling machine includes a printing device and a non-volatile memory having fixed and variable image data elements stored therein, a first portion of the fixed image data elements being stored in a compressed manner and a second portion of the fixed image data elements being stored in a bit map form. The apparatus further includes a first control device for identifying at least one of the variable image data elements stored in the non-volatile memory and associated with the image and a second control device for receiving from the first control device data corresponding to the at least one of the variable image data elements associated with the image and for downloading from the non-volatile memory and combining fixed image data elements associated with the image with the at least one of the variable data elements associated with the image and for utilizing the combined fixed and variable data elements associated with the image to cause the printing mechanism to print the image.
摘要翻译：一种用于在邮件处理机中产生图像的设备包括：打印装置和存储有固定和可变图像数据元素的非易失性存储器，固定图像数据元素的第一部分以压缩方式存储;第二部分的固定图像数据元素以位图形式存储。该装置还包括用于识别存储在非易失性存储器中并与图像相关联的可变图像数据元素中的至少一个的第一控制装置和用于从第一控制装置接收对应于至少一个与图像相关联的可变图像数据元素和用于从非易失性存储器下载并将与图像相关联的固定图像数据元素与与图像相关联的可变数据元素中的至少一个组合并且用于组合的固定和与图像相关联的可变数据元素以使打印机构打印图像。

2. 发明授权

US5377264A Memory access protection circuit with encryption key 失效
标题翻译：存储器访问保护电路带加密密钥
公开(公告)号：US5377264A
公开(公告)日：1994-12-27
申请号：US163774
申请日：1993-12-09
申请人： Young W. Lee , Sungwon Moh , Arno Muller
发明人： Young W. Lee , Sungwon Moh , Arno Muller
IPC分类号： G06F12/14 , G06F21/00 , H04L9/00
CPC分类号： H04L9/32 , G06F12/1433 , G06F21/79
摘要： A data verification system including a circuit verifies that unlocking data generated by a microprocessor to be written into the ASIC before a memory write is valid. The microprocessor is programmed to generate an ASIC address when unlocking data is to be written to the ASIC and to encrypt and decrypt that data. The verifying circuit unit receives the encrypted data and decrypts the encrypted data and compares the decrypted data with the encrypted data. The verifying circuit generating an enable signal only if the comparison is true. An address decoding unit is provided for receiving the memory address signal and causing a memory write enable signal to be generated for the memory unit only if the verifying circuit unit has generated an enable signal. Registers unit in communication with the data bus and the verifying circuit unit are provided for writing decryption parameters in the register unit in accordance with the programming of the microprocessor during power-up of the microprocessor.
摘要翻译：包括电路的数据验证系统在存储器写入有效之前验证将由微处理器产生的数据解锁以写入ASIC。当解锁数据要写入ASIC并加密和解密该数据时，微处理器被编程为产生ASIC地址。验证电路单元接收加密数据并对加密数据进行解密，并将解密后的数据与加密数据进行比较。验证电路仅在比较为真时才产生使能信号。提供地址解码单元，用于接收存储器地址信号，并且仅当验证电路单元已经产生使能信号时才使存储器单元产生存储器写使能信号。提供与数据总线和验证电路单元通信的寄存器单元，用于在微处理器加电期间根据微处理器的编程将解密参数写入寄存器单元。

3. 发明申请

US20100106289A1 CRYPTOGRAPHIC DEVICE HAVING ACTIVE CLEARING OF MEMORY REGARDLESS OF STATE OF EXTERNAL POWER 有权
标题翻译：具有外部功能状态的存储器的主动清除的结构化设备
公开(公告)号：US20100106289A1
公开(公告)日：2010-04-29
申请号：US12257728
申请日：2008-10-24
申请人： Sungwon Moh , Peter A. Pagliaro
发明人： Sungwon Moh , Peter A. Pagliaro
IPC分类号： B07C1/00 , G06F21/00 , H02J7/00 , H04L9/00
CPC分类号： G07B17/00193 , G06F21/72 , G06F21/81 , G06F21/87 , G06F2221/2143 , G07B2017/00233 , G07B2017/00258 , G07B2017/00346
摘要： A cryptographic device that will actively clear its memory even in the absence of external power when a security breach is detected is provided. The memory cell clusters of the cryptographic device are provided with an internal power source that provides sufficient energy for the memory cell clusters to perform a clearing operation. If the external power source for the memory is removed and a physical security breach is detected, the power from the internal power source will allow the memory cells to actively clear their contents, thereby rendering any attempt to obtain the contents of the memory cells fruitless.
摘要翻译：提供了即使在检测到安全漏洞的情况下，在没有外部电源的情况下也将主动清除其存储器的加密设备。密码装置的存储单元簇具有内部电源，其为存储器单元簇提供足够的能量以执行清除操作。如果存储器的外部电源被去除并且检测到物理安全漏洞，则来自内部电源的电力将允许存储器单元主动地清除其内容，从而使获得存储器单元的内容的任何尝试无效。

4. 发明授权

US5974402A Address decoder with memory wait state circuit 失效
标题翻译：地址解码器具有内存等待状态电路
公开(公告)号：US5974402A
公开(公告)日：1999-10-26
申请号：US163812
申请日：1993-12-09
申请人： Young W. Lee , Sungwon Moh , Arno Muller
发明人： Young W. Lee , Sungwon Moh , Arno Muller
IPC分类号： G06F13/16 , G07B17/00
CPC分类号： G06F13/1689 , G07B17/00193 , G07B2017/00258 , G07B2017/00395
摘要： An electronic postage meter control system having a printer for printing mixed graphic and alphanumeric information. The control system includes a programmable microprocessor in bus communication with the printer for controlling the printer and with a plurality of memory units for accounting for postage printed by the printer. The memory units include at least a first memory unit having a write access time shorter than the write access time of a second one of said memory unit, a program memory in bus communication with the programmable microprocessor having an operating program stored therein. The programmable microprocessor is able to access the operating program, an integrated circuit, the program memory, and said first and second units. The integrated circuit has an address decoding module for generating one of a plurality control signals in a unique combination in response to a respective request by the programmable microprocessor. Respective ones of the control signals are the memory write enable signals for write enabling the first or second units where write enable signals are directed to the respective memory unit. The control system further maintains the respective write enable control signals active for at least the write access time of the first memory unit in response to generation of a respective one of the write enable control signals by the address decoder. The control system further maintains the respective write enable control signal active for an additional second period such that sum period of the first period of time in combination with the second period of time is at generally equal to the write access time required by the second memory unit.
摘要翻译：一种具有用于打印混合图形和字母数字信息的打印机的电子邮资计费器控制系统。控制系统包括与打印机总线通信的可编程微处理器，用于控制打印机以及多个存储器单元，用于计算打印机打印的邮资。所述存储器单元至少包括第一存储器单元，其具有比所述存储器单元中的第二存储器单元的写入存取时间短的写访问时间，与可编程微处理器总线通信的程序存储器，其中存储有操作程序。可编程微处理器能够访问操作程序，集成电路，程序存储器以及所述第一和第二单元。集成电路具有地址解码模块，用于响应于可编程微处理器的相应请求，以独特的组合产生多个控制信号之一。控制信号中的各个是用于写入的存储器写使能信号，使能第一或第二单元，其中写使能信号被引导到相应的存储器单元。控制系统进一步维持相应的写入使能控制信号，以响应于地址解码器产生写入使能控制信号中的相应一个而至少对第一存储器单元的写入存取时间有效。控制系统进一步维持相应的写入使能控制信号在额外的第二周期中有效，使得第一时间段的结合第二时间段的和周期大体上等于第二存储器单元所需的写入时间。

5. 发明授权

US5652796A Data encryption control system 失效
标题翻译：数据加密控制系统
公开(公告)号：US5652796A
公开(公告)日：1997-07-29
申请号：US264082
申请日：1994-06-21
申请人： Thomas F. Barraza , Young W. Lee , Sungwon Moh , Arno Muller
发明人： Thomas F. Barraza , Young W. Lee , Sungwon Moh , Arno Muller
IPC分类号： H04L9/06 , H04L9/00
CPC分类号： H04L9/0625 , H04L2209/12
摘要： The data encryption system includes a first stage and a second stage data encryption engine in combination with a micro control system. The data encryption system is responsive to control signals from the micro control system. The first stage is comprised of an 8-bit bus input and output from the first stage to the second stage data encryption engine of 64-bits. The input bus of the first stage is gated to a plurality of 8-bit registers through a plurality of AND gates having a respective one of the AND gate inputs in communication with the 8-bit bus and output from the respective AND gate directed to a respective input of the respective 8-bit registers for selectively gating data from the 8-bit bus to respective ones of the 8-bit registers. A demultiplexer includes a plurality of inputs and a plurality of outputs, a respective output of the demultiplexer being in communication with the input of a respective one of the AND gates for selectively enabling a respective one of the AND gate in response to the state of the control signals.
摘要翻译：数据加密系统包括与微控制系统组合的第一级和第二级数据加密引擎。数据加密系统响应来自微控制系统的控制信号。第一级由8位总线输入和从第一级输出到64位的第二级数据加密引擎组成。第一级的输入总线通过具有与8位总线通信的与门输入中的相应一个的多个与门门控到多个8位寄存器，并从相应的与门指向一个相应的8位寄存器的输入，用于选择性地将数据从8位总线选通到8位寄存器中的相应寄存器。解复用器包括多个输入和多个输出，多路分解器的相应输出与与门的相应一个的输入通信，用于响应于所述“与”门的状态选择性地使得与门相应的一个控制信号。

6. 发明授权

US08201267B2 Cryptographic device having active clearing of memory regardless of state of external power 有权
标题翻译：无论外部电源状态如何，加密设备都可以有效清除存储器
公开(公告)号：US08201267B2
公开(公告)日：2012-06-12
申请号：US12257728
申请日：2008-10-24
申请人： Sungwon Moh , Peter A. Pagliaro
发明人： Sungwon Moh , Peter A. Pagliaro
IPC分类号： G06F21/00
CPC分类号： G07B17/00193 , G06F21/72 , G06F21/81 , G06F21/87 , G06F2221/2143 , G07B2017/00233 , G07B2017/00258 , G07B2017/00346
摘要： A cryptographic device that will actively clear its memory even in the absence of external power when a security breach is detected is provided. The memory cell clusters of the cryptographic device are provided with an internal power source that provides sufficient energy for the memory cell clusters to perform a clearing operation. If the external power source for the memory is removed and a physical security breach is detected, the power from the internal power source will allow the memory cells to actively clear their contents, thereby rendering any attempt to obtain the contents of the memory cells fruitless.
摘要翻译：提供了即使在检测到安全漏洞的情况下，在没有外部电源的情况下也将主动清除其存储器的加密设备。密码装置的存储单元簇具有内部电源，其为存储器单元簇提供足够的能量以执行清除操作。如果存储器的外部电源被去除并且检测到物理安全漏洞，则来自内部电源的电力将允许存储器单元主动地清除其内容，从而使获得存储器单元的内容的任何尝试无效。

7. 发明授权

US6144950A Postage printing system including prevention of tampering with print data sent from a postage meter to a printer 失效
标题翻译：邮资打印系统，包括防止篡改从邮资计费器发送到打印机的打印数据
公开(公告)号：US6144950A
公开(公告)日：2000-11-07
申请号：US32804
申请日：1998-02-27
申请人： Brad L. Davies , Sungwon Moh , Mark A. Scribe
发明人： Brad L. Davies , Sungwon Moh , Mark A. Scribe
IPC分类号： G06F3/12 , B41J29/38 , G07B17/00 , G07B17/02 , G09F3/00 , G06F17/00
CPC分类号： G07B17/00733 , G07B17/00314 , G07B2017/00322 , G07B2017/0058 , G07B2017/00741 , G07B2017/00951
摘要： A postage printing system includes a printer and a postage meter. The postage meter includes a controller for generating print information having a plurality of print data blocks necessary to print a postal indicia. The printer is located remotely from the postage meter and includes a controller and a printer for printing the postal indicia. The printer controller is in operative communication with the postage meter controller for receiving the plurality of print data blocks. The postage meter controller encrypts the plurality of print data blocks into a plurality of encrypted print data blocks, respectively, using a cypher block chaining encryption algorithm prior to transmitting the plurality of encrypted print data blocks to the printer controller where they are decrypted by the printer controller. Check numbers for each print data block and validation of the check numbers may be employed at the printer controller. Also, the printer controller may compare the validation rates of print data blocks containing significant data and those containing insignificant data for evidence of tampering.
摘要翻译：邮资打印系统包括打印机和邮资计费器。邮资计包括用于生成具有打印邮戳所需的多个打印数据块的打印信息的控制器。该打印机远离邮资计费器，并包括用于打印邮戳的控制器和打印机。打印机控制器与邮资计费器控制器操作通信，用于接收多个打印数据块。邮资计算器控制器在将多个加密的打印数据块发送到打印机控制器之前，使用密码块链接加密算法将多个打印数据块分别加密成多个加密的打印数据块，打印机控制器被打印机解密控制器。检查每个打印数据块的编号，并且可以在打印机控制器上使用校验号的确认。此外，打印机控制器可以比较包含重要数据的打印数据块和包含不显着数据的打印数据块的验证率，以证明篡改。

8. 发明授权

US5729716A Memory monitoring circuit for detecting unauthorized memory access 失效
标题翻译：用于检测未经授权的存储器访问的存储器监视电路
公开(公告)号：US5729716A
公开(公告)日：1998-03-17
申请号：US648454
申请日：1996-05-15
申请人： Young W. Lee , Sungwon Moh , Arno Muller
发明人： Young W. Lee , Sungwon Moh , Arno Muller
IPC分类号： G06F12/14 , G06F21/00 , G06F12/16
CPC分类号： G06F21/79 , G06F12/1433
摘要： The memory security circuit detects when a memory unit has been accessed independently of an address instruction of a programmable microprocessor. The microprocessor is programmed to provide a unique address signal for write enabling a discrete memory unit. The memory unit has a write enable pin and chip select pin which when enabled in combination permits writing into the memory unit. The address decoder receives the unique address instruction and causes a write enable signal and a chip select signal to be generated for that memory unit. The write enable signal and chip select signal are to be received, respectively, by the write enable pin and the chip select pin of the memory unit. The memory security circuit monitors the write enable pin and the chip select pin of the memory unit and generates a first output signal when the memory unit has been properly addressed. A second output signal is generated when the memory unit has not been addressed by the address decoder and the write enable and the chip select signals are present at the memory unit.
摘要翻译：存储器安全电路检测存储器单元何时被访问，独立于可编程微处理器的地址指令。微处理器被编程为提供独特的地址信号用于写入使分立存储器单元。存储器单元具有写使能引脚和芯片选择引脚，当组合使能时，可以写入存储器单元。地址解码器接收唯一的地址指令，并且为该存储器单元产生写使能信号和片选信号。写使能信号和芯片选择信号分别由存储器单元的写使能引脚和芯片选择引脚接收。存储器安全电路监视存储器单元的写使能引脚和芯片选择引脚，并且当存储器单元被适当寻址时产生第一输出信号。当存储器单元未被地址解码器寻址并且写使能和芯片选择信号存在于存储器单元时，产生第二输出信号。

9. 发明授权

US5634044A Charge coupled device control module 失效
标题翻译：充电耦合器件控制模块
公开(公告)号：US5634044A
公开(公告)日：1997-05-27
申请号：US282246
申请日：1994-07-29
申请人： Young W. Lee , Sungwon Moh , Arno Muller
发明人： Young W. Lee , Sungwon Moh , Arno Muller
IPC分类号： H04N5/335 , G06F1/04
CPC分类号： H04N5/335
摘要： The control system controls the operation of a charge coupled device. The operation of the charge coupled device is responsive to a shift clock signal of a given frequency and a shift enable signal. The control system includes a timer for generating one of a number of shift clock signals. Each of the shift clock signals has a different frequency. A programmable register stores a plurality of control bits which may be programmed into the program memory of the control system. A multiplex switching is used for selecting one of the shift clock signals in response to the state of the control bits and directing the selected shift clock signal to the charge coupled device. An address decoder in response to addressing by the microprocessor, generates the shift enable signal which signal is directed to the charge coupled device concurrently with the presence of the selected shift clock signal.
摘要翻译：控制系统控制电荷耦合器件的工作。电荷耦合器件的操作响应给定频率的移位时钟信号和移位使能信号。控制系统包括用于产生多个移位时钟信号之一的定时器。每个移位时钟信号具有不同的频率。可编程寄存器存储可以被编程到控制系统的程序存储器中的多个控制位。多路开关用于响应于控制位的状态选择一个移位时钟信号，并将所选择的移位时钟信号引导到电荷耦合器件。响应于微处理器寻址的地址解码器产生与所选移位时钟信号的存在同时发送到电荷耦合器件的信号的移位使能信号。

10. 发明授权

US08055936B2 System and method for data recovery in a disabled integrated circuit 有权
标题翻译：禁用集成电路中数据恢复的系统和方法
公开(公告)号：US08055936B2
公开(公告)日：2011-11-08
申请号：US12347772
申请日：2008-12-31
申请人： Sungwon Moh , Peter A. Pagliaro
发明人： Sungwon Moh , Peter A. Pagliaro
IPC分类号： G06F11/00
CPC分类号： G06F13/16 , G06F11/2236
摘要： Systems and methods for providing memory access circuitry in application specific integrated circuits, and in certain configurations for recovering data from non-volatile memory registers in a partially disabled application specific integrated circuit as provided. In one configuration, a virtual partial dual-port non-volatile memory is provided having a secondary partial read only port. In another configuration, a physical partial dual-port non-volatile memory is provided having a secondary partial read only port.
摘要翻译：在专用集成电路中提供存储器访问电路的系统和方法，以及用于在提供的部分禁用的专用集成电路中从非易失性存储器寄存器恢复数据的某些配置。在一种配置中，提供具有次级部分只读端口的虚拟部分双端口非易失性存储器。在另一配置中，提供具有次要部分只读端口的物理部分双端口非易失性存储器。

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