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1. 发明授权

US5377264A Memory access protection circuit with encryption key 失效
标题翻译：存储器访问保护电路带加密密钥
公开(公告)号：US5377264A
公开(公告)日：1994-12-27
申请号：US163774
申请日：1993-12-09
申请人： Young W. Lee , Sungwon Moh , Arno Muller
发明人： Young W. Lee , Sungwon Moh , Arno Muller
IPC分类号： G06F12/14 , G06F21/00 , H04L9/00
CPC分类号： H04L9/32 , G06F12/1433 , G06F21/79
摘要： A data verification system including a circuit verifies that unlocking data generated by a microprocessor to be written into the ASIC before a memory write is valid. The microprocessor is programmed to generate an ASIC address when unlocking data is to be written to the ASIC and to encrypt and decrypt that data. The verifying circuit unit receives the encrypted data and decrypts the encrypted data and compares the decrypted data with the encrypted data. The verifying circuit generating an enable signal only if the comparison is true. An address decoding unit is provided for receiving the memory address signal and causing a memory write enable signal to be generated for the memory unit only if the verifying circuit unit has generated an enable signal. Registers unit in communication with the data bus and the verifying circuit unit are provided for writing decryption parameters in the register unit in accordance with the programming of the microprocessor during power-up of the microprocessor.
摘要翻译：包括电路的数据验证系统在存储器写入有效之前验证将由微处理器产生的数据解锁以写入ASIC。当解锁数据要写入ASIC并加密和解密该数据时，微处理器被编程为产生ASIC地址。验证电路单元接收加密数据并对加密数据进行解密，并将解密后的数据与加密数据进行比较。验证电路仅在比较为真时才产生使能信号。提供地址解码单元，用于接收存储器地址信号，并且仅当验证电路单元已经产生使能信号时才使存储器单元产生存储器写使能信号。提供与数据总线和验证电路单元通信的寄存器单元，用于在微处理器加电期间根据微处理器的编程将解密参数写入寄存器单元。

2. 发明授权

US5974402A Address decoder with memory wait state circuit 失效
标题翻译：地址解码器具有内存等待状态电路
公开(公告)号：US5974402A
公开(公告)日：1999-10-26
申请号：US163812
申请日：1993-12-09
申请人： Young W. Lee , Sungwon Moh , Arno Muller
发明人： Young W. Lee , Sungwon Moh , Arno Muller
IPC分类号： G06F13/16 , G07B17/00
CPC分类号： G06F13/1689 , G07B17/00193 , G07B2017/00258 , G07B2017/00395
摘要： An electronic postage meter control system having a printer for printing mixed graphic and alphanumeric information. The control system includes a programmable microprocessor in bus communication with the printer for controlling the printer and with a plurality of memory units for accounting for postage printed by the printer. The memory units include at least a first memory unit having a write access time shorter than the write access time of a second one of said memory unit, a program memory in bus communication with the programmable microprocessor having an operating program stored therein. The programmable microprocessor is able to access the operating program, an integrated circuit, the program memory, and said first and second units. The integrated circuit has an address decoding module for generating one of a plurality control signals in a unique combination in response to a respective request by the programmable microprocessor. Respective ones of the control signals are the memory write enable signals for write enabling the first or second units where write enable signals are directed to the respective memory unit. The control system further maintains the respective write enable control signals active for at least the write access time of the first memory unit in response to generation of a respective one of the write enable control signals by the address decoder. The control system further maintains the respective write enable control signal active for an additional second period such that sum period of the first period of time in combination with the second period of time is at generally equal to the write access time required by the second memory unit.
摘要翻译：一种具有用于打印混合图形和字母数字信息的打印机的电子邮资计费器控制系统。控制系统包括与打印机总线通信的可编程微处理器，用于控制打印机以及多个存储器单元，用于计算打印机打印的邮资。所述存储器单元至少包括第一存储器单元，其具有比所述存储器单元中的第二存储器单元的写入存取时间短的写访问时间，与可编程微处理器总线通信的程序存储器，其中存储有操作程序。可编程微处理器能够访问操作程序，集成电路，程序存储器以及所述第一和第二单元。集成电路具有地址解码模块，用于响应于可编程微处理器的相应请求，以独特的组合产生多个控制信号之一。控制信号中的各个是用于写入的存储器写使能信号，使能第一或第二单元，其中写使能信号被引导到相应的存储器单元。控制系统进一步维持相应的写入使能控制信号，以响应于地址解码器产生写入使能控制信号中的相应一个而至少对第一存储器单元的写入存取时间有效。控制系统进一步维持相应的写入使能控制信号在额外的第二周期中有效，使得第一时间段的结合第二时间段的和周期大体上等于第二存储器单元所需的写入时间。

3. 发明授权

US5652796A Data encryption control system 失效
标题翻译：数据加密控制系统
公开(公告)号：US5652796A
公开(公告)日：1997-07-29
申请号：US264082
申请日：1994-06-21
申请人： Thomas F. Barraza , Young W. Lee , Sungwon Moh , Arno Muller
发明人： Thomas F. Barraza , Young W. Lee , Sungwon Moh , Arno Muller
IPC分类号： H04L9/06 , H04L9/00
CPC分类号： H04L9/0625 , H04L2209/12
摘要： The data encryption system includes a first stage and a second stage data encryption engine in combination with a micro control system. The data encryption system is responsive to control signals from the micro control system. The first stage is comprised of an 8-bit bus input and output from the first stage to the second stage data encryption engine of 64-bits. The input bus of the first stage is gated to a plurality of 8-bit registers through a plurality of AND gates having a respective one of the AND gate inputs in communication with the 8-bit bus and output from the respective AND gate directed to a respective input of the respective 8-bit registers for selectively gating data from the 8-bit bus to respective ones of the 8-bit registers. A demultiplexer includes a plurality of inputs and a plurality of outputs, a respective output of the demultiplexer being in communication with the input of a respective one of the AND gates for selectively enabling a respective one of the AND gate in response to the state of the control signals.
摘要翻译：数据加密系统包括与微控制系统组合的第一级和第二级数据加密引擎。数据加密系统响应来自微控制系统的控制信号。第一级由8位总线输入和从第一级输出到64位的第二级数据加密引擎组成。第一级的输入总线通过具有与8位总线通信的与门输入中的相应一个的多个与门门控到多个8位寄存器，并从相应的与门指向一个相应的8位寄存器的输入，用于选择性地将数据从8位总线选通到8位寄存器中的相应寄存器。解复用器包括多个输入和多个输出，多路分解器的相应输出与与门的相应一个的输入通信，用于响应于所述“与”门的状态选择性地使得与门相应的一个控制信号。

4. 发明授权

US5729716A Memory monitoring circuit for detecting unauthorized memory access 失效
标题翻译：用于检测未经授权的存储器访问的存储器监视电路
公开(公告)号：US5729716A
公开(公告)日：1998-03-17
申请号：US648454
申请日：1996-05-15
申请人： Young W. Lee , Sungwon Moh , Arno Muller
发明人： Young W. Lee , Sungwon Moh , Arno Muller
IPC分类号： G06F12/14 , G06F21/00 , G06F12/16
CPC分类号： G06F21/79 , G06F12/1433
摘要： The memory security circuit detects when a memory unit has been accessed independently of an address instruction of a programmable microprocessor. The microprocessor is programmed to provide a unique address signal for write enabling a discrete memory unit. The memory unit has a write enable pin and chip select pin which when enabled in combination permits writing into the memory unit. The address decoder receives the unique address instruction and causes a write enable signal and a chip select signal to be generated for that memory unit. The write enable signal and chip select signal are to be received, respectively, by the write enable pin and the chip select pin of the memory unit. The memory security circuit monitors the write enable pin and the chip select pin of the memory unit and generates a first output signal when the memory unit has been properly addressed. A second output signal is generated when the memory unit has not been addressed by the address decoder and the write enable and the chip select signals are present at the memory unit.
摘要翻译：存储器安全电路检测存储器单元何时被访问，独立于可编程微处理器的地址指令。微处理器被编程为提供独特的地址信号用于写入使分立存储器单元。存储器单元具有写使能引脚和芯片选择引脚，当组合使能时，可以写入存储器单元。地址解码器接收唯一的地址指令，并且为该存储器单元产生写使能信号和片选信号。写使能信号和芯片选择信号分别由存储器单元的写使能引脚和芯片选择引脚接收。存储器安全电路监视存储器单元的写使能引脚和芯片选择引脚，并且当存储器单元被适当寻址时产生第一输出信号。当存储器单元未被地址解码器寻址并且写使能和芯片选择信号存在于存储器单元时，产生第二输出信号。

5. 发明授权

US5634044A Charge coupled device control module 失效
标题翻译：充电耦合器件控制模块
公开(公告)号：US5634044A
公开(公告)日：1997-05-27
申请号：US282246
申请日：1994-07-29
申请人： Young W. Lee , Sungwon Moh , Arno Muller
发明人： Young W. Lee , Sungwon Moh , Arno Muller
IPC分类号： H04N5/335 , G06F1/04
CPC分类号： H04N5/335
摘要： The control system controls the operation of a charge coupled device. The operation of the charge coupled device is responsive to a shift clock signal of a given frequency and a shift enable signal. The control system includes a timer for generating one of a number of shift clock signals. Each of the shift clock signals has a different frequency. A programmable register stores a plurality of control bits which may be programmed into the program memory of the control system. A multiplex switching is used for selecting one of the shift clock signals in response to the state of the control bits and directing the selected shift clock signal to the charge coupled device. An address decoder in response to addressing by the microprocessor, generates the shift enable signal which signal is directed to the charge coupled device concurrently with the presence of the selected shift clock signal.
摘要翻译：控制系统控制电荷耦合器件的工作。电荷耦合器件的操作响应给定频率的移位时钟信号和移位使能信号。控制系统包括用于产生多个移位时钟信号之一的定时器。每个移位时钟信号具有不同的频率。可编程寄存器存储可以被编程到控制系统的程序存储器中的多个控制位。多路开关用于响应于控制位的状态选择一个移位时钟信号，并将所选择的移位时钟信号引导到电荷耦合器件。响应于微处理器寻址的地址解码器产生与所选移位时钟信号的存在同时发送到电荷耦合器件的信号的移位使能信号。

6. 发明授权

US5664123A Digital communication I/O port 失效
标题翻译：数字通信I / O口
公开(公告)号：US5664123A
公开(公告)日：1997-09-02
申请号：US301086
申请日：1994-09-06
申请人： Young W. Lee , Sungwon Moh , Arno Muller
发明人： Young W. Lee , Sungwon Moh , Arno Muller
IPC分类号： H04L29/00 , G06F11/267 , G06F13/40 , H04L29/10 , G06F13/00
CPC分类号： G06F11/2221 , G06F13/4022
摘要： A micro control system includes a programmable microcontroller which is in bus communication with memory units and a operating power supply for providing operating power to said microcontroller. A communication module is part of the micro control system and is in communication with the data bus of the micro control system for receiving and transmitting data messages to an external device, and for encoding said transmitted data messages to conform to a serial communication protocol and decoding said received data messages. The microcontroller is programmed to generated a first control signal or a second control signal. An input-output interface is included as part of the micro control system and includes a number of switching units responsive to the first control signal of the microcontroller to place the respective switching units in a first mode of operation for providing communication between said communication module and a connector. The switching units also respond to said second control signal from the microcontroller to place said switching units in a second mode of operation for providing communication between said data bus of the micro control system and said connector to which connector the external device is attached.
摘要翻译：微控制系统包括与存储器单元进行总线通信的可编程微控制器和用于向所述微控制器提供工作电源的工作电源。通信模块是微控制系统的一部分，并且与微控制系统的数据总线通信，用于向外部设备接收和发送数据消息，并且对所发送的数据消息进行编码以符合串行通信协议和解码表示收到的数据信息。微控制器被编程为产生第一控制信号或第二控制信号。输入输出接口被包括在微控制系统的一部分中，并且包括响应于微控制器的第一控制信号的多个开关单元，以将相应的开关单元放置在第一操作模式中，以提供所述通信模块与连接器开关单元还响应来自微控制器的所述第二控制信号，以将所述开关单元放置在第二操作模式中，以提供微控制系统的所述数据总线与外部设备连接到的连接器的所述连接器之间的通信。

7. 发明授权

US5530840A Address decoder with memory allocation for a micro-controller system 失效
标题翻译：地址解码器，具有用于微控制器系统的存储器分配
公开(公告)号：US5530840A
公开(公告)日：1996-06-25
申请号：US163790
申请日：1993-12-09
申请人： Young W. Lee , Sungwon Moh , Arno Muller
发明人： Young W. Lee , Sungwon Moh , Arno Muller
IPC分类号： G06F12/06 , G07B17/00
CPC分类号： G07B17/00193 , G06F12/0653 , G07B2017/00258 , G07B2017/00395
摘要： The micro-controller system is comprised of a programmable microprocessor, a plurality of memory units having a plurality of addressable memory registers. The memory units are in bus communication with the programmable processor and an application specific integrated circuit. The application specific integrated circuit includes a circuit for dividing the memory units into a plurality of addressable regions in response to programming of the programmable microprocessor. The microprocessor is programmed such that the initial address for each of the regions is assigned by the most significant address bits, and the uppermost address for the region being programmably defined by an uppermost address for the respective region. The circuit includes a plurality of addressable registers. The microprocessor can address each of the circuit registers and write a respective uppermost address in a respective one of the registers, the respective address corresponding to uppermost addressable registers of the respective addressable regions of the memory units.
摘要翻译：微控制器系统包括可编程微处理器，具有多个可寻址存储器寄存器的多个存储器单元。存储器单元与可编程处理器和专用集成电路进行总线通信。专用集成电路包括用于响应于可编程微处理器的编程将存储器单元划分成多个可寻址区域的电路。微处理器被编程为使得每个区域的初始地址由最高有效地址位分配，并且该区域的最高地址由可编程地由相应区域的最高地址限定。该电路包括多个可寻址寄存器。微处理器可以对每个电路寄存器进行寻址，并在相应的一个寄存器中写入相应的最上面的地址，相应的地址对应于存储器单元的各个可寻址区域的最高可寻址寄存器。

8. 发明授权

US5475621A Dual mode timer-counter 失效
标题翻译：双模定时器 - 计数器
公开(公告)号：US5475621A
公开(公告)日：1995-12-12
申请号：US165134
申请日：1993-12-09
申请人： Young W. Lee , Sungwon Moh , Arno Muller
发明人： Young W. Lee , Sungwon Moh , Arno Muller
IPC分类号： G04G15/00 , G06F17/00
CPC分类号： G04G15/003
摘要： A programmable timer circuit which is integrated into an application specific integrated circuit includes a programmable timer counter. The programmable timer counter receives count data which is written to registers of the integrated circuit and is caused to initiate a count until that count is reached in response to clock signal. A programmable microprocessor is provided for controlling the programmable timer circuit and reading count data and mode data from non-volatile memory units in response to the microprocessor's programming and writing the count data and mode data into the registers of the application specific integrated circuit. In response to the mode data the programmable timer circuit assumes either a one shot mode or a continuos mode when the programmable timer.
摘要翻译：集成到专用集成电路中的可编程定时器电路包括可编程定时器计数器。可编程定时器计数器接收被写入集成电路的寄存器的计数数据，并且响应于时钟信号而被引起计数，直到达到该计数。提供了可编程微处理器，用于控制可编程定时器电路，并响应于微处理器的编程并将计数数据和模式数据写入专用集成电路的寄存器，从非易失性存储器单元读取计数数据和模式数据。响应于模式数据，当可编程定时器时，可编程定时器电路采用单触发模式或连续模式。

9. 发明授权

US5471608A Dynamically programmable timer-counter having enable mode for timer data load and monitoring circuit to allow enable mode only upon time-out 失效
标题翻译：动态可编程定时器计数器具有定时器数据加载和监视电路的使能模式，仅在超时时允许使能模式
公开(公告)号：US5471608A
公开(公告)日：1995-11-28
申请号：US137460
申请日：1993-12-09
申请人： Young W. Lee , Sungwon Moh , Arno Muller
发明人： Young W. Lee , Sungwon Moh , Arno Muller
IPC分类号： G04F1/00 , G06F9/318
CPC分类号： G04F1/005
摘要： A programmable timer circuit is comprised of a programmable timer counter for receiving a count and for counting to the count. A clock signal for driving the timer counter which timer counter generates a signal representative of the count. A microprocessor generates count data in response to programming of the microprocessor. Timer data register receive the count from microprocessor. A first gate is provided having an enabled mode and an non-enabled mode for enabling loading of the timer data from the timer data register to the timer counter input only in the enabled mode. A monitoring circuit is provided for monitoring the timer count and enabling the gate mean to the enabled mode only when the timer has time-out.
摘要翻译：可编程定时器电路由可编程定时器计数器组成，用于接收计数和计数。用于驱动定时器计数器的时钟信号，定时器计数器产生代表计数的信号。微处理器响应于微处理器的编程而产生计数数据。定时器数据寄存器从微处理器接收计数。提供具有启用模式和非启用模式的第一门，用于仅在启用模式中使定时器数据从定时器数据寄存器加载到定时器计数器输入。提供监控电路，用于监视定时器计数，并且只有当定时器超时时，才将门电平启用为使能模式。

10. 发明授权

US5732245A Multi-memory access limiting circuit for a multi-memory device 失效
标题翻译：用于多存储器设备的多存储器存取限制电路
公开(公告)号：US5732245A
公开(公告)日：1998-03-24
申请号：US631439
申请日：1996-04-12
申请人： Young W. Lee , Sungwon Moh , Arno Muller
发明人： Young W. Lee , Sungwon Moh , Arno Muller
IPC分类号： G06F11/00 , G06F11/07 , G07B17/00 , G06F12/16
CPC分类号： G06F11/073 , G06F11/004 , G06F11/0751 , G07B17/00314 , G07B17/00362 , G07B2017/00338 , G07B2017/00395 , G07B2017/00403
摘要： The memory access limiting circuit detects when two or more of memory units associated with a microprocessor control system have been accessed enabled concurrently representing an error condition. The memory access limiting circuit is part of an integrated circuit. The integrated circuit also includes an address decoding for receiving the unique address signal and causing a write enable signal to be generated for the memory units and one of a plurality chip select signals to be generated for a respective one of the memory units. The monitoring circuit monitors the pin levels of the integrated circuit assigned for enabling the respective memory unit. The monitoring circuit generates a first output signal when a respective one of the memory unit chip select signals has been enabled and a second output signal when a plurality of chip select signals have been enabled. The second output signal is directed to the microprocessor for corrective action.
摘要翻译：存储器访问限制电路检测何时已经访问与微处理器控制系统相关联的两个或更多个存储单元，同时表示错误状况。存储器访问限制电路是集成电路的一部分。集成电路还包括用于接收唯一地址信号的地址解码，并且为存储器单元生成写入使能信号，并且为存储器单元中的相应一个产生多个芯片选择信号之一。监视电路监视被分配用于启用相应存储器单元的集成电路的引脚电平。当已经使能存储单元芯片选择信号中的相应一个时，监视电路产生第一输出信号，并且当多个芯片选择信号被使能时，监视电路产生第二输出信号。第二个输出信号被引导到微处理器进行纠正。

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