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1. 发明授权

US08555234B2 Verification of soft error resilience 失效
标题翻译：验证软错误弹性
公开(公告)号：US08555234B2
公开(公告)日：2013-10-08
申请号：US12553224
申请日：2009-09-03
申请人： Robert Brett Tremaine , Mark Anthony Check , Pia N Sanda , Prabhakar Nandavar Kudva
发明人： Robert Brett Tremaine , Mark Anthony Check , Pia N Sanda , Prabhakar Nandavar Kudva
IPC分类号： G06F17/50
CPC分类号： G06F11/263
摘要： An efficient method for selecting a minimal and statistically relevant set of SER sensitive logic devices critical to the SER robustness for a design, through identification by device type, identification nomenclature, connectivity and context. The minimal set of devices comprise the set of fault injection test points using a conventional fault injection test verification environment to establish an SER induced failure rate a logic design. The selection method affords a design independent means to evaluate any design regardless of the origin, source language or documentation by working at the common logic device level “gate-level” netlist format for the design data. The selected set of devices is distilled from the design data by successively filtering the design through a series of heuristic rule-based device identifier computer programs that group and annotate the devices into specific database records. These records are then used to organize the fault injection device test set by test behavior and relevance.
摘要翻译：一种有效的方法，用于通过设备类型识别，识别命名，连通性和上下文来选择对设计的SER鲁棒性至关重要的SER敏感逻辑器件的最小和统计相关的集合。最小的设备组包括使用常规故障注入测试验证环境来建立SER引起的故障率逻辑设计的故障注入测试点的集合。选择方法提供了一种设计独立的方法来评估任何设计，无论原点，源语言或文档如何，通过在设计数据的通用逻辑器件级“门级”网表格格式下工作。通过将一组基于启发式规则的设备标识符计算机程序连续地过滤设计，将设备数据从设计数据中解析出来，从而将设备分组和注释到特定的数据库记录中。然后，这些记录用于通过测试行为和相关性组织故障注入设备测试集。

2. 发明申请

US20110055777A1 Verification of Soft Error Resilience 失效
标题翻译：验证软错误弹性
公开(公告)号：US20110055777A1
公开(公告)日：2011-03-03
申请号：US12553224
申请日：2009-09-03
申请人： Robert Brett Tremaine , Mark Anthony Check , Pia N. Sanda , Prabhakar Nandavar Kudva
发明人： Robert Brett Tremaine , Mark Anthony Check , Pia N. Sanda , Prabhakar Nandavar Kudva
IPC分类号： G06F17/50
CPC分类号： G06F11/263
摘要： An efficient method for selecting a minimal and statistically relevant set of SER sensitive logic devices critical to the SER robustness for a design, through identification by device type, identification nomenclature, connectivity and context. The minimal set of devices comprise the set of fault injection test points using a conventional fault injection test verification environment to establish an SER induced failure rate a logic design. The selection method affords a design independent means to evaluate any design regardless of the origin, source language or documentation by working at the common logic device level “gate-level” netlist format for the design data. The selected set of devices is distilled from the design data by successively filtering the design through a series of heuristic rule-based device identifier computer programs that group and annotate the devices into specific database records. These records are then used to organize the fault injection device test set by test behavior and relevance.
摘要翻译：一种有效的方法，用于通过设备类型识别，识别命名，连通性和上下文来选择对设计的SER鲁棒性至关重要的SER敏感逻辑器件的最小和统计相关的集合。最小的设备组包括使用常规故障注入测试验证环境来建立SER引起的故障率逻辑设计的故障注入测试点的集合。选择方法提供了一种设计独立的方法来评估任何设计，无论原点，源语言或文档如何，通过在设计数据的通用逻辑器件级“门级”网表格格式下工作。通过将一组基于启发式规则的设备标识符计算机程序连续地过滤设计，将设备数据从设计数据中解析出来，从而将设备分组和注释到特定的数据库记录中。然后，这些记录用于通过测试行为和相关性组织故障注入设备测试集。

3. 发明授权

US6090153A Multi-threshold-voltage differential cascode voltage switch (DCVS) circuits 失效
标题翻译：多门限电压差分共源共栅电压开关（DCVS）电路
公开(公告)号：US6090153A
公开(公告)日：2000-07-18
申请号：US985367
申请日：1997-12-05
申请人： Wei Chen , Wei Hwang , Prabhakar Nandavar Kudva
发明人： Wei Chen , Wei Hwang , Prabhakar Nandavar Kudva
IPC分类号： G06F17/50 , H03K19/173
CPC分类号： H03K19/1738 , G06F17/505
摘要： A differential cascode voltage switch circuit includes a plurality of devices wherein a portion of the plurality of devices have a low threshold voltage and a remainder of the plurality devices have a regular threshold voltage for providing a performance gain without a substantial increase in standby power wherein at least one device has regular threshold voltage between a supply voltage and a ground. A method of producing a multi-threshold voltage circuit includes the steps of defining between a supply voltage node and ground at least one regular threshold voltage device for producing a high resistance to reduce current leakage and defining low threshold voltage devices within the circuit for reducing leakage current.
摘要翻译：差分共源共栅电压开关电路包括多个器件，其中多个器件的一部分具有低阈值电压，并且多个器件的其余部分具有用于提供性能增益的规则阈值电压，而不增加待机功率，其中at 至少一个装置在电源电压和地之间具有规则的阈值电压。一种产生多阈值电压电路的方法包括以下步骤：在电源电压节点和接地之间限定至少一个规则阈值电压装置，用于产生高电阻以减少电流泄漏并且限定电路内的低阈值电压装置以减少泄漏当前。

4. 发明授权

US08073668B2 Method and apparatus for testing a full system integrated circuit design by statistical fault injection using hardware-based simulation 有权
标题翻译：使用基于硬件的仿真通过统计故障注入测试全系统集成电路设计的方法和装置
公开(公告)号：US08073668B2
公开(公告)日：2011-12-06
申请号：US12022869
申请日：2008-01-30
申请人： Jeffrey William Kellington , Prabhakar Nandavar Kudva , Naoko Pia Sanda , John Andrew Schumann
发明人： Jeffrey William Kellington , Prabhakar Nandavar Kudva , Naoko Pia Sanda , John Andrew Schumann
IPC分类号： G06F17/50 , G06F11/00
CPC分类号： G06F11/261 , G01R31/31816
摘要： A test system tests a full system integrated circuit (IC) model that includes a device under test (DUT) IC model and a support IC model. A test manager information handling system (IHS) maps the full system IC model on a hardware accelerator simulator via an interface bus. The hardware accelerator simulator thus emulates the full system IC model. Of all possible fault injection points in the model, the test manager IHS selects a subset of those injection points for fault injection via a statistical sampling method in one embodiment. In response to commands from the test manager IHS, the simulator serially injects faults into the selected fault injection points. The test manager IHS stores results for respective fault injections at the selected injection points. If a machine checkstop or silent data corruption error occurs as a result of an injected fault, the DUT IC model may return to a stored checkpoint and resume operation from the stored checkpoint. The result information is useful in determining a soft error rate (SER) for the DUT IC.
摘要翻译：测试系统测试包括被测设备（DUT）IC模型和支持IC模型的全系统集成电路（IC）模型。测试管理器信息处理系统（IHS）通过接口总线在硬件加速器模拟器上映射完整的系统IC模型。因此，硬件加速器模拟器仿真全系统IC模型。在模型中的所有可能的故障注入点中，测试管理器IHS在一个实施例中通过统计采样方法来选择用于故障注入的那些注入点的子集。为了响应来自测试管理器IHS的命令，模拟器将故障序列注入所选择的故障注入点。测试经理IHS存储在所选注入点处各自故障注入的结果。如果由于注入故障而发生机器检查停止或无声数据损坏错误，则DUT IC模型可能返回到存储的检查点，并从存储的检查点恢复操作。结果信息可用于确定DUT IC的软错误率（SER）。

5. 发明申请

US20090193296A1 Method and Apparatus for Testing a Full System Integrated Circuit Design by Statistical Fault Injection Using Hardware-Based Simulation 有权
标题翻译：使用基于硬件的仿真通过统计故障注入测试全系统集成电路设计的方法和装置
公开(公告)号：US20090193296A1
公开(公告)日：2009-07-30
申请号：US12022869
申请日：2008-01-30
申请人： Jeffrey William Kellington , Prabhakar Nandavar Kudva , Naoko Pia Sanda , John Andrew Schumann
发明人： Jeffrey William Kellington , Prabhakar Nandavar Kudva , Naoko Pia Sanda , John Andrew Schumann
IPC分类号： G06F11/07 , G06F17/50
CPC分类号： G06F11/261 , G01R31/31816
摘要： A test system tests a full system integrated circuit (IC) model that includes a device under test (DUT) IC model and a support IC model. A test manager information handling system (IHS) maps the full system IC model on a hardware accelerator simulator via an interface bus. The hardware accelerator simulator thus emulates the full system IC model. Of all possible fault injection points in the model, the test manager IHS selects a subset of those injection points for fault injection via a statistical sampling method in one embodiment. In response to commands from the test manager IHS, the simulator serially injects faults into the selected fault injection points. The test manager IHS stores results for respective fault injections at the selected injection points. If a machine checkstop or silent data corruption error occurs as a result of an injected fault, the DUT IC model may return to a stored checkpoint and resume operation from the stored checkpoint. The result information is useful in determining a soft error rate (SER) for the DUT IC.
摘要翻译：测试系统测试包括被测设备（DUT）IC模型和支持IC模型的全系统集成电路（IC）模型。测试管理器信息处理系统（IHS）通过接口总线在硬件加速器模拟器上映射完整的系统IC模型。因此，硬件加速器模拟器仿真全系统IC模型。在模型中的所有可能的故障注入点中，测试管理器IHS在一个实施例中通过统计采样方法来选择用于故障注入的那些注入点的子集。为了响应来自测试管理器IHS的命令，模拟器将故障序列注入所选择的故障注入点。测试经理IHS存储在所选注入点处各自故障注入的结果。如果由于注入故障而发生机器检查停止或无声数据损坏错误，则DUT IC模型可能返回到存储的检查点，并从存储的检查点恢复操作。结果信息可用于确定DUT IC的软错误率（SER）。

6. 发明授权

US07047163B1 Method and apparatus for applying fine-grained transforms during placement synthesis interaction 失效
标题翻译：在放置合成相互作用期间应用细粒度变换的方法和装置
公开(公告)号：US07047163B1
公开(公告)日：2006-05-16
申请号：US09524408
申请日：2000-03-13
申请人： Kanad Chakraborty , Wilm Ernst Donath , Prabhakar Nandavar Kudva , Lakshmi Narasimha Reddy , Leon Stok , Andrew James Sullivan , Paul Gerard Villarrubia
发明人： Kanad Chakraborty , Wilm Ernst Donath , Prabhakar Nandavar Kudva , Lakshmi Narasimha Reddy , Leon Stok , Andrew James Sullivan , Paul Gerard Villarrubia
IPC分类号： G06F17/10 , G06F7/60 , G06F15/18 , G06G7/00 , G06N3/00
CPC分类号： G06F17/5045 , G06F17/5072
摘要： A method (and system) of applying transforms for modifying a plurality of domains concurrently in a design space, includes creating a sequence of more and less granular placement and netlist modification transforms. A converging design process flow is created by a flexible mechanism in which a select combination of fine-grained transforms are applied to optimize the netlist and placement of a design.
摘要翻译：在设计空间中同时应用用于修改多个域的变换的方法（和系统）包括创建越来越少的粒度位置和网表修改变换的序列。融合设计流程由灵活的机制创建，其中应用细粒度变换的选择组合来优化设计的网表和布局。

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