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1. 发明申请

US20090193296A1 Method and Apparatus for Testing a Full System Integrated Circuit Design by Statistical Fault Injection Using Hardware-Based Simulation 有权
标题翻译：使用基于硬件的仿真通过统计故障注入测试全系统集成电路设计的方法和装置
公开(公告)号：US20090193296A1
公开(公告)日：2009-07-30
申请号：US12022869
申请日：2008-01-30
申请人： Jeffrey William Kellington , Prabhakar Nandavar Kudva , Naoko Pia Sanda , John Andrew Schumann
发明人： Jeffrey William Kellington , Prabhakar Nandavar Kudva , Naoko Pia Sanda , John Andrew Schumann
IPC分类号： G06F11/07 , G06F17/50
CPC分类号： G06F11/261 , G01R31/31816
摘要： A test system tests a full system integrated circuit (IC) model that includes a device under test (DUT) IC model and a support IC model. A test manager information handling system (IHS) maps the full system IC model on a hardware accelerator simulator via an interface bus. The hardware accelerator simulator thus emulates the full system IC model. Of all possible fault injection points in the model, the test manager IHS selects a subset of those injection points for fault injection via a statistical sampling method in one embodiment. In response to commands from the test manager IHS, the simulator serially injects faults into the selected fault injection points. The test manager IHS stores results for respective fault injections at the selected injection points. If a machine checkstop or silent data corruption error occurs as a result of an injected fault, the DUT IC model may return to a stored checkpoint and resume operation from the stored checkpoint. The result information is useful in determining a soft error rate (SER) for the DUT IC.
摘要翻译：测试系统测试包括被测设备（DUT）IC模型和支持IC模型的全系统集成电路（IC）模型。测试管理器信息处理系统（IHS）通过接口总线在硬件加速器模拟器上映射完整的系统IC模型。因此，硬件加速器模拟器仿真全系统IC模型。在模型中的所有可能的故障注入点中，测试管理器IHS在一个实施例中通过统计采样方法来选择用于故障注入的那些注入点的子集。为了响应来自测试管理器IHS的命令，模拟器将故障序列注入所选择的故障注入点。测试经理IHS存储在所选注入点处各自故障注入的结果。如果由于注入故障而发生机器检查停止或无声数据损坏错误，则DUT IC模型可能返回到存储的检查点，并从存储的检查点恢复操作。结果信息可用于确定DUT IC的软错误率（SER）。

2. 发明授权

US08073668B2 Method and apparatus for testing a full system integrated circuit design by statistical fault injection using hardware-based simulation 有权
标题翻译：使用基于硬件的仿真通过统计故障注入测试全系统集成电路设计的方法和装置
公开(公告)号：US08073668B2
公开(公告)日：2011-12-06
申请号：US12022869
申请日：2008-01-30
申请人： Jeffrey William Kellington , Prabhakar Nandavar Kudva , Naoko Pia Sanda , John Andrew Schumann
发明人： Jeffrey William Kellington , Prabhakar Nandavar Kudva , Naoko Pia Sanda , John Andrew Schumann
IPC分类号： G06F17/50 , G06F11/00
CPC分类号： G06F11/261 , G01R31/31816
摘要： A test system tests a full system integrated circuit (IC) model that includes a device under test (DUT) IC model and a support IC model. A test manager information handling system (IHS) maps the full system IC model on a hardware accelerator simulator via an interface bus. The hardware accelerator simulator thus emulates the full system IC model. Of all possible fault injection points in the model, the test manager IHS selects a subset of those injection points for fault injection via a statistical sampling method in one embodiment. In response to commands from the test manager IHS, the simulator serially injects faults into the selected fault injection points. The test manager IHS stores results for respective fault injections at the selected injection points. If a machine checkstop or silent data corruption error occurs as a result of an injected fault, the DUT IC model may return to a stored checkpoint and resume operation from the stored checkpoint. The result information is useful in determining a soft error rate (SER) for the DUT IC.
摘要翻译：测试系统测试包括被测设备（DUT）IC模型和支持IC模型的全系统集成电路（IC）模型。测试管理器信息处理系统（IHS）通过接口总线在硬件加速器模拟器上映射完整的系统IC模型。因此，硬件加速器模拟器仿真全系统IC模型。在模型中的所有可能的故障注入点中，测试管理器IHS在一个实施例中通过统计采样方法来选择用于故障注入的那些注入点的子集。为了响应来自测试管理器IHS的命令，模拟器将故障序列注入所选择的故障注入点。测试经理IHS存储在所选注入点处各自故障注入的结果。如果由于注入故障而发生机器检查停止或无声数据损坏错误，则DUT IC模型可能返回到存储的检查点，并从存储的检查点恢复操作。结果信息可用于确定DUT IC的软错误率（SER）。

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