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1. 发明授权

US6105126A Address bit decoding for same adder circuitry for RXE instruction format with same XBD location as RX format and dis-jointed extended operation code 失效
标题翻译：地址比特解码用于RXE指令格式的相同加法器电路，具有与RX格式相同的XBD位置和解码的扩展操作码
公开(公告)号：US6105126A
公开(公告)日：2000-08-15
申请号：US70359
申请日：1998-04-30
申请人： Mark Anthony Check , Ronald M. Smith, Sr. , John Stephen Liptay , Eric Mark Schwarz , Timothy John Slegel , Charles Franklin Webb
发明人： Mark Anthony Check , Ronald M. Smith, Sr. , John Stephen Liptay , Eric Mark Schwarz , Timothy John Slegel , Charles Franklin Webb
IPC分类号： G06F9/355 , G06F9/30 , G06F9/318 , G06F9/38 , G06F9/34
CPC分类号： G06F9/355 , G06F9/30185
摘要： A computer processor floating point processor six cycle pipeline system where instruction text is fetched prior to the first cycle and decoded during the first cycle for the fetched particular instruction and the base (B) and index (X) register values are read for use in address generation. RXE Instructions are of the RX-type but extended by placing the extension of the operation code beyond the first four bytes of the instruction format and to assign the operation codes in such a way that the machine may determine the exact format from the first 8 bits of the operation code alone. ESA/390 instructions SS, RR; RX; S; RRE; RI; and the new RXE instructions have a format which can be used for fixed point processing as well as floating point processing where instructions of the RXE format have their R1, X2, B2, and D2 fields in the identical positions in said instruction register as in the RX format to enable the processor to determine from the first 8 bits of the operation code alone that an instruction being decoded is an RXE format instruction and the register indexed extensions of the RXE format instruction, after which it gates the correct information to said X-B-D adder. During the second cycle the address add of B+X+Displacement is performed and sent to the cache processor's, and during the third and fourth cycles the cache is respectively accessed and data is returned, and during a fifth cycle execution of the fetched instruction occurs with the result putaway in a sixth cycle.
摘要翻译：计算机处理器浮点处理器六循环流水线系统，其中指令文本在第一周期之前获取并且在第一周期期间被解码用于所提取的特定指令，并且基准（B）和索引（X）寄存器值被读取用于地址代。 RXE指令是RX型，但通过将操作码的扩展置于指令格式的前四个字节之外进行扩展，并以这样的方式分配操作码，使得机器可以从前8位确定确切的格式的操作代码。 ESA / 390指令SS，RR; RX; S; RRE; RI; 并且新的RXE指令具有可用于固定点处理以及浮点处理的格式，其中RXE格式的指令在所述指令寄存器中的相同位置具有其R1，X2，B2和D2字段，如 RX格式，使处理器能够从操作代码的前8位确定正在解码的指令是RXE格式指令和RXE格式指令的寄存器索引扩展，之后它将正确信息锁定到所述XBD加法器。在第二周期期间，执行B + X +位移的地址添加并发送到高速缓存处理器，并且在第三和第四周期期间，分别访问高速缓存并返回数据，并且在第五周期期间执行所取出的指令结果放在第六个周期。

2. 发明授权

US5694587A Specialized millicode instructions for test PSW validity, load with access test, and character translation assist 失效
标题翻译：测试PSW有效性的专用millicode指令，访问测试负载和字符翻译辅助
公开(公告)号：US5694587A
公开(公告)日：1997-12-02
申请号：US414154
申请日：1995-03-31
申请人： Charles Franklin Webb , Mark Steven Farrell , Mark Anthony Check , John Stephen Liptay
发明人： Charles Franklin Webb , Mark Steven Farrell , Mark Anthony Check , John Stephen Liptay
IPC分类号： G06F9/30 , G06F9/305 , G06F9/318 , G06F9/38 , G06F11/07
CPC分类号： G06F9/3865 , G06F11/0721 , G06F11/0751 , G06F9/30029 , G06F9/30087 , G06F9/30145 , G06F9/3017 , G06F9/30189
摘要： A pipelined computer processor in a milli-mode architected state tests the validity of a program status word with a mask stored in a millicode general register. The mask indicates bits in the program status word which are to be zeros if the word is valid. A logical AND operation is performed between correspondingly positioned bits in the word and bits in the mask and in addition the status of at least one other bit in the word is checked, a bit other than a correspondingly positioned bit.
摘要翻译：在毫模式架构状态下的流水线计算机处理器使用存储在毫通通用寄存器中的掩码测试程序状态字的有效性。掩码表示程序状态字中的位，如果该字有效，则它们将为零。在字中的相应位置的位和掩码中的位之间执行逻辑“与”运算，另外检查字中的至少一个其他位的状态，除了对应定位的位之外的位。

3. 发明授权

US6138215A Method for absolute address history table synonym resolution 失效
标题翻译：绝对地址历史表方法同义词解析
公开(公告)号：US6138215A
公开(公告)日：2000-10-24
申请号：US70575
申请日：1998-04-30
申请人： Mark Anthony Check , Jane Helen Bartik
发明人： Mark Anthony Check , Jane Helen Bartik
IPC分类号： G06F12/10
CPC分类号： G06F12/1054 , G06F12/0888
摘要： A computer processor that uses an AAHT to provide a guess at the real (absolute) address bits used to access the cache and directories that is more accurate in a high-frequency design which prevents any sort of full or large partial adds of ranges of base, index, or displacement has two index values generated and two AAHT arrays, one each for instruction and operand logical requests. It handles cases in which the data is not directly from the GPR array. For designs that aim at improving performance data for some operations that update GPR's may be used for address generation prior to the execution and write to the GPR array, these include data bypass for Load Address (LA) and Load (L). The system handles instruction fetches, relative branches, other special instruction address instruction fetch requests, and those started as a result of a branch history table (BHT) predicted instruction fetch. A method for AAHT synonym resolution improves the accuracy of the index value for an Absolute Address History Table buffer.
摘要翻译：使用AAHT的计算机处理器提供用于访问高速缓存的实际（绝对）地址位和在高频设计中更准确的目录的猜测，其防止基站范围的任何类型的全部或大部分增加，索引或位移具有两个生成的索引值和两个AAHT数组，一个用于指令和操作数逻辑请求。它处理数据不直接来自GPR数组的情况。对于旨在改进性能数据的设计，更新GPR可能会在执行和写入GPR阵列之前产生地址，这些操作包括负载地址（LA）和负载（L）的数据旁路。系统处理指令提取，相对分支，其他特殊指令地址指令取出请求以及作为分支历史表（BHT）预测指令获取结果启动的指令。 AAHT同义词分辨率的方法提高了绝对地址历史记录表缓冲区的索引值的准确性。

4. 发明授权

US6085313A Computer processor system for executing RXE format floating point instructions 失效
标题翻译：用于执行RXE格式浮点指令的计算机处理器系统
公开(公告)号：US6085313A
公开(公告)日：2000-07-04
申请号：US070198
申请日：1998-04-30
申请人： Mark Anthony Check , Ronald M. Smith, Sr. , John Stephen Liptay , Eric Mark Schwarz , Timothy John Slegel , Charles Franklin Webb
发明人： Mark Anthony Check , Ronald M. Smith, Sr. , John Stephen Liptay , Eric Mark Schwarz , Timothy John Slegel , Charles Franklin Webb
IPC分类号： G06F9/355 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30145
摘要： A computer processor system having a floating point processor for instructions which are processed in a six cycle pipeline, in which prior to the first cycle of the pipeline an instruction text is fetched, and during the first cycle for the fetched particular instruction it is decoded and the base (B) and index (X) register values are read for use in address generation. Instructions of the RX-type are extended by placing the extension of the operation code beyond the first four bytes of the instruction format and to assign the operation codes in such a way that the machine may determine from the first 8 bits of the operation code alone, the exact format of the instruction. Instructions formats include the ESA/390 instructions SS, RR; RX; S; RRE; RI: and the new RXE instructions. where instructions of the RXE format have their R.sub.1, X.sub.2, B.sub.2, and D.sub.2 fields in the identical positions in said instruction register as in the RX format to enable the processor to determine from the first 8 bits of the operation code alone that an instruction being decoded is an RXE format instruction and the register indexed extensions of the RXE format instruction, after which it gates the correct information to said X-B-D adder. During the second cycle the address add of B+X+Displacement is performed and sent to the cache processor's, and during the third and fourth cycles the cache is respectively accessed and data is returned, and during a fifth cycle execution of the fetched instruction occurs with the result putaway in a sixth cycle.RXE instructions can be used for floating point processing and fixed point processing.
摘要翻译：一种计算机处理器系统，具有用于指令的浮点处理器，其在六个周期流水线中被处理，其中在流水线的第一周期之前取出指令文本，并且在所读取的特定指令的第一周期期间对其进行解码，读取基地址（B）和索引（X）寄存器值以用于地址生成。通过将操作代码的扩展置于指令格式的前四个字节之外来扩展RX类型的指令，并且以这样的方式分配操作代码，使得机器可以仅从操作代码的前8位确定，指令的确切格式。指令格式包括ESA / 390指令SS，RR; RX; S; RRE; RI：和新的RXE指令。其中RXE格式的指令在RX格式中在所述指令寄存器中的相同位置具有它们的R1，X2，B2和D2字段，以使处理器仅从操作代码的前8位确定指令为解码的是RXE格式指令和RXE格式指令的寄存器索引扩展，然后将正确的信息写入所述XBD加法器。在第二周期期间，执行B + X +位移的地址添加并发送到高速缓存处理器，并且在第三和第四周期期间，分别访问高速缓存并返回数据，并且在第五周期期间执行所提取的指令结果放在第六个循环中.RXE指令可用于浮点处理和定点处理。

5. 发明授权

US6035392A Computer with optimizing hardware for conditional hedge fetching into cache storage 失效
标题翻译：具有优化硬件的计算机，用于将条件对冲提取到高速缓存存储中
公开(公告)号：US6035392A
公开(公告)日：2000-03-07
申请号：US26923
申请日：1998-02-20
申请人： John Stephen Liptay , Mark Anthony Check , Barry Watson Krumm , Jennifer Almoradie Navarro , Charles Franklin Webb
发明人： John Stephen Liptay , Mark Anthony Check , Barry Watson Krumm , Jennifer Almoradie Navarro , Charles Franklin Webb
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3804
摘要： A computer for executing programs and having a structure for fetching instructions and/or operands along a path which may not be taken by a process being executed by a computer processor having a hierarchical memory structure with data being loaded into cache lines of a cache in the structure, and having block line fetch signal selection logic and computational logic with hedge selection logic for generating line fetch block signals for control of hedging by fetching instructions and/or operands along a path which may not be taken by a process being executed and making selected hedge fetches sensitive to whether the data is in the cache so as to gain the best performance advantage with a selected hedge fetch signal which accompanies each fetch request to the cache to identify whether a line should be loaded if it misses the cache to indicate a selected hedge fetch when this signal is ON, and rejecting a fetch request in the event the selected hedge fetch signal is turned ON if the data is not in the cache, the cache will reject the fetch, and thereafter repeating the fetch request after a fetch request has been rejected when the selected hedge fetch signal was turned ON the data was not in the cache to repeat the fetch request at a later time when it is more certain that the process being executed wants the data, or never repeating the request upon determination that the process being executed does not need the data to he fetched.
摘要翻译：一种用于执行程序并具有用于沿着路径获取指令和/或操作数的结构的计算机，该路径可能不被由具有分层存储器结构的计算机处理器执行的进程执行，其中数据被加载到高速缓存的高速缓存行中结构，并且具有块线取指信号选择逻辑和具有对冲选择逻辑的计算逻辑，用于产生线取指块信号，用于通过沿着路径获取指令和/或操作数来控制对冲，所述路径可能不被被执行的进程采取并且被选择对冲提取对数据是否在高速缓存中敏感，以便通过选择的对冲提取信号获得最佳的性能优势，该信号伴随着每个提取请求到高速缓存，以识别是否应该加载行，如果它错过高速缓存以指示所选择的当该信号为ON时，进行套期提取，并且如果所选择的对冲获取信号为ON，则拒绝提取请求高速缓存不在缓存中，则缓存将拒绝该提取，并且此后在所选择的对冲提取信号被接通时，在拒绝提取请求之后重复该提取请求，该数据不在高速缓存中以在稍后重复该提取请求更确定正在执行的进程想要数据的时间，或者在确定正在执行的进程不需要他获取的数据的情况下，永远不会重复该请求。

6. 发明授权

US07882278B2 Utilizing programmable channels for allocation of buffer space and transaction control in data communications 失效
标题翻译：利用可编程通道在数据通信中分配缓冲区空间和事务控制
公开(公告)号：US07882278B2
公开(公告)日：2011-02-01
申请号：US12362585
申请日：2009-01-30
申请人： Sundeep Chadha , Mark Anthony Check , Bernard Charles Drerup , Michael Grassi
发明人： Sundeep Chadha , Mark Anthony Check , Bernard Charles Drerup , Michael Grassi
IPC分类号： G06F13/42
CPC分类号： G06F13/4059
摘要： A control mechanism for data bus communications employs channels to which bus transactions are assigned, each channel having independent flow control. The control mechanism enforces an ordering algorithm among channels, whereby at least some transactions may pass other transactions. Channel attributes are programmable to vary the ordering conditions. Preferably, each channel is allocated its own programmable buffer area. The control mechanism independently determines, for each channel, whether buffer space is available and enforces flow control independently for each channel accordingly. Flow control is preferably credit-based, credits representing buffer space or some other capacity of a receiver to receive data. Preferably, the flow control mechanism comprises a central interconnect module controlling internal communications of an integrated circuit chip.
摘要翻译：用于数据总线通信的控制机制采用分配总线事务的通道，每个通道具有独立的流量控制。控制机制强制通道之间的排序算法，由此至少一些交易可以通过其他交易。通道属性可编程以改变排序条件。优选地，每个信道被分配其自己的可编程缓冲区。控制机制为每个通道独立地确定缓冲区空间是否可用，并相应地为每个通道独立地执行流量控制。流量控制优选地是基于信用的，表示缓冲区空间的信用或接收器接收数据的一些其他容量。优选地，流量控制机构包括控制集成电路芯片的内部通信的中央互连模块。

7. 发明申请

US20090138629A1 Utilizing Programmable Channels for Allocation of Buffer Space and Transaction Control in Data Communications 失效
标题翻译：利用可编程通道分配数据通信中的缓冲区空间和事务控制
公开(公告)号：US20090138629A1
公开(公告)日：2009-05-28
申请号：US12362585
申请日：2009-01-30
申请人： Sundeep Chadha , Mark Anthony Check , Bernard Charles Drerup , Michael Grassi
发明人： Sundeep Chadha , Mark Anthony Check , Bernard Charles Drerup , Michael Grassi
IPC分类号： G06F13/42
CPC分类号： G06F13/4059
摘要： A control mechanism for data bus communications employs channels to which bus transactions are assigned, each channel having independent flow control. The control mechanism enforces an ordering algorithm among channels, whereby at least some transactions may pass other transactions. Channel attributes are programmable to vary the ordering conditions. Preferably, each channel is allocated its own programmable buffer area. The control mechanism independently determines, for each channel, whether buffer space is available and enforces flow control independently for each channel accordingly. Flow control is preferably credit-based, credits representing buffer space or some other capacity of a receiver to receive data. Preferably, the flow control mechanism comprises a central interconnect module controlling internal communications of an integrated circuit chip.
摘要翻译：用于数据总线通信的控制机制采用分配总线事务的通道，每个通道具有独立的流量控制。控制机制强制通道之间的排序算法，由此至少一些交易可以通过其他交易。通道属性可编程以改变排序条件。优选地，每个信道被分配其自己的可编程缓冲区。控制机制为每个通道独立地确定缓冲区空间是否可用，并相应地为每个通道独立地执行流量控制。流量控制优选地是基于信用的，表示缓冲区空间的信用或接收器接收数据的一些其他容量。优选地，流量控制机构包括控制集成电路芯片的内部通信的中央互连模块。

8. 发明授权

US07493426B2 Data communication method and apparatus utilizing programmable channels for allocation of buffer space and transaction control 失效
标题翻译：数据通信方法和装置利用可编程通道分配缓冲区空间和事务控制
公开(公告)号：US07493426B2
公开(公告)日：2009-02-17
申请号：US11047548
申请日：2005-01-31
申请人： Sundeep Chadha , Mark Anthony Check , Bernard Charles Drerup , Michael Grassi
发明人： Sundeep Chadha , Mark Anthony Check , Bernard Charles Drerup , Michael Grassi
IPC分类号： G06F3/00 , G06F5/00 , G06F11/00 , G01R31/08 , G08C15/00 , H04J1/16 , H04J3/14 , H04L1/00 , H04L12/26
CPC分类号： G06F13/4059
摘要： A control mechanism for data bus communications employs channels to which bus transactions are assigned, each channel having independent flow control. The control mechanism enforces an ordering algorithm among channels, whereby at least some transactions may pass other transactions. Channel attributes are programmable to vary the ordering conditions. Preferably, each channel is allocated its own programmable buffer area. The control mechanism independently determines, for each channel, whether buffer space is available and enforces flow control independently for each channel accordingly. Flow control is preferably credit-based, credits representing buffer space or some other capacity of a receiver to receive data. Preferably, the flow control mechanism comprises a central interconnect module controlling internal communications of an integrated circuit chip.
摘要翻译：用于数据总线通信的控制机制采用分配总线事务的通道，每个通道具有独立的流量控制。控制机制强制通道之间的排序算法，由此至少一些交易可以通过其他交易。通道属性可编程以改变排序条件。优选地，每个信道被分配其自己的可编程缓冲区。控制机制为每个通道独立地确定缓冲区空间是否可用，并相应地为每个通道独立地执行流量控制。流量控制优选地是基于信用的，表示缓冲区空间的信用或接收器接收数据的一些其他容量。优选地，流量控制机构包括控制集成电路芯片的内部通信的中央互连模块。

9. 发明授权

US07277974B2 Data communication method and apparatus utilizing credit-based data transfer protocol and credit loss detection mechanism 失效
标题翻译：数据通信方法和设备利用信用数据传输协议和信用损失检测机制
公开(公告)号：US07277974B2
公开(公告)日：2007-10-02
申请号：US11553500
申请日：2006-10-27
申请人： Mark Anthony Check , Bernard Charles Drerup , Michael Grassi
发明人： Mark Anthony Check , Bernard Charles Drerup , Michael Grassi
IPC分类号： G06F13/00
CPC分类号： G06F13/36
摘要： A communications bus for a digital device includes a credit-based flow control mechanism, in which a sending component maintains a local record of its credits. Credits are returned to the sender by pulsing a single-bit credit return line. A separate mechanism provides a count of available credits from the receiver, the separate mechanism not necessarily being current. The local record is compared to the count of credits from the separate mechanism over a pre-determined time interval, failure of the two values to agree at any time during the interval indicating a probable credit discrepancy. A credit discrepancy is confirmed, preferably by suspending certain bus activity for a sufficiently long period to account for any delay in propagating credit value changes, and re-comparing the values. Preferably, the bus communicates between internal components of an integrated circuit chip.
摘要翻译：用于数字设备的通信总线包括基于信用的流量控制机制，其中发送组件保持其信用的本地记录。通过脉冲单位信用回报线将积分返还给发件人。单独的机制提供来自接收器的可用信用的计数，单独的机制不一定是当前的。将本地记录与预定时间间隔内的单独机制的信用计数进行比较，两个值在表示可能的信用差异的间隔期间的任何时间失败。确认信用差异，最好是通过暂停一段长时间的公共汽车活动来解决传播信用额度变化的任何延误，并重新比较价值。优选地，总线在集成电路芯片的内部部件之间进行通信。

10. 发明授权

US6108776A Globally or selectively disabling branch history table operations during sensitive portion of millicode routine in millimode supporting computer 失效
标题翻译：在毫秒支持计算机中的millicode例程的敏感部分，全局或选择性地禁用分支历史表操作
公开(公告)号：US6108776A
公开(公告)日：2000-08-22
申请号：US70362
申请日：1998-04-30
申请人： Mark Anthony Check , John Stephen Liptay , Timothy John Slegel , Charles Franklin Webb , Mark Steven Farrell
发明人： Mark Anthony Check , John Stephen Liptay , Timothy John Slegel , Charles Franklin Webb , Mark Steven Farrell
IPC分类号： G06F9/22 , G06F9/26 , G06F9/318 , G06F9/38 , G06F9/32
CPC分类号： G06F9/3806 , G06F9/3017
摘要： A millimode capable computer system provides control to millicode to allow the BHT operations to continue except when the these special situations occur that require control of instruction fetch operations must be provided and the BHT can be turned off for some sections of code execution, but not disabled for all. A single free running BHT functions for both a normal mode and a millimode for the central processor which can execute in millimode with a branch history table directing instruction fetch for which both a global BHT disable and millicode disables exist. Hit detection logic receives input from the global BHT disable, as well as from an initialized control register bit and a processor control register bit to select the correct set target information and generate a "branch history table hit detected" control signal.
摘要翻译：具有毫米级功能的计算机系统提供对millicode的控制以允许BHT操作继续，除非出现这些特殊情况需要提供指令提取操作的控制，并且BHT可以在某些代码执行部分被关闭但不被禁用对全部。单个免费运行的BHT功能可用于中央处理器的正常模式和毫模式，可以以毫米模式执行，其中分支历史表指示全局BHT禁用和毫代码禁用两者之间存在禁用指令的指令提取。命中检测逻辑接收来自全局BHT禁用的输入，以及从初始化的控制寄存器位和处理器控制寄存器位选择正确的设置目标信息并生成“检测到分支历史表命中”控制信号。

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