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1. 发明授权

US5610539A Logic family for low voltage high-speed applications 失效
标题翻译：用于低压高速应用的逻辑系列
公开(公告)号：US5610539A
公开(公告)日：1997-03-11
申请号：US594063
申请日：1996-01-30
申请人： Robert A. Blauschild , Daniel J. Linebarger
发明人： Robert A. Blauschild , Daniel J. Linebarger
IPC分类号： H03K19/086 , H03K19/013
CPC分类号： H03K19/086
摘要： A new logic family is identified that achieves much better speeds than CML logic gates. This new logic family operates with multiple inputs and a single logic level, using differential pairs of transistors for each input transistor of the multiple input. This new logic family enables high speed operation, or higher speed, than the prior art, together with lower operating current and a power-delay enhancement significantly increased over the prior art.
摘要翻译：识别出一种新的逻辑系列，其实现比CML逻辑门更好的速度。这种新的逻辑系列使用多个输入和单个逻辑电平，使用多输入的每个输入晶体管的差分晶体管对。与现有技术相比，这种新的逻辑系列能够实现高速操作或更高的速度，同时与现有技术相比，更低的工作电流和功率延迟增强显着增加。

2. 发明授权

US4005315A Triple state to binary converter 失效
标题翻译：三态到二进制转换器
公开(公告)号：US4005315A
公开(公告)日：1977-01-25
申请号：US615476
申请日：1975-09-22
申请人： Robert A. Blauschild
发明人： Robert A. Blauschild
IPC分类号： H03M5/18 , H03K19/28 , H03K19/08
CPC分类号： H03M5/18
摘要： A logic circuit for converting a triple state input to a binary output having a single line ternary input and a two line binary output. A pair of output transistors provide the two line binary output, and means are provided for driving both of these output transistors, such that three different binary output states result from the ternary input states of low, high and open (or floating), respectively.
摘要翻译：用于将三态输入转换为具有单行三进制输入和二线二进制输出的二进制输出的逻辑电路。一对输出晶体管提供两线二进制输出，并且提供用于驱动这两个输出晶体管的装置，使得三个不同的二进制输出状态分别由低，高和断开（或浮置）的三进制输入状态产生。

3. 发明授权

US4532479A Differential amplifier circuit with rail-to-rail capability 失效
标题翻译：具有轨至轨功能的差分放大器电路
公开(公告)号：US4532479A
公开(公告)日：1985-07-30
申请号：US525181
申请日：1983-08-23
申请人： Robert A. Blauschild
发明人： Robert A. Blauschild
IPC分类号： H03F3/20 , H03F3/30 , H03F3/45
CPC分类号： H03F3/4521 , H03F3/3066 , H03F3/45121 , H03F2203/45028 , H03F2203/45031 , H03F2203/45224 , H03F2203/45232 , H03F2203/45244 , H03F2203/45294 , H03F2203/45366 , H03F2203/45398 , H03F2203/45471 , H03F2203/45612
摘要： A differential amplifier circuit contains a pair of complementary input portions (3, 5 and 4, 6). The input portions amplify a common differential input signal to produce corresponding amplified differential signals which are supplied to a summing section that operates as a modulated current mirror to produce an output signal representative of the input signal. The summing section contains a pair of like-polarity first and second amplifiers (13 and 14) and a pair of like-polarity third and fourth amplifiers (19 and 20) complementary to the other amplifiers. A pair of impedance elements (11 and 12) are coupled between a first voltage supply (ground reference) and the third and fourth amplifiers. A pair of current sources, typically impedance elements (8 and 9), are coupled between a second voltage supply (+B) and the first and second amplifiers. An important feature of this circuit is that the output signal changes with the differential portion of the input signal as its common-mode portion varies over the entire voltage range between the levels of the supplies.
摘要翻译：差分放大器电路包含一对互补输入部分（3,5和4,6）。输入部分放大公共差分输入信号以产生相应的放大后的差分信号，该差分信号被提供给作为调制电流镜进行工作的求和部分，以产生表示输入信号的输出信号。求和部分包含一对相同极性的第一和第二放大器（13和14）以及与其它放大器互补的一对相似极性的第三和第四放大器（19和20）。一对阻抗元件（11和12）耦合在第一电压源（接地参考）和第三和第四放大器之间。一对电流源（通常为阻抗元件8和9）耦合在第二电压源（+ B）和第一和第二放大器之间。该电路的一个重要特征是输出信号随着输入信号的差分部分而变化，因为其共模部分在电源电平之间的整个电压范围内变化。

4. 发明授权

US3947704A Low resistance microcurrent regulated current source 失效
标题翻译：低电阻微电流调节电流源
公开(公告)号：US3947704A
公开(公告)日：1976-03-30
申请号：US532767
申请日：1974-12-16
申请人： Robert A. Blauschild
发明人： Robert A. Blauschild
IPC分类号： G05F3/26 , H03K1/12
CPC分类号： G05F3/265
摘要： A low resistance closed feedback loop regulated current source for supplying a load, the source being of the type including a transistor having input and output electrodes respectively connected between voltage input and current output terminals, and said transistor having a control electrode. The feedback loop includes amplifying means having an output connected to the transistor control electrode and having first and second inputs providing differential current gain for signal current at said inputs and for maintaining minimum differential voltage between said inputs. First and second PN semiconductor structures having first and second electrodes and having dissimilar junction boundary areas are provided with the first electrodes of said structures being connected to the respective first and second inputs of the amplifying means. A resistor is provided connected between the second electrode of the structure having the greater boundary area and the second electrode of the remaining structure. Means is provided coupled to sense current output of said source and is connected to the second electrode of said remaining structure for providing a feedback signal which causes the output of said current source to assume a predetermined value.
摘要翻译：一种用于提供负载的低电阻闭合反馈环路稳压电流源，该源极包括具有分别连接在电压输入和电流输出端子之间的输入和输出电极的晶体管，并且所述晶体管具有控制电极。反馈回路包括具有连接到晶体管控制电极并具有第一和第二输入的输出的放大装置，为所述输入处的信号电流提供差分电流增益，并保持所述输入之间的最小差分电压。具有第一和第二电极并且具有不同接合边界区域的第一和第二PN半导体结构设置有所述结构的第一电极连接到放大装置的相应的第一和第二输入端。连接在具有较大边界区域的结构的第二电极和剩余结构的第二电极之间的电阻器。提供耦合到所述源的感测电流输出并且连接到所述剩余结构的第二电极的装置，用于提供使所述电流源的输出呈现预定值的反馈信号。

5. 发明授权

US07443977B1 Method and apparatus for a high efficiency line driver 有权
标题翻译：高效率线路驱动器的方法和装置
公开(公告)号：US07443977B1
公开(公告)日：2008-10-28
申请号：US11267652
申请日：2005-11-03
申请人： Rouben Toumani , Robert A. Blauschild , Sanjay M. Bhandari , Behrooz Rezvani , Dale Smith
发明人： Rouben Toumani , Robert A. Blauschild , Sanjay M. Bhandari , Behrooz Rezvani , Dale Smith
IPC分类号： H04M1/00
CPC分类号： H04L27/0002 , H04M3/007
摘要： A high efficiency line driver is disclosed. The line driver may be applied with equal advantage in wired and wireless communication media to amplify data signals with a minimum of power consumption. In an embodiment of the invention a line driver is disclosed which includes: at least one amplifier, a delay element, a control signal generator and a generator. The at least one amplifier includes at least one bias supply, a signal input and a signal output. The delay element accepts as an input the data signal and delays delivery of the data signal to the at least one line amplifier for amplification. The generator is responsive to a control signal to generate varying voltage levels corresponding thereto on the at least one bias supply of the at least one amplifier. The control signal generator is responsive to the input data signal to detect peaks therein and to generate the control signal corresponding thereto in advance of delivery of the data signal to the amplifier.
摘要翻译：公开了一种高效线驱动器。线驱动器可以在有线和无线通信介质中具有相同的优点，以最小的功耗来放大数据信号。在本发明的实施例中，公开了一种线路驱动器，其包括：至少一个放大器，延迟元件，控制信号发生器和发生器。所述至少一个放大器包括至少一个偏置电源，信号输入和信号输出。延迟元件接收数据信号作为输入，并将数据信号的传送延迟至至少一个用于放大的线路放大器。发生器响应于控制信号以在至少一个放大器的至少一个偏置电源上产生与其对应的变化的电压电平。控制信号发生器响应于输入数据信号来检测其中的峰值，并且在将数据信号传送到放大器之前产生与之对应的控制信号。

6. 发明授权

US06987851B1 Method and apparatus for a high efficiency line driver 有权
标题翻译：高效率线路驱动器的方法和装置
公开(公告)号：US06987851B1
公开(公告)日：2006-01-17
申请号：US09962490
申请日：2001-09-24
申请人： Rouben Toumani , Robert A. Blauschild , Sanjay M. Bhandari , Behrooz Rezvani , Dale Smith
发明人： Rouben Toumani , Robert A. Blauschild , Sanjay M. Bhandari , Behrooz Rezvani , Dale Smith
IPC分类号： H04M3/40
CPC分类号： H04L27/0002 , H04M3/007
摘要： A high efficiency line driver is disclosed. The line driver may be applied with equal advantage in wired and wireless communication media to amplify data signals with a minimum of power consumption. In an embodiment of the invention a line driver is disclosed which includes: at least one amplifier, a delay element, a control signal generator and a generator. The at least one amplifier includes at least one bias supply, a signal input and a signal output. The delay element accepts as an input the data signal and delays delivery of the data signal to the at least one line amplifier for amplification. The generator is responsive to a control signal to generate varying voltage levels corresponding thereto on the at least one bias supply of the at least one amplifier. The control signal generator is responsive to the input data signal to detect peaks therein and to generate the control signal corresponding thereto in advance of delivery of the data signal to the amplifier.
摘要翻译：公开了一种高效线驱动器。线驱动器可以在有线和无线通信介质中具有相同的优点，以最小的功耗来放大数据信号。在本发明的实施例中，公开了一种线路驱动器，其包括：至少一个放大器，延迟元件，控制信号发生器和发生器。所述至少一个放大器包括至少一个偏置电源，信号输入和信号输出。延迟元件接收数据信号作为输入，并将数据信号的传送延迟至至少一个用于放大的线路放大器。发生器响应于控制信号以在至少一个放大器的至少一个偏置电源上产生与其对应的变化的电压电平。控制信号发生器响应于输入数据信号来检测其中的峰值，并且在将数据信号传送到放大器之前产生与其对应的控制信号。

7. 发明授权

US4593268A Analog-to-digital converter using absolute-value conversion 失效
标题翻译：使用绝对值转换的模数转换器
公开(公告)号：US4593268A
公开(公告)日：1986-06-03
申请号：US468720
申请日：1983-02-22
申请人： Robert A. Blauschild
发明人： Robert A. Blauschild
IPC分类号： H03M1/44 , H03M1/00 , H03K13/09
CPC分类号： H03M1/44
摘要： An absolute-value analog-to-digital converter containing a chain of matched main absolute-value differential amplifiers (A.sub.1 -A.sub.N) has a gain control for regulating the gain of each main amplifier utilizing an auxiliary absolute-value differential amplifier (A.sub.GC) matched to the main amplifiers. An offset control in the converter drives the offsets of the amplifiers toward zero by using a further absolute-value differential amplifier (A.sub.OC) matched to the other amplifiers. The gain and offset control are implemented with suitable feedback circuitry.
摘要翻译：包含匹配主绝对值差分放大器（A1-AN）链的绝对值模数转换器具有增益控制，用于利用匹配的辅助绝对值差分放大器（AGC）来调节每个主放大器的增益到主放大器。转换器中的偏移控制通过使用与其他放大器匹配的另一绝对值差分放大器（AOC）将放大器的偏移驱动为零。利用合适的反馈电路来实现增益和偏移控制。

8. 发明授权

US4346344A Stable field effect transistor voltage reference 失效
标题翻译：稳定的场效应晶体管参考电压
公开(公告)号：US4346344A
公开(公告)日：1982-08-24
申请号：US10195
申请日：1979-02-08
申请人： Robert A. Blauschild
发明人： Robert A. Blauschild
IPC分类号： G05F3/24 , H01L27/088 , G05F3/08
CPC分类号： G05F3/245 , G05F3/247 , H01L27/0883 , Y10S323/907
摘要： A temperature stable voltage reference utilizes an enhancement field effect transistor and a depletion field effect transistor each connected in series with a current source. A differential amplifier has its input terminals separately connected between each of the field effect transistors and their respective current supplies. An input terminal of the field effect transistor is utilized as the reference voltage and is also connected to the gate of one of the field effect transistors, the gate of the other field effect transistor being connected to a reference potential.
摘要翻译：温度稳定的电压基准使用与电流源串联的增强场效应晶体管和耗尽场效应晶体管。差分放大器的输入端分别连接在每个场效应晶体管和它们各自的电流源之间。场效应晶体管的输入端用作参考电压，并且还连接到场效应晶体管之一的栅极，另一场效应晶体管的栅极连接到参考电位。

9. 发明授权

US06567031B1 A/D multi-channel architecture 有权
标题翻译： A / D多通道架构
公开(公告)号：US06567031B1
公开(公告)日：2003-05-20
申请号：US09715633
申请日：2000-11-17
申请人： Behrooz Rezvani , Robert A. Blauschild
发明人： Behrooz Rezvani , Robert A. Blauschild
IPC分类号： H03M138
CPC分类号： H03M1/20 , H03M1/1215 , H03M1/145
摘要： An apparatus and method for A/D conversion is provided. The apparatus provides for multi-channel A/D conversion. It may be used in any application in which A/D conversion of either a single signal or multiple signal sources is required. Such applications include X-DSL communications. The apparatus and method allows A/D converters to be fabricated with reduced cost and power when compared with prior art designs. The A/D converter comprises a sampler, a converter and a logic. The sampler includes an input coupled with at least one analog information signal. The sampler repetitively provides at least one pre-sample together with a sample of the analog information signal. The sampling interval between the samples is substantially greater than a pre-sample interval between the pre-sample and the corresponding sample. The converter includes a bit line output and at least one input coupled with the output of said sampler. The converter is responsive to the pre-sample at the input to output a first bit signal corresponding to at least one significant bit of the pre-sample at the bit line output. The converter is further responsive to the sample at the input, to output a second bit signal corresponding to at least one significant bit of the sample at the bit line output. The logic is coupled with the bit line output of said converter. The logic combines the first bit signal and the second bit signal into a composite digital sample of the pre-sample together with the sample.
摘要翻译：提供了用于A / D转换的装置和方法。该设备提供多通道A / D转换。它可以用于需要单信号或多信号源的A / D转换的任何应用中。这样的应用包括X-DSL通信。与现有技术的设计相比，该装置和方法允许以降低的成本和功率制造A / D转换器。 A / D转换器包括采样器，转换器和逻辑。采样器包括与至少一个模拟信息信号耦合的输入。采样器重复地提供至少一个预采样与模拟信息信号的样本。样本之间的采样间隔显着大于预采样与相应样本之间的样本前间隔。转换器包括位线输出和与所述采样器的输出耦合的至少一个输入。转换器对输入端的预采样进行响应，以输出对应于位线输出处的预采样的至少一个有效位的第一位信号。转换器进一步响应输入端的采样，输出对应于位线输出的采样的至少一个有效位的第二位信号。该逻辑与所述转换器的位线输出耦合。该逻辑将第一位信号和第二位信号与样本一起组合成预取样的复合数字样本。

10. 发明授权

US4677315A Switching circuit with hysteresis 失效
标题翻译：具有迟滞的开关电路
公开(公告)号：US4677315A
公开(公告)日：1987-06-30
申请号：US890251
申请日：1986-07-28
申请人： Robert A. Blauschild , Edmond Toy
发明人： Robert A. Blauschild , Edmond Toy
IPC分类号： H03K3/0233 , H03K3/3565 , H03K5/153 , H03K5/24
CPC分类号： H03K3/3565
摘要： A circuit switches with a hysteresis defined by separately controllable thresholds which can be made largely independent of temperature and fabrication conditions. The circuit contains a pair of differential portions (21 and 22) and an arithmetic component (24). The hysteresis is introduced into the circuit by using positive feedback to control the position of a switch (23) in such a manner as to change the transconductance of the circuit as it is switching.
摘要翻译：电路开关具有由单独控制的阈值限定的滞后，其可以在很大程度上独立于温度和制造条件。电路包含一对差动部分（21,22）和运算部件（24）。通过使用正反馈来将迟滞引入到电路中，以便在切换时改变电路的跨导来控制开关（23）的位置。

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