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1. 发明授权

US06825790B2 Low power consumption pipelined analog-to-digital converter 失效
标题翻译：低功耗流水线模数转换器
公开(公告)号：US06825790B2
公开(公告)日：2004-11-30
申请号：US10234469
申请日：2002-09-05
申请人： Kuo-Yu Chou
发明人： Kuo-Yu Chou
IPC分类号： H03M138
CPC分类号： H03M1/164 , H03M1/40
摘要： This present invention is directed to a stage circuit for a pipelined analog-to-digital converter. The stage circuit includes an amplifier, a comparator, a first compensator and a second compensator, and three modes are developed for the stage circuit in signal processing: a sampling mode, a first amplifying mode and a second amplifying mode. In the sampling mode, the amplifier is inputted with an analog input signal; the comparator compares the analog input signal with a reference signal, and then generates a first digital output code. In the first amplifying mode, the first compensator selectively adds a first compensation value to the analog input signal according to the first digital output code, and then generates a first input signal; the amplifier amplifies the first input signal and then generates a first output signal; the comparator compares the first output signal with the reference signal and then generates a second digital output signal. In the second amplifying mode, the first compensator selectively adds a second compensation value to the analog input signal according to the first digital output code and the second digital output code, and then generates a second input signal; the amplifier amplifies the second input signal and then generates a second output signal; the second compensator selectively chooses a third compensation value according to the first digital output code and the second digital output code, and the third compensation value is amplified and added to the second output signal to generate an analog output signal which sends to the next stage circuit.
摘要翻译：本发明涉及一种用于流水线模数转换器的级电路。舞台电路包括放大器，比较器，第一补偿器和第二补偿器，并且在信号处理中为舞台电路开发三种模式：采样模式，第一放大模式和第二放大模式。在采样模式下，放大器输入模拟输入信号; 比较器将模拟输入信号与参考信号进行比较，然后生成第一数字输出代码。在第一放大模式中，第一补偿器根据第一数字输出码向模拟输入信号选择性地添加第一补偿值，然后产生第一输入信号; 放大器放大第一输入信号，然后产生第一输出信号; 比较器将第一输出信号与参考信号进行比较，然后产生第二数字输出信号。在第二放大模式中，第一补偿器根据第一数字输出代码和第二数字输出代码选择性地向模拟输入信号添加第二补偿值，然后产生第二输入信号; 放大器放大第二输入信号，然后产生第二输出信号; 第二补偿器根据第一数字输出码和第二数字输出码有选择地选择第三补偿值，并且第三补偿值被放大并相加到第二输出信号，以产生发送到下一级电路的模拟输出信号。

2. 发明授权

US06340943B1 Analog to digital converter method and apparatus 有权
标题翻译：模数转换器的方法和装置
公开(公告)号：US06340943B1
公开(公告)日：2002-01-22
申请号：US09483196
申请日：2000-01-14
申请人： Hugh Chow , Edward G. Callway
发明人： Hugh Chow , Edward G. Callway
IPC分类号： H03M138
CPC分类号： H03M1/145 , H03M1/36 , H03M1/46
摘要： A multistage A/D converter and conversion method includes generating a partial A/D bit result of a complete A/D result at a first bit/clock rate based on the received analog input signal and generating remaining A/D bits of the complete A/D result from the partial A/D bit result, at a second and slower bit/clock rate. Accordingly, the partial A/D result output from the first stage is used as input to determine remaining A/D bits to generate a complete A/D result.
摘要翻译：多级A / D转换器和转换方法包括基于所接收的模拟输入信号以第一位/时钟速率产生完整A / D结果的部分A / D比特结果，并产生完整A的D / D比特的剩余A / D比特 / D由部分A / D位结果产生，以第二个和较慢的位/时钟速率。因此，将从第一级输出的部分A / D结果用作输入，以确定剩余的A / D位以产生完整的A / D结果。

3. 发明授权

US06295016B1 Pipeline analog to digital (A/D) converter with relaxed accuracy requirement for sample and hold stage 有权
标题翻译：管道模拟数字（A / D）转换器，对采样和保持级具有放宽的精度要求
公开(公告)号：US06295016B1
公开(公告)日：2001-09-25
申请号：US09506208
申请日：2000-02-17
申请人： Meei-Ling Chiang
发明人： Meei-Ling Chiang
IPC分类号： H03M138
CPC分类号： H03M1/0602 , H03M1/0695 , H03M1/442
摘要： A pipeline analog to digital (A/D) converter for converting an analog input signal into a digital representation of the analog signal. The pipeline A/D converter has a sample and hold stage, the sample and hold stage sampling and holding the analog input signal and outputting a sampled and held signal. The pipeline A/D converter also has a first analog signal converter stage, the first analog converter stage producing a digital output based on the sampled and held signal, from which a most significant bit of the digital representation of the analog input signal is derived. The first analog converter stage produces a residue signal based on a comparison of the analog input signal and an analog representation of the digital output. The pipeline A/D converter has at least one additional stage, the additional stage producing a subsequent digital output based on the residue signal produced by the first analog signal converter stage, at least one bit which is less significant than the most significant bit being derived from the subsequent digital output.
摘要翻译：一种用于将模拟输入信号转换为模拟信号的数字表示的流水线模数（A / D）转换器。流水线A / D转换器具有采样和保持级，采样和保持级采样并保持模拟输入信号并输出采样和保持的信号。流水线A / D转换器还具有第一模拟信号转换器级，第一模拟转换器级基于采样和保持的信号产生数字输出，从中得到模拟输入信号的数字表示的最高有效位。第一模拟转换器级基于模拟输入信号和数字输出的模拟表示的比较产生残留信号。流水线A / D转换器具有至少一个附加级，附加级基于由第一模拟信号转换器级产生的残余信号产生后续的数字输出，至少一个比所得到的最高有效位的有效位少从后续的数字输出。

4. 发明授权

US06285309B1 Nested pipelined analog-to-digital converter 有权
标题翻译：嵌套流水线模数转换器
公开(公告)号：US06285309B1
公开(公告)日：2001-09-04
申请号：US09395846
申请日：1999-09-14
申请人： Paul C. Yu
发明人： Paul C. Yu
IPC分类号： H03M138
CPC分类号： H03M1/168
摘要： A multi-stage analog-to-digital converter (“ADC”) for converting an analog input signal to a series of digital values, each having a first plurality of bits, representing the voltage levels of the analog input signal at a corresponding series of sample times. The ADC includes a plurality of analog-to-digital converter stages connected serially in pipeline configuration. One or more of such stages includes an analog-to-digital subconverter, providing a second plurality of bits of the digital value, where the second plurality is smaller than the first plurality, the analog-to-digital subconverter including a plurality of analog-to-digital subconverter substages connected serially in pipeline configuration. Each such subconverter substages provides one or more bits of the second plurality of bits. The nested approach of this invention allows an increased resolution in the first stage of the pipeline which has the benefit of avoidance of capacitor trimming, a more efficient use of the comparators and other circuit components, a relaxation in the comparator offset requirements, and satisfy kT/C noise requirements more easily in submicron low-voltage ADC's.
摘要翻译：一种用于将模拟输入信号转换成一系列数字值的多级模数转换器（“ADC”），每一数字值具有第一多位，表示在相应系列的模拟输入信号的电压电平样品时间。 ADC包括以管道配置串联连接的多个模数转换器级。一个或多个这样的级包括模数转换子转换器，提供数字值的第二多个位，其中第二多个小于第一多个，该模数转换子转换器包括多个模拟 - 数字子转换器，数字子转换器子系列串行连接在管道配置中。每个这样的子转换器子级提供第二多个比特的一个或多个比特。本发明的嵌套方法允许在管道的第一级中增加分辨率，其有利于避免电容器微调，比较器和其他电路组件的更有效的使用，比较器偏移要求的松弛，并且满足kT / C噪声要求更容易在亚微米低压ADC中。

5. 发明授权

US06822601B1 Background-calibrating pipelined analog-to-digital converter 失效
标题翻译：背景校准流水线模数转换器
公开(公告)号：US06822601B1
公开(公告)日：2004-11-23
申请号：US10604458
申请日：2003-07-23
申请人： Hung-Chih Liu , Jieh-Tsomg Wu , Zwei-Mei Lee
发明人： Hung-Chih Liu , Jieh-Tsomg Wu , Zwei-Mei Lee
IPC分类号： H03M138
CPC分类号： H03M1/1004 , H03M1/167
摘要： A multiplying digital-to-analog converter (MDAC) stage includes a plurality of second capacitances in parallel selectively connected between an input node and an amplifier input and between a corresponding plurality of digital reference signals, which can include a pseudo-random first calibration signal, and the amplifier input. A pipelined ADC incorporating a series of such MDAC stages includes a multiplier connected to the last MDAC stage of the series, a low-pass filter for filtering output of the multiplier and outputting a DC component, and an encoder for receiving output of the MDAC stages and generating a digital output signal and for compensating the digital output signal with the DC component. Background calibration of the ADC includes applying the first calibration signal to a second capacitance of the MDAC stage during a hold phase, and filtering the first calibration signal from the digital output of the pipelined analog-to-digital converter.
摘要翻译：倍增的数模转换器（MDAC）级包括多个并联的第二电容，其选择性地连接在输入节点和放大器输入之间以及相应的多个数字参考信号之间，所述数字参考信号可以包括伪随机的第一校准信号，和放大器输入。包含一系列这样的MDAC级的流水线ADC包括连接到该系列的最后MDAC级的乘法器，用于滤波乘法器的输出和输出DC分量的低通滤波器以及用于接收MDAC级的输出的编码器并产生数字输出信号并用DC补偿数字输出信号。 ADC的背景校准包括在保持阶段将第一校准信号施加到MDAC级的第二电容，以及从流水线模数转换器的数字输出滤波第一校准信号。

6. 发明授权

US06803873B1 Pipeline analog to digital converter 失效
标题翻译：管道模数转换器
公开(公告)号：US06803873B1
公开(公告)日：2004-10-12
申请号：US10735721
申请日：2003-12-16
申请人： Ryo Motomatsu
发明人： Ryo Motomatsu
IPC分类号： H03M138
CPC分类号： H03M1/0695 , H03M1/44
摘要： An analog input signal A1 is held by a sample-hold-amplifier (SHA) 12 to be outputted as a voltage V12. The V12 is converted into a digital signal of 1,5 bits by sub-A/D converters (SADC: comparators 13, 14, and an encoder 15), and the digital signal is further converted into an analog signal by sub-D/A converters (SDAC: switches 16a, 16b, 16c) to be delivered to an SHA 18. The SHA 18 amplifies a difference in voltage between the voltage V12 and the SDAC by a factor of two to thereby output a voltage VA, which is delivered to an analog-to-digital conversion stage 20. By so doing, the range of an input voltage of the respective SHAs is suppressed to ½ of that for the conventional case, thereby enabling high-speed operation to be executed without impairing linearity.
摘要翻译：模拟输入信号A1被采样保持放大器（SHA）12保持，作为电压V12输出。通过副A / D转换器（SADC：比较器13,14和编码器15）将V12转换成1,5位的数字信号，数字信号通过副D / D转换器进一步转换成模拟信号， A转换器（SDAC：开关16a，16b，16c）被输送到SHA 18.SHA18将电压V12和SDAC之间的电压差放大二倍，从而输出电压VA 通过这样做，各个SHA的输入电压的范围被抑制到传统情况的1/2的范围，从而能够执行高速操作而不损害线性。

7. 发明授权

US06373424B1 Method and apparatus for obtaining linearity in a pipelined analog-to-digital converter 有权
标题翻译：用于在流水线模数转换器中获得线性度的方法和装置
公开(公告)号：US06373424B1
公开(公告)日：2002-04-16
申请号：US09740350
申请日：2000-12-18
申请人： Eric G. Soenen
发明人： Eric G. Soenen
IPC分类号： H03M138
CPC分类号： H03M1/0673 , H03M1/168 , H03M1/74
摘要： A pipelined analog-to-digital converter system (10) is responsive to an analog input signal (18). The system includes four pipeline stages (11-14), which each produce a respective digital output (26-29) that is coupled to a combining circuit (16). The combining circuit generates the digital output (41) of the system. Each pipeline stage includes an analog-to-digital converter (101), which generates the digital output for that stage. A shuffler circuit (103) randomly shuffles the bits of this digital output, in order to generate shuffled switching signals, which in turn are used to control electronic switches (206-209, 211-214) associated with several capacitors (C1-C4). By randomly shuffling the switching signals, the effects caused by variation of any capacitor from an ideal value are randomized. This avoids nonlinearity such as harmonic distortion in the analog output signal (21) from that stage.
摘要翻译：流水线模拟 - 数字转换器系统（10）响应于模拟输入信号（18）。该系统包括四个流水线级（11-14），其分别产生耦合到组合电路（16）的相应的数字输出（26-29）。组合电路产生系统的数字输出（41）。每个流水线级包括一个模拟 - 数字转换器（101），它产生该级的数字输出。洗牌电路（103）随机地洗牌这个数字输出的比特，以便产生混洗的切换信号，其又被用于控制与几个电容器（C1-C4）相关联的电子开关（206-209,211-214）。通过随机洗牌切换信号，将任何电容器从理想值的变化引起的效果随机化。这避免了来自该级的模拟输出信号（21）中的非线性，例如谐波失真。

8. 发明授权

US06348888B1 Pipelined ADC with noise-shaped interstage gain error 有权
标题翻译：流水线ADC具有噪声级间级增益误差
公开(公告)号：US06348888B1
公开(公告)日：2002-02-19
申请号：US09273837
申请日：1999-03-22
申请人： Paul C. Yu
发明人： Paul C. Yu
IPC分类号： H03M138
CPC分类号： H03M1/0634 , H03M1/164 , H03M1/44
摘要： A pipelined analog to digital converter for converting an analog signal to a sequence of digital words, each such word representing a value of the analog signal at a time in a succession of times. The converter includes a sequence of analog to digital converter stages, each such stage generating at least one bit for each such word. A first such stage in the sequence receives the analog signal, and each such stage subsequent to the first stage receives a residue signal from a previous stage in the sequence. Each such stage includes an analog to digital unit that senses a sample of the analog signal and provides one or more bits representing a value of the sample. In at least one of the stages the analog to digital unit comprises a &Sgr;-&Dgr; converter.
摘要翻译：一种用于将模拟信号转换为数字字序列的流水线模数转换器，每个这样的字表示一次中的模拟信号的值。该转换器包括一系列模数转换器级，每个这样的级产生每个这样的字的至少一位。序列中的第一个这样的阶段接收模拟信号，并且在第一级之后的每个这样的级从序列中的前一级接收残留信号。每个这样的级包括模拟数字单元，其感测模拟信号的采样并提供表示样本值的一个或多个位。在至少一个级中，模数转换单元包括一个SIGMA-DELTA转换器。

9. 发明授权

US06310571B1 Multiplexed multi-channel bit serial analog-to-digital converter 有权
标题翻译：多路复用多通道位串行模数转换器
公开(公告)号：US06310571B1
公开(公告)日：2001-10-30
申请号：US09823443
申请日：2001-03-30
申请人： David Xiao Dong Yang , William R. Bidermann
发明人： David Xiao Dong Yang , William R. Bidermann
IPC分类号： H03M138
CPC分类号： H03M1/123 , H03M1/56
摘要： A circuit includes an analog-to-digital (A/D) converter for multiplexing between a number of analog input signals and converting the selected analog input signals to a digital code representation. The A/D converter includes a comparator having a first input terminal connected to receive the first signal having a number of levels, a second input terminal connected to receive a multiple number of analog input signals, and a third input terminal for receiving a multiple number of input select signals. The comparator includes a multiplexer coupling the multiple number of analog input signals to a multiple number of corresponding input signal paths. The multiplexer selects one of the multiple number of input signal paths based on the multiple number of input select signals. In one embodiment, the A/D converter is applied in a digital image sensor for performing pixel-level analog-to-digital conversion using a multi-channel bit serial ADC technique.
摘要翻译：电路包括用于在多个模拟输入信号之间进行复用并将所选择的模拟输入信号转换为数字码表示的模拟（A / D）转换器。 A / D转换器包括比较器，其具有被连接以接收具有多个电平的第一信号的第一输入端，被连接以接收多个模拟输入信号的第二输入端，以及用于接收多个数的第三输入端的输入选择信号。比较器包括将多个模拟输入信号耦合到多个对应的输入信号路径的多路复用器。多路复用器根据多个输入选择信号选择多个输入信号路径中的一个。在一个实施例中，A / D转换器应用于数字图像传感器中，用于使用多通道位串行ADC技术进行像素级模数转换。

10. 发明授权

US06281830B1 System for acquiring and processing signals for controlling a device or a process 失效
标题翻译：用于获取和处理用于控制设备或过程的信号的系统
公开(公告)号：US06281830B1
公开(公告)日：2001-08-28
申请号：US09551886
申请日：2000-04-18
申请人： Emmanuel Flety
发明人： Emmanuel Flety
IPC分类号： H03M138
CPC分类号： G10H1/0066 , G10H3/188
摘要： A system for acquiring and processing signals for controlling a device or a process has inputs receiving analog signals supplied by sensors and which are processed in order to send to the device control signals configured in accordance with a predetermined communication protocol. The system includes a screen and a keypad for accessing and modifying control signal configuration parameters. One application of the system is to controlling devices producing sound effects added to or applied to the sound of a musical instrument.
摘要翻译：用于获取和处理用于控制设备或过程的信号的系统具有接收由传感器提供的模拟信号的输入，并且被处理以便向设备发送根据预定通信协议配置的控制信号。该系统包括用于访问和修改控制信号配置参数的屏幕和键盘。该系统的一个应用是控制产生添加到或应用于乐器的声音的声音效果的装置。

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