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1. 发明申请

US20100109079A1 Vertical type semiconductor device 有权
标题翻译：垂直型半导体器件
公开(公告)号：US20100109079A1
公开(公告)日：2010-05-06
申请号：US12588948
申请日：2009-11-03
申请人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
发明人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
IPC分类号： H01L29/78
CPC分类号： H01L29/7827 , H01L29/66666
摘要： A vertical pillar semiconductor device may include a substrate, a group of channel patterns, a gate insulation layer pattern and a gate electrode. The substrate may be divided into an active region and an isolation layer. A first impurity region may be formed in the substrate corresponding to the active region. The group of channel patterns may protrude from a surface of the active region and may be arranged parallel to each other. A second impurity region may be formed on an upper portion of the group of channel patterns. The gate insulation layer pattern may be formed on the substrate and a sidewall of the group of channel patterns. The gate insulation layer pattern may be spaced apart from an upper face of the group of channel patterns. The gate electrode may contact the gate insulation layer and may enclose a sidewall of the group of channel patterns.
摘要翻译：垂直柱半导体器件可以包括衬底，沟道图案组，栅极绝缘层图案和栅电极。衬底可分为有源区和隔离层。可以在对应于有源区的衬底中形成第一杂质区。通道图案组可以从有源区域的表面突出并且可以彼此平行地布置。第二杂质区可以形成在沟道图案组的上部。栅极绝缘层图案可以形成在衬底和沟道图案组的侧壁上。栅极绝缘层图案可以与沟道图案组的上表面间隔开。栅电极可以接触栅极绝缘层并且可以包围沟道图案组的侧壁。

2. 发明申请

US20100078698A1 Vertical semiconductor device, dram device including the same 审中-公开
标题翻译：垂直半导体器件，包括相同的电容器件
公开(公告)号：US20100078698A1
公开(公告)日：2010-04-01
申请号：US12585776
申请日：2009-09-24
申请人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
发明人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
IPC分类号： H01L27/06 , H01L29/78
CPC分类号： H01L27/10852 , B82Y10/00 , H01L21/823487 , H01L27/10876 , H01L29/0673 , H01L29/0676 , H01L29/66439 , H01L29/66666 , H01L29/775 , H01L29/7827
摘要： A vertical semiconductor device, a DRAM device, and associated methods, the vertical semiconductor device including single crystalline active bodies vertically disposed on an upper surface of a single crystalline substrate, each of the single crystalline active bodies having a first active portion on the substrate and a second active portion on the first active portion, and the first active portion having a first width smaller than a second width of the second active portion, a gate insulating layer on a sidewall of the first active portion and the upper surface of the substrate, a gate electrode on the gate insulating layer, the gate electrode having a linear shape surrounding the active bodies, a first impurity region in the upper surface of the substrate under the active bodies, and a second impurity region in the second active portion.
摘要翻译：垂直半导体器件，DRAM器件和相关方法，垂直半导体器件包括垂直设置在单晶衬底的上表面上的单晶有源体，每个单晶有源体在衬底上具有第一有源部分，所述第一有源部分的第二有源部分和所述第一有源部分具有小于所述第二有源部分的第二宽度的第一宽度，所述第一有源部分的侧壁和所述衬底的上表面上的栅极绝缘层，所述栅电极在所述栅极绝缘层上，所述栅电极具有围绕所述有源体的直线形状，所述基板的所述有源体下方的上表面中的第一杂质区域和所述第二有源部分中的第二杂质区域。

3. 发明申请

US20090242966A1 Vertical-type semiconductor devices 有权
标题翻译：垂直型半导体器件
公开(公告)号：US20090242966A1
公开(公告)日：2009-10-01
申请号：US12380565
申请日：2009-02-27
申请人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
发明人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
IPC分类号： H01L29/792
CPC分类号： H01L27/11582 , H01L21/02524 , H01L21/02587 , H01L21/02598 , H01L21/02675 , H01L21/28282 , H01L21/28518 , H01L21/30604 , H01L21/32133 , H01L27/1052 , H01L27/11568 , H01L27/11578 , H01L27/1158 , H01L29/4234 , H01L29/45 , H01L29/665 , H01L29/66666 , H01L29/66787 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.
摘要翻译：在垂直型存储器件和垂直型存储器件的制造方法中，垂直存储器件包括设置在衬底上的线状绝缘层图形，柱状单晶半导体图案设置在两侧壁上设置在每个单晶半导体图案的侧壁上的绝缘层图案和晶体管。晶体管沿着单晶半导体图案的垂直方向排列，因此存储器件可以高度集成。

4. 发明授权

US08309417B2 Vertical-type semiconductor devices and methods of manufacturing the same 有权
标题翻译：垂直型半导体器件及其制造方法
公开(公告)号：US08309417B2
公开(公告)日：2012-11-13
申请号：US13271446
申请日：2011-10-12
申请人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
发明人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
IPC分类号： H01L21/336
CPC分类号： H01L27/11582 , H01L21/02524 , H01L21/02587 , H01L21/02598 , H01L21/02675 , H01L21/28282 , H01L21/28518 , H01L21/30604 , H01L21/32133 , H01L27/1052 , H01L27/11568 , H01L27/11578 , H01L27/1158 , H01L29/4234 , H01L29/45 , H01L29/665 , H01L29/66666 , H01L29/66787 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.
摘要翻译：在垂直型存储器件和垂直型存储器件的制造方法中，垂直存储器件包括设置在衬底上的线状绝缘层图形，柱状单晶半导体图案设置在两侧壁上设置在每个单晶半导体图案的侧壁上的绝缘层图案和晶体管。晶体管沿着单晶半导体图案的垂直方向排列，因此存储器件可以高度集成。

5. 发明授权

US07960780B2 Vertical-type semiconductor device 有权
标题翻译：垂直型半导体器件
公开(公告)号：US07960780B2
公开(公告)日：2011-06-14
申请号：US12478081
申请日：2009-06-04
申请人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
发明人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
IPC分类号： H01L29/772 , H01L21/8242
CPC分类号： H01L29/7827 , H01L27/108 , H01L27/10802 , H01L27/10876 , H01L29/66666 , H01L29/7841
摘要： In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties. The mask pattern is not provided on the upper surface of the single-crystalline semiconductor pattern in the second impurity region, to thereby reduce failures of processes.
摘要翻译：在垂直型半导体器件中，其制造方法及其操作方法，垂直型半导体器件包括：具有设置在基板上的柱状的单晶半导体图案，单晶半导体图案，并且具有比单晶半导体图案的上表面低的上表面，形成在栅极的上表面上的掩模图案，所述掩模图案具有与单个半导体图案的上表面共面的上表面晶体半导体图案，在单晶半导体图案下的衬底中的第一杂质区域和在单晶半导体图案的上表面下方的第二杂质区域。形成在单晶半导体图案中的垂直型立柱晶体可以提供优异的电性能。在第二杂质区域中的单晶半导体图案的上表面上没有设置掩模图案，从而减少处理的失败。

6. 发明申请

US20100123182A1 VERTICAL TYPE SEMICONDUCTOR DEVICE 失效
标题翻译：垂直型半导体器件
公开(公告)号：US20100123182A1
公开(公告)日：2010-05-20
申请号：US12620923
申请日：2009-11-18
申请人： Yong-Hoon SON , Jong-Wook Lee , Jong-Hyuk Kang
发明人： Yong-Hoon SON , Jong-Wook Lee , Jong-Hyuk Kang
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , H01L27/11578 , H01L29/66833 , H01L29/7923
摘要： A vertical pillar semiconductor device includes a substrate, a single crystalline semiconductor pattern, a gate insulation layer structure and a gate electrode. The substrate may include a first impurity region. The single crystalline semiconductor pattern may be on the first impurity region. The single crystalline semiconductor pattern has a pillar shape substantially perpendicular to the substrate. A second impurity region may be formed in an upper portion of the single crystalline semiconductor pattern. The gate insulation layer structure may include a charge storage pattern, the gate insulation layer structure on a sidewall of the single crystalline semiconductor pattern. The gate electrode may be formed on the gate insulation layer structure and opposite the sidewall of the single crystalline semiconductor pattern. The gate electrode has an upper face substantially lower than that of the single crystalline semiconductor pattern.
摘要翻译：垂直柱半导体器件包括衬底，单晶半导体图案，栅极绝缘层结构和栅电极。衬底可以包括第一杂质区域。单晶半导体图案可以在第一杂质区上。单晶半导体图案具有基本上垂直于基板的柱形。可以在单晶半导体图案的上部形成第二杂质区。栅极绝缘层结构可以包括电荷存储图案，单晶半导体图案的侧壁上的栅极绝缘层结构。栅电极可以形成在栅极绝缘层结构上并且与单晶半导体图案的侧壁相对。栅电极具有比单晶半导体图案基本上低的上表面。

7. 发明申请

US20150263038A1 VERTICAL-TYPE SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：垂直型半导体器件及其制造方法
公开(公告)号：US20150263038A1
公开(公告)日：2015-09-17
申请号：US14723644
申请日：2015-05-28
申请人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
发明人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
IPC分类号： H01L27/115 , H01L21/306 , H01L29/423 , H01L21/02 , H01L21/3213 , H01L21/285 , H01L29/66 , H01L21/28
CPC分类号： H01L27/11582 , H01L21/02524 , H01L21/02587 , H01L21/02598 , H01L21/02675 , H01L21/28282 , H01L21/28518 , H01L21/30604 , H01L21/32133 , H01L27/1052 , H01L27/11568 , H01L27/11578 , H01L27/1158 , H01L29/4234 , H01L29/45 , H01L29/665 , H01L29/66666 , H01L29/66787 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.
摘要翻译：在垂直型存储器件和垂直型存储器件的制造方法中，垂直存储器件包括设置在衬底上的线状绝缘层图形，柱状单晶半导体图案设置在两侧壁上设置在每个单晶半导体图案的侧壁上的绝缘层图案和晶体管。晶体管沿着单晶半导体图案的垂直方向排列，因此存储器件可以高度集成。

8. 发明授权

US08324056B2 Vertical type semiconductor device and method of manufacturing a vertical type semiconductor device 有权
标题翻译：垂直型半导体器件及其制造方法
公开(公告)号：US08324056B2
公开(公告)日：2012-12-04
申请号：US13317022
申请日：2011-10-07
申请人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
发明人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L29/7827 , H01L29/66666
摘要： A vertical pillar semiconductor device may include a substrate, a group of channel patterns, a gate insulation layer pattern and a gate electrode. The substrate may be divided into an active region and an isolation layer. A first impurity region may be formed in the substrate corresponding to the active region. The group of channel patterns may protrude from a surface of the active region and may be arranged parallel to each other. A second impurity region may be formed on an upper portion of the group of channel patterns. The gate insulation layer pattern may be formed on the substrate and a sidewall of the group of channel patterns. The gate insulation layer pattern may be spaced apart from an upper face of the group of channel patterns. The gate electrode may contact the gate insulation layer and may enclose a sidewall of the group of channel patterns.
摘要翻译：垂直柱半导体器件可以包括衬底，沟道图案组，栅极绝缘层图案和栅电极。衬底可分为有源区和隔离层。可以在对应于有源区的衬底中形成第一杂质区。通道图案组可以从有源区域的表面突出并且可以彼此平行地布置。第二杂质区可以形成在沟道图案组的上部。栅极绝缘层图案可以形成在衬底和沟道图案组的侧壁上。栅极绝缘层图案可以与沟道图案组的上表面间隔开。栅电极可以接触栅极绝缘层并且可以包围沟道图案组的侧壁。

9. 发明申请

US20120028428A1 Vertical type semiconductor device and method of manufacturing a vertical type semiconductor device 有权
公开(公告)号：US20120028428A1
公开(公告)日：2012-02-02
申请号：US13317022
申请日：2011-10-07
申请人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
发明人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
IPC分类号： H01L21/336
CPC分类号： H01L29/7827 , H01L29/66666
摘要： A vertical pillar semiconductor device may include a substrate, a group of channel patterns, a gate insulation layer pattern and a gate electrode. The substrate may be divided into an active region and an isolation layer. A first impurity region may be formed in the substrate corresponding to the active region. The group of channel patterns may protrude from a surface of the active region and may be arranged parallel to each other. A second impurity region may be formed on an upper portion of the group of channel patterns. The gate insulation layer pattern may be formed on the substrate and a sidewall of the group of channel patterns. The gate insulation layer pattern may be spaced apart from an upper face of the group of channel patterns. The gate electrode may contact the gate insulation layer and may enclose a sidewall of the group of channel patterns.

10. 发明授权

US08063438B2 Vertical-type semiconductor devices 有权
标题翻译：垂直型半导体器件
公开(公告)号：US08063438B2
公开(公告)日：2011-11-22
申请号：US12380565
申请日：2009-02-27
申请人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
发明人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
IPC分类号： H01L29/66
CPC分类号： H01L27/11582 , H01L21/02524 , H01L21/02587 , H01L21/02598 , H01L21/02675 , H01L21/28282 , H01L21/28518 , H01L21/30604 , H01L21/32133 , H01L27/1052 , H01L27/11568 , H01L27/11578 , H01L27/1158 , H01L29/4234 , H01L29/45 , H01L29/665 , H01L29/66666 , H01L29/66787 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.
摘要翻译：在垂直型存储器件和垂直型存储器件的制造方法中，垂直存储器件包括设置在衬底上的线状绝缘层图形，柱状单晶半导体图案设置在两侧壁上设置在每个单晶半导体图案的侧壁上的绝缘层图案和晶体管。晶体管沿着单晶半导体图案的垂直方向排列，因此存储器件可以高度集成。

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