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1. 发明授权

US5565370A Method of enhancing the current gain of bipolar junction transistors 失效
标题翻译：提高双极结型晶体管电流增益的方法
公开(公告)号：US5565370A
公开(公告)日：1996-10-15
申请号：US385005
申请日：1995-02-07
申请人： Rick C. Jerome , Ian R. C. Post , Gary M. Wodek
发明人： Rick C. Jerome , Ian R. C. Post , Gary M. Wodek
IPC分类号： H01L21/331 , H01L29/08 , H01L29/417 , H01L21/265
CPC分类号： H01L29/66272 , H01L29/0804 , H01L29/41708 , Y10S148/124
摘要： The present invention teaches a method and structure of enhancing the current gain characteristics of a bipolar junction transistor using a semiconductor substrate comprising a base, an emitter and a collector and an interface at the emitter, such that a carrier current conducts between the base and the emitter. Further, a first polysilicon layer is formed superjacent the interface, and is implanted with O.sub.2. Subsequently, the substrate is heated such that the emitter interface is obstructed by a silicon dioxide formation, thereby blocking a portion of carrier current from passing through the interface.
摘要翻译：本发明教导了使用包括基极，发射极和集电极以及在发射极处的界面的半导体衬底来增强双极结型晶体管的电流增益特性的方法和结构，使得载流子电流在基极和发射器。此外，在界面之上形成第一多晶硅层，并注入O2。随后，加热衬底，使得发射极界面被二氧化硅形成所阻挡，从而阻止载流子电流的一部分通过界面。

2. 发明授权

US5420050A Method of enhancing the current gain of bipolar junction transistors 失效
标题翻译：提高双极结型晶体管电流增益的方法
公开(公告)号：US5420050A
公开(公告)日：1995-05-30
申请号：US170542
申请日：1993-12-20
申请人： Rick C. Jerome , Ian R. C. Post , Gary M. Wodek
发明人： Rick C. Jerome , Ian R. C. Post , Gary M. Wodek
IPC分类号： H01L21/331 , H01L29/08 , H01L29/417
CPC分类号： H01L29/66272 , H01L29/0804 , H01L29/41708 , Y10S148/124
摘要： The present invention teaches a method and structure of enhancing the current gain characteristics of a bipolar junction transistor. The method comprises the step of forming a patterned silicon dioxide layer superjacent a semiconductor substrate comprising a base, an emitter and a collector, such that a carrier current conducts between the base and the emitter. The silicon dioxide layer forms an interface on the substrate at the emitter. Further, a first polysilicon layer is formed superjacent both the patterned silicon dioxide layer and the interface, and is implanted with O.sub.2. Subsequently, the substrate is heated such that the emitter interface is obstructed by a silicon dioxide formation, thereby blocking a portion of carrier current from passing through the interface.
摘要翻译：本发明教导了增强双极结型晶体管的电流增益特性的方法和结构。该方法包括在包括基极，发射极和集电极的半导体衬底之上形成图案化二氧化硅层的步骤，使得载流子电流在基极和发射极之间导通。二氧化硅层在发射极处在衬底上形成界面。此外，在图案化二氧化硅层和界面上方形成第一多晶硅层，并且注入O2。随后，加热衬底，使得发射极界面被二氧化硅形成所阻挡，从而阻止载流子电流的一部分通过界面。

3. 发明授权

US5561073A Method of fabricating an isolation trench for analog bipolar devices in harsh environments 失效
标题翻译：在恶劣环境下制造模拟双极器件的隔离沟槽的方法
公开(公告)号：US5561073A
公开(公告)日：1996-10-01
申请号：US226804
申请日：1994-04-12
申请人： Rick C. Jerome , Ian R. C. Post
发明人： Rick C. Jerome , Ian R. C. Post
IPC分类号： H01L21/331 , H01L21/762 , H01L27/082 , H01L21/265
CPC分类号： H01L29/66265 , H01L21/76235 , H01L27/082
摘要： The present invention teaches a method of making an isolation trench. First, a silicon on insulator ("SOI") structure is provided having a conductive layer superjacent the insulator of the SOI. Second, a trench is formed down to the insulator of the SOI, thereby creating a first and second conductive region. Third, a first silicon dioxide layer is formed conformally with the sidewalls of the first and second conductive region. Fourth, a second silicon dioxide layer is formed conformally and superjacent the first silicon dioxide layer. Fifth, the remaining areas unfilled in the trench are filled with an undoped polysilicon filling. Sixth, the polysilicon layer is planarized. Seventh, an oxide cap is formed on top of the polysilicon refill. Eight, an isolation mask is formed, and the active area openings within the structure are etched down to the single crystal silicon.
摘要翻译：本发明教导了制造隔离沟槽的方法。首先，提供绝缘体上硅（SOI）结构，其具有超过SOI绝缘体的导电层。第二，沟槽形成在SOI的绝缘体之下，从而产生第一和第二导电区域。第三，第一二氧化硅层与第一和第二导电区域的侧壁保形地形成。第四，第二二氧化硅层与第一二氧化硅层保形地相邻地形成。第五，填埋在沟槽中的剩余区域充满了未掺杂的多晶硅填料。第六，多晶硅层被平坦化。第七，在多晶硅再填充物的顶部形成氧化物盖。八，形成隔离掩模，将结构内的有源区开口刻蚀成单晶硅。

4. 发明授权

US5670394A Method of making bipolar transistor having amorphous silicon contact as emitter diffusion source 失效
标题翻译：制造具有非晶硅接触的双极晶体管作为发射极扩散源的方法
公开(公告)号：US5670394A
公开(公告)日：1997-09-23
申请号：US317155
申请日：1994-10-03
申请人： Rick C. Jerome , Ian R. C. Post
发明人： Rick C. Jerome , Ian R. C. Post
IPC分类号： H01L21/225 , H01L21/331 , H01L21/8228 , H01L21/265
CPC分类号： H01L29/66272 , H01L21/2257 , H01L21/8228 , Y10S148/01 , Y10S148/011
摘要： The present invention teaches a method for fabricating a bipolar junction transistor ("BJT") from a semiconductor substrate having a base region, wherein the BJT comprises an increased Early voltage. The method initially comprises the step of forming a patterned interlevel dielectric layer superjacent the substrate such that a segment of the substrate is exposed. Subsequently, a contact comprising a material having a grain size smaller than polycrystalline silicon is formed superjacent the patterned interlevel dielectric layer and the segment of the substrate exposed. The contact is then implanted with a dopant. Once implanted, the substrate is annealed to enable the dopant to diffuse from the contact into the base region impeded by the grain size to form an emitter region and thereby increase the Early voltage of the bipolar junction transistor.
摘要翻译：本发明教导了一种从具有基极区域的半导体衬底制造双极结型晶体管（“BJT”）的方法，其中BJT包括增加的早期电压。该方法最初包括以下步骤：在衬底之上形成图案化的层间电介质层，使得衬底的一部分被暴露。随后，包含具有小于多晶硅的晶粒尺寸的材料的触点形成在图案化的层间电介质层的上方，并且衬底的部分被暴露。然后用掺杂剂注入接触。一旦被植入，衬底被退火以使掺杂剂从接触扩散到由晶粒尺寸阻挡的基极区域中，以形成发射极区域，从而增加双极结型晶体管的早期电压。

5. 发明申请

US20150171218A1 MULTI-THRESHOLD VOLTAGE DEVICES AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS 有权
标题翻译：多电压电压器件及相关技术及配置
公开(公告)号：US20150171218A1
公开(公告)日：2015-06-18
申请号：US14108265
申请日：2013-12-16
申请人： Joseph M. Steigerwald , Tahir Ghani , Jenny Hu , Ian R. C. Post
发明人： Joseph M. Steigerwald , Tahir Ghani , Jenny Hu , Ian R. C. Post
IPC分类号： H01L29/78 , H01L29/423 , H01L21/28 , H01L29/66
CPC分类号： H01L29/7831 , H01L21/28114 , H01L21/823431 , H01L21/82345 , H01L21/823456 , H01L27/0886 , H01L29/42372 , H01L29/42376 , H01L29/4908 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66484 , H01L29/66772 , H01L29/66795 , H01L29/7855 , H01L29/7856 , H01L29/78645
摘要： Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了多阈值电压装置及相关联的技术和配置。在一个实施例中，一种装置包括半导体衬底，设置在半导体衬底上的沟道体，具有与沟道本体耦合的第一厚度的第一栅电极和具有与沟道本体耦合的第二厚度的第二栅电极，其中，第一厚度大于第二厚度。可以描述和/或要求保护其他实施例。

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