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1. 发明申请

US20060167645A1 Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) 有权
标题翻译：用于在集成电路（IC）的扫描测试期间补偿时钟周期伸长的装置和方法
公开(公告)号：US20060167645A1
公开(公告)日：2006-07-27
申请号：US11389971
申请日：2006-03-27
申请人： Richard Rogers , Jeffrey Rearick , Cory Groth
发明人： Richard Rogers , Jeffrey Rearick , Cory Groth
IPC分类号： G01R27/28
CPC分类号： G01R31/318552 , G01R31/31858
摘要： An apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) comprises operating a clock associated with the IC at a frequency (fTARGET) at which IC operation is sought to be determined, measuring the actual clock period (TCLOCK—OUT) at a clock output, scan testing the IC, measuring the actual clock period (TSCAN—CLOCK—OUT) at the clock output, determining a delay by calculating the difference between TSCAN—CLOCK—OUT and TCLOCK—OUT, and compensating for the delay by increasing the clock frequency during scan test.
摘要翻译：用于在集成电路（IC）的扫描测试期间补偿时钟周期伸长的装置和方法包括以寻求确定IC操作的频率（f> TARGET ）操作与IC相关联的时钟，在时钟输出端测量实际时钟周期（T - OUT> ），对IC进行扫描测试，测量实际时钟周期（T _{SCAN - - / SUB> 在时钟输出端，通过计算T SCAN < SUB> CLOCK _{> 和T - _{OUT ，并通过在扫描测试期间增加时钟频率来补偿延迟。}}}

2. 发明申请

US20050222795A1 Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) 失效
标题翻译：用于在集成电路（IC）的扫描测试期间补偿时钟周期伸长的装置和方法
公开(公告)号：US20050222795A1
公开(公告)日：2005-10-06
申请号：US10818884
申请日：2004-04-06
申请人： Richard Rodgers , Jeffrey Rearick , Cory Groth
发明人： Richard Rodgers , Jeffrey Rearick , Cory Groth
IPC分类号： G01R31/3185 , G06F19/00
CPC分类号： G01R31/318552 , G01R31/31858
摘要： An apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) comprises operating a clock associated with the IC at a frequency (fTARGET) at which IC operation is sought to be determined, measuring the actual clock period (TCLOCK—OUT) at a clock output, scan testing the IC, measuring the actual clock period (TSCAN—CLOCK—OUT) at the clock output, determining a delay by calculating the difference between TSCAN—CLOCK—OUT and TCLOCK—OUT, and compensating for the delay by increasing the clock frequency during scan test.
摘要翻译：用于在集成电路（IC）的扫描测试期间补偿时钟周期伸长的装置和方法包括以寻求确定IC操作的频率（f> TARGET ）操作与IC相关联的时钟，在时钟输出端测量实际时钟周期（T - OUT> ），对IC进行扫描测试，测量实际时钟周期（T _{SCAN - - / SUB> 在时钟输出端，通过计算T SCAN < SUB> CLOCK _{> 和T - _{OUT ，并通过在扫描测试期间增加时钟频率来补偿延迟。}}}

3. 发明申请

US20070001661A1 DELAY-LOCKED LOOP AND A METHOD OF TESTING A DELAY-LOCKED LOOP 有权
标题翻译：延迟锁定环路和延迟锁定环路的测试方法
公开(公告)号：US20070001661A1
公开(公告)日：2007-01-04
申请号：US11468955
申请日：2006-08-31
申请人： Alvin LOKE , Michael Gilsdorf , Peter Meier , Jeffrey Rearick
发明人： Alvin LOKE , Michael Gilsdorf , Peter Meier , Jeffrey Rearick
IPC分类号： G01R23/12
CPC分类号： H03L7/07 , H03L7/0812
摘要： A delay-locked loop (DLL) of an integrated circuit (IC) with testing circuitry and a method for testing a DLL. During test mode, a phase comparator of the DLL receives a test clock in place of the reference clock and determines the phase difference between the test clock and the clock fed back to the DLL from a clock buffer tree. A variable delay element of the DLL then shifts the reference clock in time by an amount that depends on that phase difference. The variable delay element can be exercised by varying the phase of the test clock with respect to the reference clock by a known phase offset to cause the variable delay element to produce a range of delays. Whether the variable delay element is functioning properly can be determined by checking whether the phase of the test clock is aligned with the phase of the feedback clock.
摘要翻译：具有测试电路的集成电路（IC）的延迟锁定环（DLL）和用于测试DLL的方法。在测试模式期间，DLL的相位比较器代替参考时钟接收测试时钟，并从时钟缓冲器树中确定测试时钟与反馈到DLL的时钟之间的相位差。然后，DLL的可变延迟元件将参考时钟在时间上移动取决于该相位差的量。可以通过将测试时钟相对于参考时钟的相位改变已知的相位偏移来使可变延迟元件产生延迟范围来实现可变延迟元件。可以通过检查测试时钟的相位是否与反馈时钟的相位对准来确定可变延迟元件是否正常工作。

4. 发明授权

US07502978B2 Systems and methods for reconfiguring scan chains 有权
标题翻译：用于重新配置扫描链的系统和方法
公开(公告)号：US07502978B2
公开(公告)日：2009-03-10
申请号：US11314570
申请日：2005-12-21
申请人： John Bratt , Jeffrey Rearick
发明人： John Bratt , Jeffrey Rearick
IPC分类号： G01R31/28
CPC分类号： G01R31/318536 , G01R31/318544
摘要： Systems and methods for reconfiguring scan chains are provided. A representative system incorporates a first scan chain of flip-flops operative in either a normal mode or a rotate mode such that, if the first scan chain is operative in the normal mode, inputs are provided to the flip-flops in sequential order with a first of the flip-flops receiving an input prior to a second of the flip-flops, and, if the first scan chain is operative in the rotate mode, inputs are provided to the flip-flops with the first of the flip-flops receiving an input subsequent to the second of the flip-flops.
摘要翻译：提供了重新配置扫描链的系统和方法。代表性系统包括以正常模式或旋转模式操作的触发器的第一扫描链，使得如果第一扫描链在正常模式下操作，则按顺序向触发器提供输入，触发器中的第一触发器在第二触发器之前接收输入，并且如果第一扫描链在旋转模式下操作，则将触发器中的第一触发器接收到输入在第二个触发器之后的输入。

5. 发明申请

US20060156139A1 Systems and methods for facilitating testing of integrated circuits 审中-公开
标题翻译：用于促进集成电路测试的系统和方法
公开(公告)号：US20060156139A1
公开(公告)日：2006-07-13
申请号：US11311013
申请日：2005-12-19
申请人： John Rohrbaugh , Jeffrey Rearick
发明人： John Rohrbaugh , Jeffrey Rearick
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31905 , G01R31/3172 , G01R31/31926
摘要： Systems and methods for testing integrated circuits (ICs) are provided. In this regard, a representative method involves an IC having a first pad configured as a signal interface for components external to the IC, the first pad having a first receiver configured to receive an input signal from a component external to the IC. The method comprises: electrically interconnecting automated test equipment (ATE) with the IC; providing at least one stimulus such that the IC detects a presence of a signal short between the first pad and the second pad; and receiving information corresponding to the signal short.
摘要翻译：提供了用于测试集成电路（IC）的系统和方法。在这方面，代表性的方法涉及具有被配置为用于IC外部的组件的信号接口的第一焊盘的IC，第一焊盘具有被配置为从IC外部的部件接收输入信号的第一接收器。该方法包括：将自动测试设备（ATE）与IC互连; 提供至少一个刺激，使得IC检测在第一焊盘和第二焊盘之间存在短路的信号; 并且接收对应于信号短的信息。

6. 发明申请

US20060150040A1 Systems and methods for reconfiguring scan chains 有权
公开(公告)号：US20060150040A1
公开(公告)日：2006-07-06
申请号：US11314570
申请日：2005-12-21
申请人： John Bratt , Jeffrey Rearick
发明人： John Bratt , Jeffrey Rearick
IPC分类号： G01R31/28
CPC分类号： G01R31/318536 , G01R31/318544
摘要： Systems and methods for reconfiguring scan chains are provided. A representative system incorporates a first scan chain of flip-flops operative in either a normal mode or a rotate mode such that, if the first scan chain is operative in the normal mode, inputs are provided to the flip-flops in sequential order with a first of the flip-flops receiving an input prior to a second of the flip-flops, and, if the first scan chain is operative in the rotate mode, inputs are provided to the flip-flops with the first of the flip-flops receiving an input subsequent to the second of the flip-flops.

7. 发明申请

US20050229056A1 Circuit and method for comparing circuit performance between functional and AC scan testing in an integrated circuit (IC) 有权
标题翻译：用于比较集成电路（IC）中的功能和AC扫描测试之间的电路性能的电路和方法
公开(公告)号：US20050229056A1
公开(公告)日：2005-10-13
申请号：US10818866
申请日：2004-04-06
申请人： John Rohrbaugh , Jeffrey Rearick
发明人： John Rohrbaugh , Jeffrey Rearick
IPC分类号： G01R31/28 , G01R31/3185
CPC分类号： G01R31/318566 , G01R31/318577 , G01R31/31858
摘要： A circuit and method for determining operating speed of a clock associated with an integrated circuit (IC), comprises an IC logic element, a scan chain, and a calibration circuit comprising a first plurality of flip-flops and a combinational delay line. The calibration circuit operates in a functional test mode and in a scan test mode to determine a clock signal delay between the functional test mode and the scan test mode.
摘要翻译：用于确定与集成电路（IC）相关联的时钟的操作速度的电路和方法包括IC逻辑元件，扫描链和包括第一多个触发器和组合延迟线的校准电路。校准电路在功能测试模式和扫描测试模式下工作，以确定功能测试模式和扫描测试模式之间的时钟信号延迟。

8. 发明申请

US20060123305A1 Method and apparatus for an embedded time domain reflectometry test 有权
公开(公告)号：US20060123305A1
公开(公告)日：2006-06-08
申请号：US10996113
申请日：2004-11-23
申请人： David Linam , Jeffrey Rearick , Guy Humphrey
发明人： David Linam , Jeffrey Rearick , Guy Humphrey
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/11 , G01R31/31717 , G01R31/31855 , G01R31/318572
摘要： A method and apparatus for testing an integrated circuit interconnect comprises an IC having circuitry embedded in the IC capable of providing a pseudo time domain reflectometry test by launching a test transition onto the interconnect and capturing a reflection of the test transition.

9. 发明申请

US20060095818A1 System and method for automatic masking of compressed scan chains with unbalanced lengths 有权
公开(公告)号：US20060095818A1
公开(公告)日：2006-05-04
申请号：US10980961
申请日：2004-11-04
申请人： John Bratt , Jeffrey Rearick
发明人： John Bratt , Jeffrey Rearick
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： A scan test architecture is implemented. The scan test architecture provides a method of performing scan test of unbalanced scan chains. The scan test architecture generates a control signal (i.e., masking signal) to mask bits in an unbalanced scan chain. In one embodiment, the control signal is generated with a logic gate, a comparator, and a counter.

10. 发明申请

US20050060624A1 Programmable hysteresis for boundary-scan testing 有权
标题翻译：边界扫描测试的可编程滞后
公开(公告)号：US20050060624A1
公开(公告)日：2005-03-17
申请号：US10666770
申请日：2003-09-17
申请人： Charles Moore , Xiaoyang Zhang , Jeffrey Rearick
发明人： Charles Moore , Xiaoyang Zhang , Jeffrey Rearick
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/3177
CPC分类号： G01R31/2815 , G01R31/31855 , G01R31/318572
摘要： Disclosed is a Boundary-Scan test receiver for capturing signals during board interconnect testing. The test receiver has a comparator with a first input to receive signals during board interconnect testing, and a second input to receive a reference voltage. A programmable hysteresis circuit is coupled to at least one of the comparator's inputs. The programmable hysteresis circuit may be configured to program a hysteresis voltage and/or a hysteresis delay, both of which help prevent the comparator from integrating signal noise.
摘要翻译：公开了一种用于在板互连测试期间捕获信号的边界扫描测试接收器。测试接收机具有比较器，其具有第一输入以在电路板互连测试期间接收信号，以及第二输入以接收参考电压。可编程迟滞电路耦合到至少一个比较器的输入端。可编程迟滞电路可以被配置为对滞后电压和/或滞后延迟进行编程，这两者都有助于防止比较器积分信号噪声。

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