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1. 发明授权

US5835336A Complemetary reset scheme for micromechanical devices 失效
标题翻译：微机械装置的完整复位方案
公开(公告)号：US5835336A
公开(公告)日：1998-11-10
申请号：US818466
申请日：1997-02-24
申请人： Richard L. Knipe , Duane E. Carter , Lionel S. White
发明人： Richard L. Knipe , Duane E. Carter , Lionel S. White
IPC分类号： G02B26/08 , H02N1/00 , H02N13/00
CPC分类号： H02N1/006 , G02B26/0841
摘要： A method of operating a micromechanical device. The device is in a first state. Data for the next state of the device is loaded onto the activation circuitry of the device, where the next state may be the same state the device is currently in, or a state different from the first state. The equilibrium of the device is shifted away from the next state, by making the data appear complementary to the true data for the next state. When the trapping field is removed or lowered, and a signal to start the transition is provided, the device moves to its new state and the trapping field is reapplied. The data can be made to look complementary by either loading the complements to the true data, or by reversing the polarity of the trapping field.
摘要翻译：一种操作微机械装置的方法。设备处于第一状态。设备的下一状态的数据被加载到设备的激活电路上，其中下一状态可能是设备当前处于相同状态，或者与第一状态不同的状态。通过使数据与下一个状态的真实数据互补，器件的平衡从下一个状态转移。当捕获场被去除或降低，并且提供开始转变的信号时，装置移动到其新状态并重新应用捕获场。可以通过将补充物加载到真实数据或通过反转捕获场的极性来使数据看起来互补。

2. 发明授权

US6028690A Reduced micromirror mirror gaps for improved contrast ratio 有权
标题翻译：减少微镜反射镜间隙，提高对比度
公开(公告)号：US6028690A
公开(公告)日：2000-02-22
申请号：US197723
申请日：1998-11-23
申请人： Duane E. Carter , James D. Huffman , Rodney D. Miller , Brian L. Ray , Robert E. Meier
发明人： Duane E. Carter , James D. Huffman , Rodney D. Miller , Brian L. Ray , Robert E. Meier
IPC分类号： G02B26/08 , H04N5/74
CPC分类号： G02B26/0841
摘要： A micromirror array fabricated on a semiconductor substrate 708. The micromirrors in the micromirror array logically divided into an interior active region 704 which selectively modulates light striking the mirrors in the interior active region 704, and an exterior border region 702 for producing a dark border around the image produced by the interior active region 704. A gap between each mirror allows adjacent mirrors to rotate. The gap 712 between mirrors in the interior active region 704 of the array is larger than the gap 710 between at least some of the mirrors in the exterior border region 702. The smaller gap 710 in the exterior region 702 is enabled by restricting mirrors in the exterior region 702 to a single direction of rotation.
摘要翻译：制造在半导体衬底708上的微镜阵列。微反射镜阵列中的微反射镜在逻辑上被分为内部有源区域704，该有源区域选择性地调制在内部有源区域704中的反射镜的入射光，以及外部边界区域702，用于产生围绕由内部有源区域704产生的图像。每个反射镜之间的间隙允许相邻的反射镜旋转。阵列的内部有源区域704中的反射镜之间的间隙712大于外部边界区域702中的至少一些反射镜之间的间隙710.外部区域702中的较小间隙710通过限制外部区域702中的反射镜来实现外部区域702到单个旋转方向。

3. 发明授权

US4502915A Two-step plasma process for selective anisotropic etching of polycrystalline silicon without leaving residue 失效
标题翻译：用于选择性各向异性蚀刻多晶硅而不留下残留物的两步等离子体工艺
公开(公告)号：US4502915A
公开(公告)日：1985-03-05
申请号：US572772
申请日：1984-01-23
申请人： Duane E. Carter , Rhett B. Jucha
发明人： Duane E. Carter , Rhett B. Jucha
IPC分类号： H01L21/3213 , H01L21/306 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/32137
摘要： The disclosure relates to a two-step for selective anisotropic etching of polycrystalline silicon having a silicon dioxide base thereunder and an exposed opposing face with contaminants thereon including silicon dioxide without leaving a residue wherein the silicon is initially etched with a non-selective etchant for a distance below all contaminants and then an etchant used is a highly anisotropic selective polycrystalline silicon etchant.
摘要翻译：本公开涉及一种用于选择性各向异性蚀刻的两步骤，其中具有二氧化硅基底的多晶硅和其上具有污染物的暴露的相对面包括二氧化硅而不留下残余物，其中硅最初用非选择性蚀刻剂蚀刻用于距离低于所有污染物，然后使用的蚀刻剂是高度各向异性的选择性多晶硅蚀刻剂。

4. 发明授权

US06967054B2 Coating thickness control using surface features 失效
标题翻译：涂层厚度控制使用表面特征
公开(公告)号：US06967054B2
公开(公告)日：2005-11-22
申请号：US10382675
申请日：2003-03-06
申请人： Jay Bernard Kirk , Zuhair Hilali , Duy Phan , Darren S. Lee , Duane E. Carter , Gary A. Evans , David Alan Willis
发明人： Jay Bernard Kirk , Zuhair Hilali , Duy Phan , Darren S. Lee , Duane E. Carter , Gary A. Evans , David Alan Willis
IPC分类号： G03F7/16 , B32B3/00 , G02F1/00 , G03C5/00
CPC分类号： G03F7/162 , Y10T428/24182 , Y10T428/24479 , Y10T428/2457 , Y10T428/24612
摘要： A uniform coating is provided using surface features. Multiple ridges or other shapes are fabricated near an area of interest to allow for uniform coating in between the ridges. Areas at either ends of the ridges are left open to allow for excess pooling of photoresist liquid and to aid in obtaining uniform coating. The photoresist liquid or other coating fluid is applied to the sample and spun dry. A soft-bake process is performed to evaporate remaining solvents. An element, such as a diffractive, refractive, or reflective grating structure, is then formed in the area of interest using the uniform photoresist coating.
摘要翻译：使用表面特征提供均匀的涂层。在感兴趣的区域附近制造多个脊或其它形状，以允许在脊之间均匀涂覆。脊的任一端的区域保持开放，以允许光致抗蚀剂液体的过度汇集并有助于获得均匀的涂层。将光致抗蚀剂液体或其它涂布液施加到样品上并旋转干燥。进行软烘烤过程以蒸发剩余的溶剂。然后使用均匀的光致抗蚀剂涂层在感兴趣的区域中形成诸如衍射，折射或反射光栅结构的元件。

5. 发明授权

US06544886B2 Process for isolating an exposed conducting surface 有权
公开(公告)号：US06544886B2
公开(公告)日：2003-04-08
申请号：US09574731
申请日：2000-05-18
申请人： Jiong-Ping Lu , Qi-Zhong Hong , Duane E. Carter , Yung Liu
发明人： Jiong-Ping Lu , Qi-Zhong Hong , Duane E. Carter , Yung Liu
IPC分类号： H01L214763
CPC分类号： H01L21/02244 , H01L21/02178 , H01L21/02252 , H01L21/02255 , H01L21/28562 , H01L21/31683 , H01L21/76831 , H01L21/76834 , H01L21/76888
摘要： A method of isolating an exposed conductive surface. An aluminum layer (130) is selectively formed over the exposed conductive (106) surface (e.g., Cu) but not over the surrounding dielectric (110) surface using a thermal CVD process. The aluminum layer (130) is then oxidized to form a thin isolating aluminum-oxide (108) over only the conductive surface. The isolating aluminum-oxide provides a barrier for the Cu while taking up minimal space and reducing the effective dielectric constant.

6. 发明授权

US4842680A Advanced vacuum processor 失效
标题翻译：先进的真空处理器
公开(公告)号：US4842680A
公开(公告)日：1989-06-27
申请号：US188633
申请日：1988-05-02
申请人： Cecil J. Davis , Timothy J. Wooldridge , Duane E. Carter
发明人： Cecil J. Davis , Timothy J. Wooldridge , Duane E. Carter
IPC分类号： H01L21/00 , H01L21/677 , H01L21/687
CPC分类号： H01L21/67201 , H01L21/6719 , H01L21/67772 , H01L21/68785
摘要： A complete integrated circuit processing module, wherein multiple processing stations, each with its own vacuum isolation, are located inside a single module which is held at hard vacuum. A wafer transport arm mechanism permits interchange of wafers among the processing stations and a load lock. The load lock is equipped to remove and replace wafers from a vacuum-sealed wafer carrier. The wafers remain face-down and under hard vacuum during all the wafer handling steps.
摘要翻译：一个完整的集成电路处理模块，其中具有其自身真空隔离的多个处理站位于保持在硬真空下的单个模块内部。晶片传送臂机构允许在处理站之间交换晶片和加载锁定。负载锁被设置为从真空密封的晶片载体中移除和替换晶片。在所有晶片处理步骤期间，晶片保持面朝下且在硬真空下。

7. 发明授权

US4685999A Apparatus for plasma assisted etching 失效
标题翻译：等离子辅助蚀刻装置
公开(公告)号：US4685999A
公开(公告)日：1987-08-11
申请号：US790707
申请日：1985-10-24
申请人： Cecil J. Davis , Duane E. Carter , Rhett B. Jucha
发明人： Cecil J. Davis , Duane E. Carter , Rhett B. Jucha
IPC分类号： H01L21/302 , C23F1/00 , H01J37/32 , H01L21/3065 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01J37/3244
摘要： An apparatus for reactive ion etching or plasma etching wherein the wafer faces downward. The process gas is supplied through a distributor which is below the wafer and has orifices pointing away from the wafer. The vacuum (exhaust) port is below the distributor, so that there is no bulk gas flow near the face of the wafer. Preferably transport of the process gasses and their products to the face of the wafer is dominated by diffusion.
摘要翻译：用于反应离子蚀刻或等离子体蚀刻的装置，其中晶片面向下。工艺气体通过位于晶片下方并具有远离晶片的孔的分配器供应。真空（排气）端口位于分配器下面，使得在晶片表面附近没有大量气体流动。优选将工艺气体及其产品输送到晶片的表面，由扩散来支配。

8. 发明授权

US06184129B2 Low resistivity poly-silicon gate produced by selective metal growth 有权
标题翻译：通过选择性金属生长生产的低电阻率多晶硅栅极
公开(公告)号：US06184129B2
公开(公告)日：2001-02-06
申请号：US09405265
申请日：1999-09-23
申请人： Ming Hwang , Jiong-Ping Lu , Duane E. Carter , Wei-Yung Hsu
发明人： Ming Hwang , Jiong-Ping Lu , Duane E. Carter , Wei-Yung Hsu
IPC分类号： H01L2148
CPC分类号： H01L27/10873 , H01L21/28061 , H01L21/76885 , H01L27/10888 , H01L27/10891 , H01L29/4941 , H01L29/66545
摘要： A method for fabricating a low resistivity polymetal silicide conductor/gate comprising, the steps of forming a polysilicon (66) over a gate oxide (64) followed by protection of the polysilicon (66) with a sacrificial material (68), is disclosed. Gate sidewalls (70) are created to protect the sides of the polysilicon (66) and the sacrificial material (68), followed by stripped the sacrificial material (68) to expose the top surface of the polysilicon (66). Next, a diffusion barrier (76) is deposited over the exposed polysilicon (66) and a metal layer (78) is selectively grown on the diffusion barrier (76) to form a gate contact and conductor. Finally, a dielectric layer (80) is deposited over the selectively grown metal layer (78), the sidewalls (70) and the gate oxide (64).
摘要翻译：公开了一种用于制造低电阻率多金属硅化物导体/栅极的方法，包括以下步骤：在栅极氧化物（64）上形成多晶硅（66），随后用牺牲材料（68）保护多晶硅（66）。产生栅极侧壁（70）以保护多晶硅（66）和牺牲材料（68）的侧面，随后剥离牺牲材料（68）以暴露多晶硅（66）的顶表面。接下来，在暴露的多晶硅（66）上沉积扩散阻挡层（76），并且在扩散阻挡层（76）上选择性地生长金属层（78）以形成栅极接触和导体。最后，介电层（80）沉积在选择性生长的金属层（78），侧壁（70）和栅极氧化物（64）上。

9. 发明授权

US5512130A Method and apparatus of etching a clean trench in a semiconductor material 失效
标题翻译：蚀刻半导体材料中的清洁沟槽的方法和装置
公开(公告)号：US5512130A
公开(公告)日：1996-04-30
申请号：US209750
申请日：1994-03-09
申请人： Gabriel G. Barna , James G. Frank , Richard P. VanMeurs , Duane E. Carter
发明人： Gabriel G. Barna , James G. Frank , Richard P. VanMeurs , Duane E. Carter
IPC分类号： C23F4/00 , H01L21/302 , H01L21/3065 , H01L21/00
CPC分类号： H01J37/32082 , H01J37/32706 , H01L21/3065 , H01J2237/3347
摘要： An etching apparatus (10) includes a process chamber (12) partially surrounded by an upper electrode (14) and a lower electrode (16). A semiconductor material (18) lies within the process chamber (12) and in contact with the lower electrode (16). The lower electrode (16) is connected to a first power supply (22) operating at a substantially high frequency and is also connected to a second power supply (24) operating at a relatively low frequency. The lower frequency of the second power supply (24) provides a degree of anisotropic control to the trench etching process performed on the semiconductor material (18). The added anisotropic control allows for the elimination of sidewall deposition enhancing materials within a plasma chemistry introduced into the process chamber (12) by a gas distributor (20). Without the requirement of a sidewall deposition enhancing material during trench etching of the semiconductor material (18), buildup of residue due to sidewall deposition does not occur within process chamber (12).
摘要翻译：蚀刻装置（10）包括由上电极（14）和下电极（16）部分包围的处理室（12）。半导体材料（18）位于处理室（12）内并与下电极（16）接触。下电极（16）连接到以基本高频工作的第一电源（22），并且还连接到以较低频率工作的第二电源（24）。第二电源（24）的较低频率为在半导体材料（18）上执行的沟槽蚀刻工艺提供一定程度的各向异性控制。添加的各向异性控制允许通过气体分配器（20）消除引入处理室（12）的等离子体化学物质中的侧壁沉积增强材料。在半导体材料（18）的沟槽蚀刻期间不需要侧壁沉积增强材料，在处理室（12）内不会发生由侧壁沉积引起的残留物的积聚。

10. 发明授权

US5252506A Method to eliminate gate filaments on field plate isolated devices 失效
标题翻译：在场板隔离装置上消除栅极细丝的方法
公开(公告)号：US5252506A
公开(公告)日：1993-10-12
申请号：US879697
申请日：1992-05-05
申请人： Duane E. Carter , William R. McKee , Gishi Chung , Fred D. Fishburn
发明人： Duane E. Carter , William R. McKee , Gishi Chung , Fred D. Fishburn
IPC分类号： H01L21/8242 , H01L21/306
CPC分类号： H01L27/10861
摘要： A method is disclosed for preventing formation of undesirable polysilicon word line gate filaments in integrated circuit devices such as VLSI dynamic random access memories employing field plate isolation. Before the word lines are processed, an oxide layer is formed in the field plate openings beneath sidewalls of nitride along the edges of the field plate openings. The oxide layer partially fills an undercut area beneath a dip out of the sidewall of nitride. The dip out of the sidewall of nitride is removed. The removal of the dip out and the partial filling of the undercut area reduces the possibility of polysilicon word line filaments from forming around the edge of the field plate openings in the undercut area when the word lines are later added. A field plate isolated memory device is also disclosed wherein along the edges of the field plate openings, the partially filling oxide layer and the sidewall nitride layer are approximately coincident.
摘要翻译：公开了一种用于防止在诸如使用场板隔离的VLSI动态随机存取存储器的集成电路器件中形成不需要的多晶硅字线栅极细丝的方法。在处理字线之前，沿着场板开口的边缘在氮化物侧壁下方的场板开口中形成氧化物层。氧化物层部分地填充氮化物侧壁下方的浸渍下方的底切区域。去除氮化物侧壁的浸出。脱落区域的去除以及部分填充底切区域减少了当字线稍后添加时，多晶硅字线细丝在底切区域的场板开口的边缘周围形成的可能性。还公开了一种场板隔离存储器件，其中沿着场板开口的边缘，部分填充的氧化物层和侧壁氮化物层几乎重合。

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