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1. 发明授权

US5512130A Method and apparatus of etching a clean trench in a semiconductor material 失效
标题翻译：蚀刻半导体材料中的清洁沟槽的方法和装置
公开(公告)号：US5512130A
公开(公告)日：1996-04-30
申请号：US209750
申请日：1994-03-09
申请人： Gabriel G. Barna , James G. Frank , Richard P. VanMeurs , Duane E. Carter
发明人： Gabriel G. Barna , James G. Frank , Richard P. VanMeurs , Duane E. Carter
IPC分类号： C23F4/00 , H01L21/302 , H01L21/3065 , H01L21/00
CPC分类号： H01J37/32082 , H01J37/32706 , H01L21/3065 , H01J2237/3347
摘要： An etching apparatus (10) includes a process chamber (12) partially surrounded by an upper electrode (14) and a lower electrode (16). A semiconductor material (18) lies within the process chamber (12) and in contact with the lower electrode (16). The lower electrode (16) is connected to a first power supply (22) operating at a substantially high frequency and is also connected to a second power supply (24) operating at a relatively low frequency. The lower frequency of the second power supply (24) provides a degree of anisotropic control to the trench etching process performed on the semiconductor material (18). The added anisotropic control allows for the elimination of sidewall deposition enhancing materials within a plasma chemistry introduced into the process chamber (12) by a gas distributor (20). Without the requirement of a sidewall deposition enhancing material during trench etching of the semiconductor material (18), buildup of residue due to sidewall deposition does not occur within process chamber (12).
摘要翻译：蚀刻装置（10）包括由上电极（14）和下电极（16）部分包围的处理室（12）。半导体材料（18）位于处理室（12）内并与下电极（16）接触。下电极（16）连接到以基本高频工作的第一电源（22），并且还连接到以较低频率工作的第二电源（24）。第二电源（24）的较低频率为在半导体材料（18）上执行的沟槽蚀刻工艺提供一定程度的各向异性控制。添加的各向异性控制允许通过气体分配器（20）消除引入处理室（12）的等离子体化学物质中的侧壁沉积增强材料。在半导体材料（18）的沟槽蚀刻期间不需要侧壁沉积增强材料，在处理室（12）内不会发生由侧壁沉积引起的残留物的积聚。

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