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1. 发明授权

US5146674A Manufacturing process of a high density substrate design 失效
标题翻译：高密度基板设计的制造工艺
公开(公告)号：US5146674A
公开(公告)日：1992-09-15
申请号：US724245
申请日：1991-07-01
申请人： Richard F. Frankeny , Karl Hermann , Ronald L. Imken , Joseph LaTorre
发明人： Richard F. Frankeny , Karl Hermann , Ronald L. Imken , Joseph LaTorre
IPC分类号： H01L21/48 , H01L23/538 , H05K3/00 , H05K3/20 , H05K3/42 , H05K3/44 , H05K3/46
CPC分类号： H05K3/462 , H01L21/4857 , H01L23/5383 , H05K3/445 , H01L2924/0002 , H05K2201/09318 , H05K2201/09554 , H05K2201/09563 , H05K2203/0152 , H05K2203/066 , H05K2203/0733 , H05K3/0023 , H05K3/205 , H05K3/423 , H05K3/4641 , H05K3/4647 , Y10T29/49126 , Y10T29/49156
摘要： Substrate layers with individual bumps and cavities are provided which can be manufactured and tested in parallel and then joined into a multilayer substrate. The method of manufacturing these layers, as contemplated by the present invention, includes initially forming a plurality of vias in a layer of electrically conductive material. Next, a dielectric material, is placed adjacent the layer of conductive material. Holes which are coaxial with the vias are then formed in the dielectric material. Electrically conductive material is then deposited within the vias, thereby forming a conductive stud. Additional electrically conductive material is then deposited, on the side of the dielectric opposite the conductive material to form a signal layer, as well projections of electrically conductive material extending from the studs. A continuous layer of dielectric material is then placed adjacent the side of the substrate opposite the projections. A portion of this layer, adjacent the stud, is then removed, thereby exposing the stud and forming a cavity. The substrate layers can then be joined to form a multilayer substrate module.
摘要翻译：提供具有单独凸块和空腔的基板层，其可以并联制造和测试，然后连接到多层基板中。如本发明所设想的制造这些层的方法包括最初在导电材料层中形成多个通孔。接下来，将电介质材料放置在邻近导电材料层的位置。然后在电介质材料中形成与通孔同轴的孔。然后将导电材料沉积在通孔内，从而形成导电柱。然后在电介质的与导电材料相对的一侧上沉积附加的导电材料以形成信号层，以及从螺柱延伸的导电材料的突起。然后将连续的介电材料层放置成与衬底相对的与突起相对的一侧。然后去除邻近螺柱的该层的一部分，从而暴露螺柱并形成空腔。然后可以将衬底层接合以形成多层衬底模块。

2. 发明授权

US5065227A Integrated circuit packaging using flexible substrate 失效
标题翻译：集成电路使用柔性基板包装
公开(公告)号：US5065227A
公开(公告)日：1991-11-12
申请号：US533262
申请日：1990-06-04
申请人： Jerome A. Frankeny , Richard F. Frankeny , Karl Hermann , Ronald L. Imken
发明人： Jerome A. Frankeny , Richard F. Frankeny , Karl Hermann , Ronald L. Imken
IPC分类号： H01L21/60 , H01L21/66 , H01L23/14 , H01L23/373 , H01L23/498 , H05K1/00 , H05K3/42 , H05K3/44
CPC分类号： H05K3/429 , H01L23/142 , H01L23/3735 , H01L23/4985 , H05K3/445 , H01L2224/16 , H01L2224/16235 , H01L2924/01019 , H01L2924/01078 , H05K1/0393 , H05K2201/0154 , H05K2201/068 , H05K2201/09581 , H05K2201/09718 , H05K2201/09881 , H05K2203/0323 , H05K2203/1438 , Y10T29/41
摘要： A multilayer, flexible substrate upon which integrated circuit chips can be attached is disclosed. The input/output(I/O) connections from the chip do not radiate outward from the side of the die, but rather extend from a bottom surface. Since the I/O signal lines would not be accessible for testing once the IC chip is mounted on a substrate, each I/O line is extended outward from the IC footprint to an area on the substrate which is accessible. Additionally, an electrical path from each I/O signal port is simultaneously passed through the substrate layers upon which the chip is mounted, thus providing electrical contact of all I/O ports to the underside of the flexible substrate.An integrated circuit chip is mounted on this flexible substrate. Since each I/O line is accessible after mounting, the IC chip can be tested prior to mounting on its ultimate carrier. Once tested, the IC chip and the substrate upon which it is mounted are excised from the roll of substrate material. This excised, pretested memory package, which includes both the IC chip and the flexible substrate, can then be mounted directly onto the ultimate carrier either by reflow soldering or direct bonding.
摘要翻译：公开了可以连接集成电路芯片的多层柔性基板。来自芯片的输入/输出（I / O）连接不会从模具侧向外辐射，而是从底部表面延伸。由于一旦将IC芯片安装在基板上，I / O信号线将无法进行测试，因此每个I / O线从IC占位区向外延伸到可访问的基板上的区域。此外，来自每个I / O信号端口的电路同时通过其上安装有芯片的基板层，从而提供所有I / O端口与柔性基板的下侧的电接触。集成电路芯片安装在该柔性基板上。由于每个I / O线在安装后都可以访问，因此IC芯片可以在安装在其最终的载波上进行测试。一旦被测试，将IC芯片及其安装在其上的基板从基板材料卷上切下。包括IC芯片和柔性基板的切除的预测试存储器封装可以通过回流焊接或直接接合直接安装在极限载体上。

3. 发明授权

US5363275A Modular component computer system 失效
标题翻译：模块化组件计算机系统
公开(公告)号：US5363275A
公开(公告)日：1994-11-08
申请号：US15989
申请日：1993-02-10
申请人： Jerome A. Frankeny , Richard F. Frankeny , Karl Hermann , Ronald L. Imken
发明人： Jerome A. Frankeny , Richard F. Frankeny , Karl Hermann , Ronald L. Imken
IPC分类号： G06F1/18 , H01L23/538 , H05K1/11 , H05K1/18 , H05K3/00 , H05K3/36 , H05K1/00
CPC分类号： H05K1/189 , H01L23/5385 , H01L23/5387 , H01L2224/16225 , H01L2924/15311 , H05K1/118 , H05K2201/041 , H05K2201/053 , H05K2201/2009 , H05K3/0058 , H05K3/361 , H05K3/4691
摘要： Discrete computational elements are provided that will be connected to a base unit, and to one another or I/O devices, in order to configure a particular computer system. The base unit provides the electrical power required to energize the computational elements. A plurality of identically configured substrates are joined in a layered relation and are electrically connected with one another. These substrates are capable of being fabricated of different lengths such that they can extend outwardly from the computational element and may be connected to other computational elements. At least one integrated circuit will be placed on one side of the joined substrates and is electrically connected to each substrate layer. In this manner the ICs will be able to communicate with chips on other computational elements. A support member is also included that stiffens the plural substrate layers and independently distributes electrical power through voltage and ground potential planes, and interconnected substrate layers, to the chips. The support member will be disposed adjacent the substrate layers on a side opposite the ICs and independently attachable to the base unit by using electrical connection pins, a pluggable lip portion, or the like.
摘要翻译：提供将连接到基本单元和彼此或I / O设备的离散计算元件，以便配置特定的计算机系统。基本单元提供激励计算元件所需的电力。多个相同配置的基板以分层关系连接并且彼此电连接。这些基板能够被制造成不同的长度，使得它们可以从计算元件向外延伸并且可以连接到其它计算元件。至少一个集成电路将被放置在接合的衬底的一侧上，并且电连接到每个衬底层。以这种方式，IC将能够与其他计算元件上的芯片通信。还包括支撑构件，其硬化多个衬底层，并且通过电压和接地电位平面以及互连的衬底层独立地分配电力到芯片。支撑构件将被布置在与IC相对的一侧上的基底层附近，并且通过使用电连接销，可插入唇部等可独立地附接到基座单元。

4. 发明授权

US5037311A High density interconnect strip 失效
标题翻译：高密度互连条
公开(公告)号：US5037311A
公开(公告)日：1991-08-06
申请号：US347695
申请日：1989-05-05
申请人： Jerome A. Frankeny , Richard F. Frankeny , Javad Haj-Ali-Ahmadi , Karl Hermann , Ronald L. Imken
发明人： Jerome A. Frankeny , Richard F. Frankeny , Javad Haj-Ali-Ahmadi , Karl Hermann , Ronald L. Imken
IPC分类号： H01R43/20 , H01R12/71 , H01R13/04 , H01R13/24 , H05K1/14 , H05K3/32 , H05K3/36
CPC分类号： H01R13/2435 , H01R12/714 , H05K3/368 , H05K1/145 , H05K2201/0311 , H05K2201/0397 , H05K2201/10424 , H05K2203/167 , H05K3/325 , H05K3/365 , H05K3/366
摘要： An interconnect strip is provided for effecting electrical interconnection between pluralities of conductor pads disposed on circuit boards or the like in a high density configuration. The strip is fabricated from a polymer film carrier having laminated thereon a metal foil with preselected spring properties. After lamination, lithographic techniques from a series of electrically isolated metallic beams on the carrier. Additional chemical processing removes portions of the carrier at opposing sides of the strip to expose opposing ends of the beams which extend beyond the carrier parallel to one another in opposing directions outwards from the carrier. By urging the pads towards respective beam ends of the strip disposed between the pads until mating engagement therewith, a plurality of electrical interconnections are established through the beams. Flexural properties of the strip provide a low insertion force connection for a high density of conductors wherein the spring action of the strip assures favorable contact forces to the pads. The exposed film side of the strip may also be metalized and provided with beams or interconnected to beams on opposing side of the film by vias thereby providing a ground plane.

5. 发明授权

US5316787A Method for manufacturing electrically isolated polyimide coated vias in a flexible substrate 失效
标题翻译：在柔性基板中制造电隔离聚酰亚胺涂层通孔的方法
公开(公告)号：US5316787A
公开(公告)日：1994-05-31
申请号：US978309
申请日：1992-11-17
申请人： Richard F. Frankeny , Ronald L. Imken
发明人： Richard F. Frankeny , Ronald L. Imken
IPC分类号： H01L21/60 , H01L21/66 , H01L23/14 , H01L23/373 , H01L23/498 , H05K1/00 , H05K3/42 , H05K3/44 , C23C26/00
CPC分类号： H05K3/429 , H01L23/142 , H01L23/3735 , H01L23/4985 , H05K3/445 , H01L2224/16 , H01L2224/16235 , H01L2924/01019 , H01L2924/01078 , H05K1/0393 , H05K2201/0154 , H05K2201/068 , H05K2201/09581 , H05K2201/09718 , H05K2201/09881 , H05K2203/0323 , H05K2203/1438 , Y10T29/41
摘要： A method and system for manufacturing electrically isolated vias in a flexible substrate composed of a metal core laminated by layers of an organic material. The method includes the steps of etching via holes, hydrolyzing the inner organic surfaces of the via holes and baking a polyimide solution coated in the via holes.
摘要翻译：一种用于制造由通过有机材料层层压的金属芯构成的柔性基板中的电隔离通孔的方法和系统。该方法包括蚀刻通孔，水解通孔的内部有机表面并烘烤涂覆在通孔中的聚酰亚胺溶液的步骤。

6. 发明授权

US4943242A Zero insertion force high density connector system 失效
标题翻译：零插入力高密度连接器系统
公开(公告)号：US4943242A
公开(公告)日：1990-07-24
申请号：US347694
申请日：1989-05-05
申请人： Richard F. Frankeny , Javad Haj-ali-Ahmadi , Ronald L. Imken , Rolf Wustrau
发明人： Richard F. Frankeny , Javad Haj-ali-Ahmadi , Ronald L. Imken , Rolf Wustrau
IPC分类号： H01R13/193 , H01R12/88 , H01R24/00 , H05K7/14
CPC分类号： H05K7/1404 , H01R12/88
摘要： A system for providing low insertion force electrical interconnections between high density contacts for use in interconnecting circuit packages. A housing has disposed therein one or more pre-buckled beam connectors. Each connector has a resilient insulative strip carrying a plurality of buckling beams electrically isolated from each other. The beams are aligned on the plane defining the strip in parallel with ends extending away from the strip edges in opposing directions. Means are provided for deforming the strip within the housing prior to effecting desired interconnections whereby the beams are pre-buckled. Upon urging contacts into proximity with the beam ends, the buckling force is released causing each beam's ends to be urged away from the strip into engagement with respective contacts, thereby effecting desired interconnection between contacts and through one or more beams.

7. 发明授权

US5509200A Method of making laminar stackable circuit board structure 失效
标题翻译：层叠电路板结构的制作方法
公开(公告)号：US5509200A
公开(公告)日：1996-04-23
申请号：US342506
申请日：1994-11-21
申请人： Jerome A. Frankeny , Richard F. Frankeny , Ronald L. Imken , Keith A. Vanderlee
发明人： Jerome A. Frankeny , Richard F. Frankeny , Ronald L. Imken , Keith A. Vanderlee
IPC分类号： H01L23/538 , H05K1/11 , H05K1/16 , H05K3/00 , H05K3/44 , H05K3/46 , H01K3/10
CPC分类号： H05K3/462 , H01L23/5385 , H05K1/112 , H05K1/162 , H05K3/445 , H05K3/4641 , H01L2224/16225 , H05K2201/0175 , H05K2201/0179 , H05K2201/0317 , H05K2201/0355 , H05K2201/0373 , H05K2201/09309 , H05K2201/09509 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/09718 , H05K2201/10378 , H05K2203/0307 , H05K3/0023 , H05K3/0094 , H05K3/4623 , Y10S428/901 , Y10T29/49165
摘要： Method and apparatus for fabricating fine pitch pattern multilayer printed circuit boards involving laminar stackable board layers providing power distribution, signal distribution and capacitive decoupling. In one respect, the invention relates to the fabrication of board layers by beginning with a metallic core, patterning the core, selectively enclosing the core in a dielectric, selectively depositing metal to form vias, plugs and signal lines, and forming dendrites with joining metallurgy on the vias and plugs to provide stackable connection from above or below the plane of the board layer. In another aspect, the invention is directed to the use of a sol-gel process to form a thin high dielectric constant crystalline film onto a metallic sheet followed with a deposition of a metallic layer onto the high dielectric constant film. The film serves as the dielectric of a capacitor layer which is thereafter in succession patterned, covered by a dielectric, and has selectively deposited a metallic layer for interconnecting the capacitor and forming vias. The ends of the vias are thereafter subject to dendritic growth and joining metallurgy to provide stackable interconnection capability.
摘要翻译：用于制造精细间距图案多层印刷电路板的方法和装置，其包括提供功率分配，信号分配和电容去耦的层叠堆叠板层。在一个方面，本发明涉及通过金属芯开始制造板层，图案化芯，选择性地将芯包围在电介质中，选择性地沉积金属以形成通孔，插塞和信号线，以及用连接冶金形成树突在通孔和插头上，以从板层的平面上方或下方提供可堆叠连接。在另一方面，本发明涉及使用溶胶 - 凝胶法在金属片上形成薄的高介电常数结晶膜，随后在高介电常数膜上沉积金属层。该膜用作电容器层的电介质，其后连续地被图案化，被电介质覆盖，并且已经选择性地沉积用于互连电容器和形成通孔的金属层。然后通孔的端部经历树枝状生长并连接冶金以提供可堆叠的互连能力。

8. 发明授权

US5229916A Chip edge interconnect overlay element 失效
标题翻译：芯片边缘互连覆盖元件
公开(公告)号：US5229916A
公开(公告)日：1993-07-20
申请号：US846301
申请日：1992-03-04
申请人： Richard F. Frankeny , Ronald L. Imken
发明人： Richard F. Frankeny , Ronald L. Imken
IPC分类号： H01L21/60 , H01L23/498 , H05K1/18
CPC分类号： H01L24/73 , H01L23/4985 , H01L2224/05553 , H01L2224/05554 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L24/48 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01055 , H01L2924/01075 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12042 , H01L2924/14
摘要： A chip overlay element is formed of a flexible substrate of polymer having electrically conductive material applied to one side thereof and circuitized to form signal lines. A metal stiffener/heat spreader is laminated to the polymer on the opposite side of the conductor. I/Os are formed on one end of the signal lines of the circuitized layer (near the end of the overlay element) and interconnection pads, bumps, or the like are formed on the opposite end (near the center of the element). The metal stiffener is then etched to form three distinct areas. The chip edge is then placed on the center metal stiffener area and bonded, with the other two stiffener areas being bent around the chip and bonded to the corresponding chip sides. The original I/Os are then electrically connected to the I/Os formed on the signal lines of the overlay element.
摘要翻译：芯片覆盖元件由具有施加到其一侧的导电材料的聚合物的柔性基板形成并电路化以形成信号线。金属加强件/散热器层叠在导体相反侧的聚合物上。 I / O形成在电路化层的信号线的一端（靠近覆盖元件的端部），并且在相对端（元件的中心附近）形成互连焊盘，凸起等。然后金属加强件被蚀刻以形成三个不同的区域。然后将芯片边缘放置在中心金属加强件区域上并结合，另外两个加强区域围绕芯片弯曲并结合到相应的芯片侧。然后将原始I / O电连接到形成在覆盖元件的信号线上的I / O。

9. 发明授权

US5198693A Aperture formation in aluminum circuit card for enhanced thermal dissipation 失效
标题翻译：铝电路卡中的孔径形成用于增强散热
公开(公告)号：US5198693A
公开(公告)日：1993-03-30
申请号：US831855
申请日：1992-02-05
申请人： Ronald L. Imken , Joseph LaTorre
发明人： Ronald L. Imken , Joseph LaTorre
IPC分类号： B42D15/10 , G06K19/077 , H01L23/12 , H01L23/373 , H01L23/40 , H05K1/02 , H05K1/05 , H05K1/18 , H05K3/00 , H05K3/44 , H05K7/20
CPC分类号： H05K1/0204 , H01L23/3735 , H01L23/4006 , H05K1/021 , H01L2023/4043 , H01L2023/4062 , H01L2224/48091 , H01L2224/48227 , H01L24/48 , H01L2924/00014 , H01L2924/01014 , H01L2924/01078 , H01L2924/14 , H01L2924/19041 , H05K1/053 , H05K1/182 , H05K2201/09054 , H05K2203/0315 , H05K2203/049 , H05K2203/135
摘要： A method and system are provided for forming apertures in the dielectric layers of an aluminum circuit to allow electrical connection to the aluminum core and enhance the thermal efficiency of integrated circuit devices attached thereto. Specifically, the apertures are formed to accommodate the ICs and allow them to be in direct contact with the aluminum core layer of the circuit card. The apertures are formed by placing a photoresist material on the aluminum core in locations corresponding to the desired locations of the aperture. The photoresist material is used as a "placeholder" during subsequent processing. The aluminum is then anodized to form aluminum oxide and a polymer material is then electrophoretically placed over the aluminum oxide. The photoresist "placeholder" is then removed, leaving an aperture that will accommodate an IC. The top of the polymer layer can then be circuitized to interconnect the chips.
摘要翻译：提供了一种用于在铝电路的电介质层中形成孔的方法和系统，以允许与铝芯的电连接并增强与其连接的集成电路器件的热效率。具体地，形成孔以容纳IC并允许它们与电路卡的铝芯层直接接触。通过将光致抗蚀剂材料放置在对应于孔的所需位置的位置的铝芯上而形成孔。光致抗蚀剂材料在后续处理中被用作“占位符”。然后将铝阳极氧化以形成氧化铝，然后将聚合物材料电泳放置在氧化铝上。然后去除光致抗蚀剂“占位符”，留下将容纳IC的孔。然后可以将聚合物层的顶部电路化以使芯片互连。

10. 发明授权

US07947429B2 Long length flexible circuits and method of making same 有权
标题翻译：长长度柔性电路及其制作方法
公开(公告)号：US07947429B2
公开(公告)日：2011-05-24
申请号：US11830666
申请日：2007-07-30
申请人： Ronald L. Imken
发明人： Ronald L. Imken
IPC分类号： G03F7/22
CPC分类号： H05K3/0082 , H05K1/0393 , H05K2203/056 , H05K2203/1545
摘要： Disclosed is a method for making long flexible circuits. Some of the long circuits may be made using a single photoimaging mask. Also disclosed are flexible circuits made by this method.
摘要翻译：公开了一种制造长柔性电路的方法。一些长电路可以使用单个光成像掩模制成。还公开了通过该方法制造的柔性电路。

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