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1. 发明授权

US5037311A High density interconnect strip 失效
标题翻译：高密度互连条
公开(公告)号：US5037311A
公开(公告)日：1991-08-06
申请号：US347695
申请日：1989-05-05
申请人： Jerome A. Frankeny , Richard F. Frankeny , Javad Haj-Ali-Ahmadi , Karl Hermann , Ronald L. Imken
发明人： Jerome A. Frankeny , Richard F. Frankeny , Javad Haj-Ali-Ahmadi , Karl Hermann , Ronald L. Imken
IPC分类号： H01R43/20 , H01R12/71 , H01R13/04 , H01R13/24 , H05K1/14 , H05K3/32 , H05K3/36
CPC分类号： H01R13/2435 , H01R12/714 , H05K3/368 , H05K1/145 , H05K2201/0311 , H05K2201/0397 , H05K2201/10424 , H05K2203/167 , H05K3/325 , H05K3/365 , H05K3/366
摘要： An interconnect strip is provided for effecting electrical interconnection between pluralities of conductor pads disposed on circuit boards or the like in a high density configuration. The strip is fabricated from a polymer film carrier having laminated thereon a metal foil with preselected spring properties. After lamination, lithographic techniques from a series of electrically isolated metallic beams on the carrier. Additional chemical processing removes portions of the carrier at opposing sides of the strip to expose opposing ends of the beams which extend beyond the carrier parallel to one another in opposing directions outwards from the carrier. By urging the pads towards respective beam ends of the strip disposed between the pads until mating engagement therewith, a plurality of electrical interconnections are established through the beams. Flexural properties of the strip provide a low insertion force connection for a high density of conductors wherein the spring action of the strip assures favorable contact forces to the pads. The exposed film side of the strip may also be metalized and provided with beams or interconnected to beams on opposing side of the film by vias thereby providing a ground plane.

2. 发明授权

US5313097A High density memory module 失效
标题翻译：高密度内存模块
公开(公告)号：US5313097A
公开(公告)日：1994-05-17
申请号：US976770
申请日：1992-11-16
申请人： Javad Haj-Ali-Ahmadi , Paul A. Farrar , Jerome A. Frankeny , Richard F. Frankeny , Karl Hermann , Jacqueline A. Shorter-Beauchamp , John A. Williamson
发明人： Javad Haj-Ali-Ahmadi , Paul A. Farrar , Jerome A. Frankeny , Richard F. Frankeny , Karl Hermann , Jacqueline A. Shorter-Beauchamp , John A. Williamson
IPC分类号： H01L25/00 , H01L25/065 , H01L25/07 , H01L25/18 , H05K3/32 , H01L23/02 , H02B1/00
CPC分类号： H01L25/0657 , H01L25/0652 , H05K3/325 , H01L2224/16 , H01L2224/16108 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06589 , H01L2225/06596
摘要： A memory module is built up from a power distribution assembly in the form of plates forming a capacitor of low inductance and a flexible circuit substrate. The circuit substrate is populated with precisely positioned contact pads for the power, read, write and address lines of memory chips that contact the substrate. Memory chips are fixed to heat spreaders and loaded into a chip holder which positions the chips for contact with the contact pads on the substrate. The substrate contact pads are plated to form dendritic crystals of palladium and the memory chips are provided with solder balls on the contact pads of the memory chip. The solder balls are held in contact with the contact pads by the compressive forces of clamping a heat sink over the heat spreaders for testing, and the assembly may be readily disassembled to replace any defective memory. The compression connection of the chips to the substrate may be relied on or the solder balls may be reflowed to establish permanent solder connections.
摘要翻译：存储器模块由形成低电感电容器的板的形式的配电组件和柔性电路基板构成。电路基板上装有用于接触基板的存储芯片的功率，读取，写入和地址线的精确定位的接触焊盘。存储芯片固定在散热器上，并装载到芯片保持器中，芯片保持器将芯片定位成与衬底上的接触焊盘接触。将衬底接触垫电镀以形成钯的树枝晶体，并且存储器芯片在存储器芯片的接触焊盘上设置有焊球。通过将散热器夹在散热器上用于测试的压缩力，焊球与接触垫保持接触，并且组装可以容易地拆卸以代替任何有缺陷的存储器。芯片与基板的压缩连接可以依赖于或者焊球可以被回流以建立永久的焊接连接。

3. 发明授权

US5290710A Method for testing integrated circuits on a carrier substrate 失效
标题翻译：在载体基板上测试集成电路的方法
公开(公告)号：US5290710A
公开(公告)日：1994-03-01
申请号：US887995
申请日：1992-05-22
申请人： Javad Haj-Ali-Ahmadi , Jerome A. Frankeny , Richard F. Frankeny , Adolph B. Habich , Karl Hermann , Ronald E. Hunt
发明人： Javad Haj-Ali-Ahmadi , Jerome A. Frankeny , Richard F. Frankeny , Adolph B. Habich , Karl Hermann , Ronald E. Hunt
IPC分类号： G01R31/28 , G01R31/30 , H01L21/00 , H01L21/60 , H01L21/66 , H05K13/08 , H01L21/52 , H01L21/58
CPC分类号： G01R31/2862 , G01R31/2863 , H01L21/67098 , H01L22/00 , H01L24/75 , H01L24/81 , H05K13/08 , G01R31/287 , G01R31/2877 , H01L2224/75 , H01L2224/81801 , H01L2924/01013 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/351
摘要： A method and apparatus is provided for testing integrated circuits and permanently affixing the ICs which are successfully tested to a product level carrier substrate. A modular test oven is used which allows the chips to be electrically and thermally tested with the chips non-permanently affixed to a carrier substrate. If all of the chips on the carrier substrate test good, then the temperature within the oven is elevated, thereby reflowing the solder balls and permanently affixing the chips to the carrier substrate.
摘要翻译：提供了一种用于测试集成电路并将成功测试的IC永久地固定到产品级载体衬底的方法和装置。使用模块化测试烘箱，其允许芯片通过非永久性地固定到载体衬底上的芯片进行电气和热学测试。如果载体基板上的所有芯片测试良好，则炉内的温度升高，从而回流焊球并将芯片永久地固定到载体基板上。

4. 发明授权

US5148003A Modular test oven 失效
标题翻译：模块化试验箱
公开(公告)号：US5148003A
公开(公告)日：1992-09-15
申请号：US619369
申请日：1990-11-28
申请人： Javad Haj-Ali-Ahmadi , Jerome A. Frankeny , Richard F. Frankeny , Adolph B. Habich , Karl Hermann , Ronald E. Hunt
发明人： Javad Haj-Ali-Ahmadi , Jerome A. Frankeny , Richard F. Frankeny , Adolph B. Habich , Karl Hermann , Ronald E. Hunt
IPC分类号： G01R31/28 , G01R31/30 , H01L21/00 , H01L21/60 , H01L21/66 , H05K13/08
CPC分类号： G01R31/2862 , G01R31/2863 , H01L21/67098 , H01L22/00 , H01L24/75 , H01L24/81 , H05K13/08 , G01R31/287 , G01R31/2877 , H01L2224/75 , H01L2224/81801 , H01L2924/01013 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/351
摘要： A method and apparatus is provided for testing integrated circuits and permanently affixing the ICs which are successfully tested to a product level carrier substrate. A modular test oven is used which allows the chips to be electrically and thermally tested with the chips non-permanently affixed to a carrier substrate. If all of the chips on the carrier substrate test good, then the temperature within the oven is elevated, thereby reflowing the solder balls and permanently affixing the chips to the carrier substrate. This card can then be used in the manufacture of an electronic device without the necessity of reworking the burned-in ICs. Further, if any of the chips fail the burn-in testing, the time and overhead required for reworking is minimized since the chips are not permanently attached.
摘要翻译：提供了一种用于测试集成电路并将成功测试的IC永久地固定到产品级载体衬底的方法和装置。使用模块化测试烘箱，其允许芯片通过非永久性地固定到载体衬底上的芯片进行电气和热学测试。如果载体基板上的所有芯片测试良好，则炉内的温度升高，从而回流焊球并将芯片永久地固定到载体基板上。然后，该卡可用于电子设备的制造，而不需要对烧毁的IC进行重新加工。此外，如果任何芯片失败老化测试，则重新加工所需的时间和开销最小化，因为芯片不是永久性连接的。

5. 发明授权

US4943242A Zero insertion force high density connector system 失效
标题翻译：零插入力高密度连接器系统
公开(公告)号：US4943242A
公开(公告)日：1990-07-24
申请号：US347694
申请日：1989-05-05
申请人： Richard F. Frankeny , Javad Haj-ali-Ahmadi , Ronald L. Imken , Rolf Wustrau
发明人： Richard F. Frankeny , Javad Haj-ali-Ahmadi , Ronald L. Imken , Rolf Wustrau
IPC分类号： H01R13/193 , H01R12/88 , H01R24/00 , H05K7/14
CPC分类号： H05K7/1404 , H01R12/88
摘要： A system for providing low insertion force electrical interconnections between high density contacts for use in interconnecting circuit packages. A housing has disposed therein one or more pre-buckled beam connectors. Each connector has a resilient insulative strip carrying a plurality of buckling beams electrically isolated from each other. The beams are aligned on the plane defining the strip in parallel with ends extending away from the strip edges in opposing directions. Means are provided for deforming the strip within the housing prior to effecting desired interconnections whereby the beams are pre-buckled. Upon urging contacts into proximity with the beam ends, the buckling force is released causing each beam's ends to be urged away from the strip into engagement with respective contacts, thereby effecting desired interconnection between contacts and through one or more beams.

6. 发明授权

US5065227A Integrated circuit packaging using flexible substrate 失效
标题翻译：集成电路使用柔性基板包装
公开(公告)号：US5065227A
公开(公告)日：1991-11-12
申请号：US533262
申请日：1990-06-04
申请人： Jerome A. Frankeny , Richard F. Frankeny , Karl Hermann , Ronald L. Imken
发明人： Jerome A. Frankeny , Richard F. Frankeny , Karl Hermann , Ronald L. Imken
IPC分类号： H01L21/60 , H01L21/66 , H01L23/14 , H01L23/373 , H01L23/498 , H05K1/00 , H05K3/42 , H05K3/44
CPC分类号： H05K3/429 , H01L23/142 , H01L23/3735 , H01L23/4985 , H05K3/445 , H01L2224/16 , H01L2224/16235 , H01L2924/01019 , H01L2924/01078 , H05K1/0393 , H05K2201/0154 , H05K2201/068 , H05K2201/09581 , H05K2201/09718 , H05K2201/09881 , H05K2203/0323 , H05K2203/1438 , Y10T29/41
摘要： A multilayer, flexible substrate upon which integrated circuit chips can be attached is disclosed. The input/output(I/O) connections from the chip do not radiate outward from the side of the die, but rather extend from a bottom surface. Since the I/O signal lines would not be accessible for testing once the IC chip is mounted on a substrate, each I/O line is extended outward from the IC footprint to an area on the substrate which is accessible. Additionally, an electrical path from each I/O signal port is simultaneously passed through the substrate layers upon which the chip is mounted, thus providing electrical contact of all I/O ports to the underside of the flexible substrate.An integrated circuit chip is mounted on this flexible substrate. Since each I/O line is accessible after mounting, the IC chip can be tested prior to mounting on its ultimate carrier. Once tested, the IC chip and the substrate upon which it is mounted are excised from the roll of substrate material. This excised, pretested memory package, which includes both the IC chip and the flexible substrate, can then be mounted directly onto the ultimate carrier either by reflow soldering or direct bonding.
摘要翻译：公开了可以连接集成电路芯片的多层柔性基板。来自芯片的输入/输出（I / O）连接不会从模具侧向外辐射，而是从底部表面延伸。由于一旦将IC芯片安装在基板上，I / O信号线将无法进行测试，因此每个I / O线从IC占位区向外延伸到可访问的基板上的区域。此外，来自每个I / O信号端口的电路同时通过其上安装有芯片的基板层，从而提供所有I / O端口与柔性基板的下侧的电接触。集成电路芯片安装在该柔性基板上。由于每个I / O线在安装后都可以访问，因此IC芯片可以在安装在其最终的载波上进行测试。一旦被测试，将IC芯片及其安装在其上的基板从基板材料卷上切下。包括IC芯片和柔性基板的切除的预测试存储器封装可以通过回流焊接或直接接合直接安装在极限载体上。

7. 发明授权

US5363275A Modular component computer system 失效
标题翻译：模块化组件计算机系统
公开(公告)号：US5363275A
公开(公告)日：1994-11-08
申请号：US15989
申请日：1993-02-10
申请人： Jerome A. Frankeny , Richard F. Frankeny , Karl Hermann , Ronald L. Imken
发明人： Jerome A. Frankeny , Richard F. Frankeny , Karl Hermann , Ronald L. Imken
IPC分类号： G06F1/18 , H01L23/538 , H05K1/11 , H05K1/18 , H05K3/00 , H05K3/36 , H05K1/00
CPC分类号： H05K1/189 , H01L23/5385 , H01L23/5387 , H01L2224/16225 , H01L2924/15311 , H05K1/118 , H05K2201/041 , H05K2201/053 , H05K2201/2009 , H05K3/0058 , H05K3/361 , H05K3/4691
摘要： Discrete computational elements are provided that will be connected to a base unit, and to one another or I/O devices, in order to configure a particular computer system. The base unit provides the electrical power required to energize the computational elements. A plurality of identically configured substrates are joined in a layered relation and are electrically connected with one another. These substrates are capable of being fabricated of different lengths such that they can extend outwardly from the computational element and may be connected to other computational elements. At least one integrated circuit will be placed on one side of the joined substrates and is electrically connected to each substrate layer. In this manner the ICs will be able to communicate with chips on other computational elements. A support member is also included that stiffens the plural substrate layers and independently distributes electrical power through voltage and ground potential planes, and interconnected substrate layers, to the chips. The support member will be disposed adjacent the substrate layers on a side opposite the ICs and independently attachable to the base unit by using electrical connection pins, a pluggable lip portion, or the like.
摘要翻译：提供将连接到基本单元和彼此或I / O设备的离散计算元件，以便配置特定的计算机系统。基本单元提供激励计算元件所需的电力。多个相同配置的基板以分层关系连接并且彼此电连接。这些基板能够被制造成不同的长度，使得它们可以从计算元件向外延伸并且可以连接到其它计算元件。至少一个集成电路将被放置在接合的衬底的一侧上，并且电连接到每个衬底层。以这种方式，IC将能够与其他计算元件上的芯片通信。还包括支撑构件，其硬化多个衬底层，并且通过电压和接地电位平面以及互连的衬底层独立地分配电力到芯片。支撑构件将被布置在与IC相对的一侧上的基底层附近，并且通过使用电连接销，可插入唇部等可独立地附接到基座单元。

8. 发明授权

US5053853A Modular electronic packaging system 失效
标题翻译：模块化电子包装系统
公开(公告)号：US5053853A
公开(公告)日：1991-10-01
申请号：US520439
申请日：1990-05-08
申请人： Javad Haj-Ali-Ahmadi , Richard F. Frankeny , Karl Hermann
发明人： Javad Haj-Ali-Ahmadi , Richard F. Frankeny , Karl Hermann
IPC分类号： H01L23/473 , H01L23/40 , H01L23/42 , H01L23/433 , H01L25/00 , H01L25/065 , H05K5/00
CPC分类号： H01L23/433 , H01L23/4006 , H01L23/42 , H01L25/0655 , H05K5/0091 , H01L2023/4043 , H01L2023/4062 , H01L2023/4068 , H01L2224/16 , H01L2224/73253
摘要： An electronic circuit packaging module includes a lower substrate, an upper cooling unit, and a frame disposed between the substrate and cooling unit. The substrate carries a plurality of integrated circuit chips with lead-outs to a plurality of downwardly protruding dimpled contact points disposed about the substrate periphery. The frame includes a plurality of insulative inserts about its periphery having conductive pins each with a lower extension extending below the insert and an upper contact point recessed within the insert. The cooling unit includes a plurality of fluid bags each in contact with a respective chip on the substrate for thermal management. A plurality of such modules are stacked in vertical registry with each downwardly protruding dimple of a module extending into a respective insert recess of an adjacent module. Electrical contact is thus effected between the respective dimples on the lower surface of the upper module and respective upper contact points of the recessed pins on the upper surface of the cover module. The lower extension of the pins of each insert of a given module thus extend into contact with the upper surface of a respective dimple of an adjacent lower module. In this manner, vertical electrical interconnection is established through the pins when mated in vertical registry, establishing a plurality of conductive paths in the Z axis.

9. 发明授权

US5509200A Method of making laminar stackable circuit board structure 失效
标题翻译：层叠电路板结构的制作方法
公开(公告)号：US5509200A
公开(公告)日：1996-04-23
申请号：US342506
申请日：1994-11-21
申请人： Jerome A. Frankeny , Richard F. Frankeny , Ronald L. Imken , Keith A. Vanderlee
发明人： Jerome A. Frankeny , Richard F. Frankeny , Ronald L. Imken , Keith A. Vanderlee
IPC分类号： H01L23/538 , H05K1/11 , H05K1/16 , H05K3/00 , H05K3/44 , H05K3/46 , H01K3/10
CPC分类号： H05K3/462 , H01L23/5385 , H05K1/112 , H05K1/162 , H05K3/445 , H05K3/4641 , H01L2224/16225 , H05K2201/0175 , H05K2201/0179 , H05K2201/0317 , H05K2201/0355 , H05K2201/0373 , H05K2201/09309 , H05K2201/09509 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/09718 , H05K2201/10378 , H05K2203/0307 , H05K3/0023 , H05K3/0094 , H05K3/4623 , Y10S428/901 , Y10T29/49165
摘要： Method and apparatus for fabricating fine pitch pattern multilayer printed circuit boards involving laminar stackable board layers providing power distribution, signal distribution and capacitive decoupling. In one respect, the invention relates to the fabrication of board layers by beginning with a metallic core, patterning the core, selectively enclosing the core in a dielectric, selectively depositing metal to form vias, plugs and signal lines, and forming dendrites with joining metallurgy on the vias and plugs to provide stackable connection from above or below the plane of the board layer. In another aspect, the invention is directed to the use of a sol-gel process to form a thin high dielectric constant crystalline film onto a metallic sheet followed with a deposition of a metallic layer onto the high dielectric constant film. The film serves as the dielectric of a capacitor layer which is thereafter in succession patterned, covered by a dielectric, and has selectively deposited a metallic layer for interconnecting the capacitor and forming vias. The ends of the vias are thereafter subject to dendritic growth and joining metallurgy to provide stackable interconnection capability.
摘要翻译：用于制造精细间距图案多层印刷电路板的方法和装置，其包括提供功率分配，信号分配和电容去耦的层叠堆叠板层。在一个方面，本发明涉及通过金属芯开始制造板层，图案化芯，选择性地将芯包围在电介质中，选择性地沉积金属以形成通孔，插塞和信号线，以及用连接冶金形成树突在通孔和插头上，以从板层的平面上方或下方提供可堆叠连接。在另一方面，本发明涉及使用溶胶 - 凝胶法在金属片上形成薄的高介电常数结晶膜，随后在高介电常数膜上沉积金属层。该膜用作电容器层的电介质，其后连续地被图案化，被电介质覆盖，并且已经选择性地沉积用于互连电容器和形成通孔的金属层。然后通孔的端部经历树枝状生长并连接冶金以提供可堆叠的互连能力。

10. 发明授权

US5161087A Pivotal heat sink assembly 失效
标题翻译：枢轴散热器组件
公开(公告)号：US5161087A
公开(公告)日：1992-11-03
申请号：US742566
申请日：1991-08-07
申请人： Jerome A. Frankeny , Richard F. Frankeny , Karl Hermann , Rolf Wustrau
发明人： Jerome A. Frankeny , Richard F. Frankeny , Karl Hermann , Rolf Wustrau
IPC分类号： H01L23/40 , H05K7/20
CPC分类号： H01L23/4093 , H01L2924/0002
摘要： This invention provides a heat sink assembly for cooling electrical and electronic circuits. A low cost assembly method is achieved by a pivotal assembly containing a heat sink which snaps into place adjacent to an electrical/electronic circuit which requires cooling. The snap-in heat sink assembly contains a resilient heat transfer material which is exposed to the devices requiring heat removal by windows or other openings in a plate which is disposed between the heat transfer material and the snap-in frame.
摘要翻译：本发明提供一种用于冷却电气和电子电路的散热器组件。通过包含散热器的枢转组件实现了低成本组装方法，所述散热器卡扣在需要冷却的电气/电子电路附近的位置。卡入式散热器组件包含弹性传热材料，其暴露于需要通过设置在传热材料和卡入式框架之间的板中的窗口或其它开口进行除热的装置。

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