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1. 发明授权

US5827765A Buried-strap formation in a dram trench capacitor 失效
标题翻译：埋地式电容器中的埋地带形成
公开(公告)号：US5827765A
公开(公告)日：1998-10-27
申请号：US605622
申请日：1996-02-22
申请人： Reinhard Stengl , Erwin Hammerl , Herbert L. Ho , Jack A. Mandelman , Radhika Srinivasan , Alvin P. Short
发明人： Reinhard Stengl , Erwin Hammerl , Herbert L. Ho , Jack A. Mandelman , Radhika Srinivasan , Alvin P. Short
IPC分类号： H01L27/00 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10861 , H01L27/10832
摘要： A method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell. The electrical connection is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.
摘要翻译：一种用于在DRAM单元中的沟槽存储电容器和存取晶体管之间进行电连接的方法。电连接是通过选择性地控制存在于沟槽中的N型或P型掺杂剂的扩散形成的，该单晶通过从沟槽侧壁外延（epi）生长的单晶半导体材料。该外延生长的单晶层作为在常规DRAM的处理中可能发生的过量掺杂剂扩散扩散的障碍。

2. 发明授权

US5844266A Buried strap formation in a DRAM trench capacitor 失效
标题翻译：在DRAM沟槽电容器中形成埋地带
公开(公告)号：US5844266A
公开(公告)日：1998-12-01
申请号：US879871
申请日：1997-06-20
申请人： Reinhard Stengl , Erwin Hammerl , Herbert L. Ho , Jack A. Mandelman , Radhika Srinivasan , Alvin P. Short
发明人： Reinhard Stengl , Erwin Hammerl , Herbert L. Ho , Jack A. Mandelman , Radhika Srinivasan , Alvin P. Short
IPC分类号： H01L27/00 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/10832
摘要： In a method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, the electrical connection is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.
摘要翻译：在用于在DRAM单元中的沟槽存储电容器和存取晶体管之间进行电连接的方法中，通过选择性地控制存在于沟槽中的N型或P型掺杂剂的扩散，通过单晶半导体材料，其通过从沟槽侧壁外延（epi）生长。该外延生长的单晶层作为在常规DRAM的处理中可能发生的过量掺杂剂扩散扩散的障碍。

3. 发明授权

US5792685A Three-dimensional device layout having a trench capacitor 失效
标题翻译：具有沟槽电容器的三维器件布局
公开(公告)号：US5792685A
公开(公告)日：1998-08-11
申请号：US667541
申请日：1996-06-21
申请人： Erwin Hammerl , Jack A. Mandelman , Bernhard Poschenrieder , Alvin P. Short , Radhika Srinivasan , Reinhard J. Stengl , Herbert L. Ho
发明人： Erwin Hammerl , Jack A. Mandelman , Bernhard Poschenrieder , Alvin P. Short , Radhika Srinivasan , Reinhard J. Stengl , Herbert L. Ho
IPC分类号： H01L27/00 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/10832
摘要： Method for forming three-dimensional device structures comprising a second device formed over a first device is disclosed. A layer having a single crystalline top surface is formed above the first device to provide the base for forming the active area of the second device.
摘要翻译：公开了一种用于形成包括形成在第一装置上的第二装置的三维装置结构的方法。在第一装置上方形成具有单一晶体顶表面的层，以提供用于形成第二装置的有效区域的基座。

4. 发明授权

US5893735A Three-dimensional device layout with sub-groundrule features 失效
标题翻译：具有子基础特征的三维设备布局
公开(公告)号：US5893735A
公开(公告)日：1999-04-13
申请号：US742533
申请日：1996-11-01
申请人： Reinhard J. Stengl , Erwin Hammerl , Jack A. Mandelman , Herbert L. Ho , Radhika Srinivasan , Alvin P. Short , Bernhard Poschenrieder
发明人： Reinhard J. Stengl , Erwin Hammerl , Jack A. Mandelman , Herbert L. Ho , Radhika Srinivasan , Alvin P. Short , Bernhard Poschenrieder
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/10832
摘要： Method for forming three-dimensional device structures comprising a second device having sub-groundrule features formed over a first device is disclosed. A layer having a single crystalline top surface is formed above the first device to provide the base for forming the active area of the second device. the sub-groundrule feature is formed using mandrel and spacers.
摘要翻译：公开了一种用于形成三维器件结构的方法，其包括在第一器件上形成的具有次基底特征的第二器件。在第一装置上方形成具有单一晶体顶表面的层，以提供用于形成第二装置的有效区域的基座。使用心轴和间隔件形成子底座特征。

5. 发明授权

US5656535A Storage node process for deep trench-based DRAM 失效
标题翻译：深沟槽DRAM的存储节点处理
公开(公告)号：US5656535A
公开(公告)日：1997-08-12
申请号：US610912
申请日：1996-03-04
申请人： Herbert Ho , Radhika Srinivasan , Scott D. Halle , Erwin Hammerl , David M. Dobuzinsky , Jack A. Mandelman , Mark Anthony Jaso
发明人： Herbert Ho , Radhika Srinivasan , Scott D. Halle , Erwin Hammerl , David M. Dobuzinsky , Jack A. Mandelman , Mark Anthony Jaso
IPC分类号： H01L27/04 , H01L21/02 , H01L21/762 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10861 , H01L21/76232 , H01L27/10832 , H01L28/82 , Y10S438/973
摘要： A simplified method of fabricating a storage node for a deep trench-based DRAM on a semiconductor substrate. The method involves the etching a trench in a surface of the substrate and then forming a layer of dielectric material on a sidewall of the trench the top portion of which is subsequently removed from the sidewall. Next, a layer of oxide is grown on the exposed portion of the sidewall. A portion of this layer of oxide is then removed from the sidewall in order to orient the layer of oxide a predetermined distance from the surface of the substrate. Finally, the trench is filled with a semiconductive material.
摘要翻译：一种在半导体衬底上制造用于深沟槽DRAM的存储节点的简化方法。该方法包括在衬底的表面中蚀刻沟槽，然后在沟槽的侧壁上形成介电材料层，其顶部部分随后从侧壁去除。接下来，在侧壁的暴露部分上生长一层氧化物。然后从侧壁去除该层氧化物的一部分，以便将氧化层定向到距衬底表面预定的距离。最后，沟槽填充有半导体材料。

6. 发明授权

US5923971A Reliable low resistance strap for trench storage DRAM cell using selective epitaxy 失效
标题翻译：使用选择性外延的沟槽存储DRAM单元的可靠的低电阻带
公开(公告)号：US5923971A
公开(公告)日：1999-07-13
申请号：US731940
申请日：1996-10-22
申请人： Herbert L. Ho , Andre R. LeBlanc , Jack A. Mandelman , Radhika Srinivasan
发明人： Herbert L. Ho , Andre R. LeBlanc , Jack A. Mandelman , Radhika Srinivasan
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
摘要： Strap resistance, surface strap shorts and wordline capacitance can be reduced by providing a selectively grown silicon strap which tapers away from spacer nitride and has less contact with spacer nitride. In addition the strap is optionally doped with an arsenic implant which reduces resistance.
摘要翻译：通过提供选择性地生长的硅带，可以减少带状电阻，表面带短路和字线电容，该带从间隔氮化物逐渐变细并且与间隔氮化物接触较少。此外，带可选地掺杂有降低电阻的砷注入。

7. 发明授权

US6153474A Method of controllably forming a LOCOS oxide layer over a portion of a vertically extending sidewall of a trench extending into a semiconductor substrate 失效
标题翻译：在延伸到半导体衬底的沟槽的垂直延伸的侧壁的一部分上可控地形成LOCOS氧化物层的方法
公开(公告)号：US6153474A
公开(公告)日：2000-11-28
申请号：US108619
申请日：1998-07-01
申请人： Herbert Lei Ho , Radhika Srinivasan , Scott D. Halle , Erwin Hammerl , David M. Dobuzinsky , Jack Allan Mandelman , Mark Anthony Jaso
发明人： Herbert Lei Ho , Radhika Srinivasan , Scott D. Halle , Erwin Hammerl , David M. Dobuzinsky , Jack Allan Mandelman , Mark Anthony Jaso
IPC分类号： H01L27/04 , H01L21/02 , H01L21/762 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L21/336
CPC分类号： H01L27/10861 , H01L21/76232 , H01L27/10832 , H01L28/82 , Y10S438/973
摘要： The present invention includes a method and system to increase the deep trench sidewall surface area in a storage node on a DRAM chip. By tilting the trenches the capacitance is increased without taking up more space on the semiconductor chip.
摘要翻译：本发明包括一种用于增加DRAM芯片上的存储节点中的深沟槽侧壁表面积的方法和系统。通过倾斜沟槽，电容增加，而不占用半导体芯片上的更多空间。

8. 发明授权

US6140208A Shallow trench isolation (STI) with bilayer of oxide-nitride for VLSI applications 有权
标题翻译：浅沟槽隔离（STI），双层氧化物氮化物用于VLSI应用
公开(公告)号：US6140208A
公开(公告)日：2000-10-31
申请号：US245958
申请日：1999-02-05
申请人： Farid Agahi , Gary Bronner , Bertrand Flietner , Erwin Hammerl , Herbert Ho , Radhika Srinivasan
发明人： Farid Agahi , Gary Bronner , Bertrand Flietner , Erwin Hammerl , Herbert Ho , Radhika Srinivasan
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76224
摘要： A reduction in parasitic leakages of shallow trench isolation vias is disclosed wherein the distance between the silicon nitride liner and the active silicon sidewalls is increased by depositing an insulating oxide layer prior to deposition of the silicon nitride liner. Preferably, the insulating oxide layer comprises tetraethylorthosilicate. The method comprises of etching one or more shallow trench isolations into a semiconductor wafer; depositing an insulating oxide layer into the trench; growing a thermal oxide in the trench; and depositing a silicon nitride liner in the trench. The thermal oxide may be grown prior to or after deposition of the insulating oxide layer.
摘要翻译：公开了浅沟槽隔离通孔的寄生泄漏的减少，其中通过在沉积氮化硅衬垫之前沉积绝缘氧化物层来增加氮化硅衬垫和有源硅侧壁之间的距离。优选地，绝缘氧化物层包括原硅酸四乙酯。该方法包括将一个或多个浅沟槽隔离件蚀刻成半导体晶片; 将绝缘氧化物层沉积到沟槽中; 在沟槽中生长热氧化物; 以及在沟槽中沉积氮化硅衬垫。热氧化物可以在沉积绝缘氧化物层之前或之后生长。

9. 发明授权

US06348394B1 Method and device for array threshold voltage control by trapped charge in trench isolation 失效
标题翻译：用于沟槽隔离中捕获电荷的阵列阈值电压控制的方法和装置
公开(公告)号：US06348394B1
公开(公告)日：2002-02-19
申请号：US09573375
申请日：2000-05-18
申请人： Jack A. Mandelman , Rama Divakaruni , Herbert Ho , Giuseppe La Rosa , Yujun Li , Jochen Beintner , Radhika Srinivasan
发明人： Jack A. Mandelman , Rama Divakaruni , Herbert Ho , Giuseppe La Rosa , Yujun Li , Jochen Beintner , Radhika Srinivasan
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L21/76224
摘要： A semiconductor device and method of manufacturing thereof are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. A nitride liner is formed in the trench. Charge is trapped in the nitride liner. In a preferred embodiment, the trench is filled with an oxide by an HDP process to increase the amount of charge trapped in the nitride liner. Preferably, the oxide fill is formed directly on the nitride liner.
摘要翻译：提供半导体器件及其制造方法。在半导体衬底中形成沟槽。优选在沟槽的表面上形成薄的氧化物衬垫。氮化物衬垫形成在沟槽中。电荷被困在氮化物衬垫中。在优选实施例中，沟槽通过HDP工艺填充氧化物以增加在氮化物衬垫中捕获的电荷量。优选地，氧化物填充物直接形成在氮化物衬垫上。

10. 发明授权

US06190955B1 Fabrication of trench capacitors using disposable hard mask 失效
标题翻译：使用一次性硬掩模制作沟槽电容器
公开(公告)号：US06190955B1
公开(公告)日：2001-02-20
申请号：US09014433
申请日：1998-01-27
申请人： Matthias Ilg , Richard L. Kleinhenz , Soichi Nadahara , Ronald W. Nunes , Klaus Penner , Klaus Roithner , Radhika Srinivasan , Shigeki Sugimoto
发明人： Matthias Ilg , Richard L. Kleinhenz , Soichi Nadahara , Ronald W. Nunes , Klaus Penner , Klaus Roithner , Radhika Srinivasan , Shigeki Sugimoto
IPC分类号： H01L218244
CPC分类号： H01L21/3081
摘要： Improved trench forming methods for semiconductor substrates using BSG avoid the problems associated with conventional TEOS hard mask techniques. The methods comprise: (a) providing a semiconductor substrate, (b) applying a conformal layer of borosilicate glass (BSG) on the substrate; (c) forming a patterned photoresist layer over the BSG layer whereby a portion of a layer underlying the photoresist layer is exposed, (d) anisotropically etching through the exposed portion of the underlying layer, through any other layers lying between the photoresist layer and the semiconductor substrate, and into the semiconductor substrate, thereby forming a trench in the semiconductor substrate. Preferably, one or more dielectric layers are present on the substrate surface prior to application of the BSG layer. One or more chemical barrier and/or organic antireflective coating layers may be applied over the BSG layer between the BSG layer and the photoresist layer. The methods are especially useful for forming deep trenches in silicon substrates with pad dielectric layers.
摘要翻译：使用BSG的半导体衬底的改进的沟槽形成方法避免了与常规TEOS硬掩模技术相关的问题。所述方法包括：（a）提供半导体衬底，（b）在衬底上施加保形层硼硅酸盐玻璃（BSG）;（c）在BSG层上形成图案化的光刻胶层，由此在光刻胶下面的一部分层（d）通过位于光致抗蚀剂层和半导体衬底之间的任何其它层，通过底层的暴露部分进行各向异性蚀刻，并进入半导体衬底，由此在半导体衬底中形成沟槽。优选地，一个或更多的介电层在施加BSG层之前存在于衬底表面上。可以在BSG层和光致抗蚀剂层之间的BSG层上施加一个或多个化学屏障和/或有机抗反射涂层。该方法对于在具有焊盘电介质层的硅衬底中形成深沟槽特别有用。

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