专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5893735A Three-dimensional device layout with sub-groundrule features 失效
标题翻译：具有子基础特征的三维设备布局
公开(公告)号：US5893735A
公开(公告)日：1999-04-13
申请号：US742533
申请日：1996-11-01
申请人： Reinhard J. Stengl , Erwin Hammerl , Jack A. Mandelman , Herbert L. Ho , Radhika Srinivasan , Alvin P. Short , Bernhard Poschenrieder
发明人： Reinhard J. Stengl , Erwin Hammerl , Jack A. Mandelman , Herbert L. Ho , Radhika Srinivasan , Alvin P. Short , Bernhard Poschenrieder
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/10832
摘要： Method for forming three-dimensional device structures comprising a second device having sub-groundrule features formed over a first device is disclosed. A layer having a single crystalline top surface is formed above the first device to provide the base for forming the active area of the second device. the sub-groundrule feature is formed using mandrel and spacers.
摘要翻译：公开了一种用于形成三维器件结构的方法，其包括在第一器件上形成的具有次基底特征的第二器件。在第一装置上方形成具有单一晶体顶表面的层，以提供用于形成第二装置的有效区域的基座。使用心轴和间隔件形成子底座特征。

2. 发明授权

US5792685A Three-dimensional device layout having a trench capacitor 失效
标题翻译：具有沟槽电容器的三维器件布局
公开(公告)号：US5792685A
公开(公告)日：1998-08-11
申请号：US667541
申请日：1996-06-21
申请人： Erwin Hammerl , Jack A. Mandelman , Bernhard Poschenrieder , Alvin P. Short , Radhika Srinivasan , Reinhard J. Stengl , Herbert L. Ho
发明人： Erwin Hammerl , Jack A. Mandelman , Bernhard Poschenrieder , Alvin P. Short , Radhika Srinivasan , Reinhard J. Stengl , Herbert L. Ho
IPC分类号： H01L27/00 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/10832
摘要： Method for forming three-dimensional device structures comprising a second device formed over a first device is disclosed. A layer having a single crystalline top surface is formed above the first device to provide the base for forming the active area of the second device.
摘要翻译：公开了一种用于形成包括形成在第一装置上的第二装置的三维装置结构的方法。在第一装置上方形成具有单一晶体顶表面的层，以提供用于形成第二装置的有效区域的基座。

3. 发明授权

US5827765A Buried-strap formation in a dram trench capacitor 失效
标题翻译：埋地式电容器中的埋地带形成
公开(公告)号：US5827765A
公开(公告)日：1998-10-27
申请号：US605622
申请日：1996-02-22
申请人： Reinhard Stengl , Erwin Hammerl , Herbert L. Ho , Jack A. Mandelman , Radhika Srinivasan , Alvin P. Short
发明人： Reinhard Stengl , Erwin Hammerl , Herbert L. Ho , Jack A. Mandelman , Radhika Srinivasan , Alvin P. Short
IPC分类号： H01L27/00 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10861 , H01L27/10832
摘要： A method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell. The electrical connection is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.
摘要翻译：一种用于在DRAM单元中的沟槽存储电容器和存取晶体管之间进行电连接的方法。电连接是通过选择性地控制存在于沟槽中的N型或P型掺杂剂的扩散形成的，该单晶通过从沟槽侧壁外延（epi）生长的单晶半导体材料。该外延生长的单晶层作为在常规DRAM的处理中可能发生的过量掺杂剂扩散扩散的障碍。

4. 发明授权

US5844266A Buried strap formation in a DRAM trench capacitor 失效
标题翻译：在DRAM沟槽电容器中形成埋地带
公开(公告)号：US5844266A
公开(公告)日：1998-12-01
申请号：US879871
申请日：1997-06-20
申请人： Reinhard Stengl , Erwin Hammerl , Herbert L. Ho , Jack A. Mandelman , Radhika Srinivasan , Alvin P. Short
发明人： Reinhard Stengl , Erwin Hammerl , Herbert L. Ho , Jack A. Mandelman , Radhika Srinivasan , Alvin P. Short
IPC分类号： H01L27/00 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/10832
摘要： In a method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, the electrical connection is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.
摘要翻译：在用于在DRAM单元中的沟槽存储电容器和存取晶体管之间进行电连接的方法中，通过选择性地控制存在于沟槽中的N型或P型掺杂剂的扩散，通过单晶半导体材料，其通过从沟槽侧壁外延（epi）生长。该外延生长的单晶层作为在常规DRAM的处理中可能发生的过量掺杂剂扩散扩散的障碍。

5. 发明授权

US5543348A Controlled recrystallization of buried strap in a semiconductor memory device 失效
标题翻译：半导体存储器件中埋置带的可控再结晶
公开(公告)号：US5543348A
公开(公告)日：1996-08-06
申请号：US412442
申请日：1995-03-29
申请人： Erwin Hammerl , Jack A. Mandelman , Herbert L. Ho , Junichi Shiozawa , Reinhard J. Stengl
发明人： Erwin Hammerl , Jack A. Mandelman , Herbert L. Ho , Junichi Shiozawa , Reinhard J. Stengl
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861
摘要： A method of forming a coupled capacitor and transistor is provided. A trench is formed in a semiconductor substrate and an impurity-doped first conductive region is then formed by filling the trench with an impurity-doped first conductive material. The impurity-doped first conductive region is etched back to a first level within the trench. An insulating layer is then formed on a sidewall of the portion of the trench opened by the etching back of the impurity-doped first conductive region and a second conductive region is formed by filling the remainder of the trench with a second conductive material. The insulating layer and the second conductive region are etched back to a second level within the trench and an amorphous silicon layer is formed in the portion of the trench opened by the etching back of the insulating layer and the second conductive region. The undoped amorphous silicon layer is etched back to a third a level within the trench. The undoped amorphous silicon layer is then recrystallized. Impurities are outdiffused from the impurity-doped first conductive region to the semiconductor substrate through the recrystallized silicon layer. A source/drain region of the transistor is formed adjacent to an intersection of the trench and the surface of the semiconductor substrate. The outdiffused impurities and the recrystallized silicon layer constitute a buried strap for electrically connecting the first and second conductive layers in the trench to the source/drain region.
摘要翻译：提供一种形成耦合电容器和晶体管的方法。在半导体衬底中形成沟槽，然后通过用杂质掺杂的第一导电材料填充沟槽来形成杂质掺杂的第一导电区域。杂质掺杂的第一导电区域被回蚀刻到沟槽内的第一水平。然后在通过杂质掺杂的第一导电区域的蚀刻开口的沟槽部分的侧壁上形成绝缘层，并且通过用第二导电材料填充沟槽的其余部分形成第二导电区域。将绝缘层和第二导电区域回蚀刻到沟槽内的第二层，并且在通过绝缘层和第二导电区域的蚀刻打开的沟槽部分中形成非晶硅层。未掺杂的非晶硅层在沟槽内回蚀刻到第三级。然后将未掺杂的非晶硅层重结晶。杂质通过再结晶硅层从杂质掺杂的第一导电区向外延伸到半导体衬底。晶体管的源极/漏极区域形成为与沟槽和半导体衬底的表面的交点相邻。超扩散杂质和再结晶硅层构成用于将沟槽中的第一和第二导电层电连接到源极/漏极区域的掩埋带。

6. 发明授权

US5656535A Storage node process for deep trench-based DRAM 失效
标题翻译：深沟槽DRAM的存储节点处理
公开(公告)号：US5656535A
公开(公告)日：1997-08-12
申请号：US610912
申请日：1996-03-04
申请人： Herbert Ho , Radhika Srinivasan , Scott D. Halle , Erwin Hammerl , David M. Dobuzinsky , Jack A. Mandelman , Mark Anthony Jaso
发明人： Herbert Ho , Radhika Srinivasan , Scott D. Halle , Erwin Hammerl , David M. Dobuzinsky , Jack A. Mandelman , Mark Anthony Jaso
IPC分类号： H01L27/04 , H01L21/02 , H01L21/762 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10861 , H01L21/76232 , H01L27/10832 , H01L28/82 , Y10S438/973
摘要： A simplified method of fabricating a storage node for a deep trench-based DRAM on a semiconductor substrate. The method involves the etching a trench in a surface of the substrate and then forming a layer of dielectric material on a sidewall of the trench the top portion of which is subsequently removed from the sidewall. Next, a layer of oxide is grown on the exposed portion of the sidewall. A portion of this layer of oxide is then removed from the sidewall in order to orient the layer of oxide a predetermined distance from the surface of the substrate. Finally, the trench is filled with a semiconductive material.
摘要翻译：一种在半导体衬底上制造用于深沟槽DRAM的存储节点的简化方法。该方法包括在衬底的表面中蚀刻沟槽，然后在沟槽的侧壁上形成介电材料层，其顶部部分随后从侧壁去除。接下来，在侧壁的暴露部分上生长一层氧化物。然后从侧壁去除该层氧化物的一部分，以便将氧化层定向到距衬底表面预定的距离。最后，沟槽填充有半导体材料。

7. 发明授权

US5670805A Controlled recrystallization of buried strap in a semiconductor memory device 失效
标题翻译：半导体存储器件中埋置带的可控再结晶
公开(公告)号：US5670805A
公开(公告)日：1997-09-23
申请号：US643983
申请日：1996-05-07
申请人： Erwin Hammerl , Jack A. Mandelman , Herbert L. Ho , Junichi Shiozawa , Reinhard Johannes Stengl
发明人： Erwin Hammerl , Jack A. Mandelman , Herbert L. Ho , Junichi Shiozawa , Reinhard Johannes Stengl
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94
CPC分类号： H01L27/10861
摘要： A semiconductor memory device includes a trench formed in a semiconductor substrate. Conductive material is formed in the trench and is insulatively spaced from the semiconductor substrate to form a capacitor. A transfer gate transistor includes source/drain regions formed on a surface of the semiconductor substrate and a control gate which is insulatively spaced from a channel region between the source and drain regions. A buried strap electrically connects the capacitor to one of the source/drain regions of the transfer gate transistor. A portion of the buried strap includes recrystallized silicon.
摘要翻译：半导体存储器件包括形成在半导体衬底中的沟槽。导电材料形成在沟槽中并且与半导体衬底绝缘地间隔开以形成电容器。传输栅极晶体管包括形成在半导体衬底的表面上的源极/漏极区域和与源极区域和漏极区域之间的沟道区域间隔开的控制栅极。掩埋带将电容器电连接到传输栅极晶体管的源极/漏极区域之一。掩埋带的一部分包括再结晶硅。

8. 发明授权

US5923971A Reliable low resistance strap for trench storage DRAM cell using selective epitaxy 失效
标题翻译：使用选择性外延的沟槽存储DRAM单元的可靠的低电阻带
公开(公告)号：US5923971A
公开(公告)日：1999-07-13
申请号：US731940
申请日：1996-10-22
申请人： Herbert L. Ho , Andre R. LeBlanc , Jack A. Mandelman , Radhika Srinivasan
发明人： Herbert L. Ho , Andre R. LeBlanc , Jack A. Mandelman , Radhika Srinivasan
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
摘要： Strap resistance, surface strap shorts and wordline capacitance can be reduced by providing a selectively grown silicon strap which tapers away from spacer nitride and has less contact with spacer nitride. In addition the strap is optionally doped with an arsenic implant which reduces resistance.
摘要翻译：通过提供选择性地生长的硅带，可以减少带状电阻，表面带短路和字线电容，该带从间隔氮化物逐渐变细并且与间隔氮化物接触较少。此外，带可选地掺杂有降低电阻的砷注入。

9. 发明授权

US06348394B1 Method and device for array threshold voltage control by trapped charge in trench isolation 失效
标题翻译：用于沟槽隔离中捕获电荷的阵列阈值电压控制的方法和装置
公开(公告)号：US06348394B1
公开(公告)日：2002-02-19
申请号：US09573375
申请日：2000-05-18
申请人： Jack A. Mandelman , Rama Divakaruni , Herbert Ho , Giuseppe La Rosa , Yujun Li , Jochen Beintner , Radhika Srinivasan
发明人： Jack A. Mandelman , Rama Divakaruni , Herbert Ho , Giuseppe La Rosa , Yujun Li , Jochen Beintner , Radhika Srinivasan
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L21/76224
摘要： A semiconductor device and method of manufacturing thereof are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. A nitride liner is formed in the trench. Charge is trapped in the nitride liner. In a preferred embodiment, the trench is filled with an oxide by an HDP process to increase the amount of charge trapped in the nitride liner. Preferably, the oxide fill is formed directly on the nitride liner.
摘要翻译：提供半导体器件及其制造方法。在半导体衬底中形成沟槽。优选在沟槽的表面上形成薄的氧化物衬垫。氮化物衬垫形成在沟槽中。电荷被困在氮化物衬垫中。在优选实施例中，沟槽通过HDP工艺填充氧化物以增加在氮化物衬垫中捕获的电荷量。优选地，氧化物填充物直接形成在氮化物衬垫上。

10. 发明授权

US08008713B2 Vertical SOI trench SONOS cell 有权
标题翻译：垂直SOI沟槽SONOS单元
公开(公告)号：US08008713B2
公开(公告)日：2011-08-30
申请号：US12410935
申请日：2009-03-25
申请人： David M. Dobuzinsky , Herbert L. Ho , Jack A. Mandelman , Yoichi Otani
发明人： David M. Dobuzinsky , Herbert L. Ho , Jack A. Mandelman , Yoichi Otani
IPC分类号： H01L29/00
CPC分类号： H01L29/792 , H01L21/26586 , H01L27/115 , H01L27/11568 , H01L29/7926
摘要： A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.
摘要翻译：提供一种半导体存储器件，其中在绝缘体上半导体（SOI）衬底中形成垂直沟槽半导体氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元，其允许将致密的非易失性随机存取基于SOI的互补金属氧化物半导体（CMOS）技术的存储器（NVRAM）单元。使用常规沟槽处理处理沟槽，并且在本发明方法的开始附近处理允许将存储单元的制造完全从SOI逻辑处理分离开来的处理。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式