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1. 发明授权

US5185736A Synchronous optical transmission system 失效
标题翻译：同步光传输系统
公开(公告)号：US5185736A
公开(公告)日：1993-02-09
申请号：US351861
申请日：1989-05-12
申请人： Raymond E. Tyrrell , O. Lamar Bishop , William E. Powell , Dale L. Krisher , William H. Stephenson , M. Rodney Briscoe , Hal A. Thorne , Claude M. Hurlocker , V. Paul Runyon , Timothy J. Williams , Joseph E. Sutherland , William B. Weeber , Michael J. Gingell , Kenneth J. Stoia , William J. Fox , Jeffrey P. Jones , Richard M. Czerwiec , Ertugrul Baydar , Heinrich T. Sonnenberg , Richard Peters , Gus C. Sanders , Richard J. Sanders, Jr. , Francis G. Noser , Joseph L. Smith , Jak Yaemsiri , Camille A. Abu-Saba , Patrick M. Farrell , Wenkwei Rou , Victor W. Wilkerson , Mohammad S. Arani , Stephen C. Dunning , Keith Bernhardt , Dana Merrill , Michael Sutton
发明人： Raymond E. Tyrrell , O. Lamar Bishop , William E. Powell , Dale L. Krisher , William H. Stephenson , M. Rodney Briscoe , Hal A. Thorne , Claude M. Hurlocker , V. Paul Runyon , Timothy J. Williams , Joseph E. Sutherland , William B. Weeber , Michael J. Gingell , Kenneth J. Stoia , William J. Fox , Jeffrey P. Jones , Richard M. Czerwiec , Ertugrul Baydar , Heinrich T. Sonnenberg , Richard Peters , Gus C. Sanders , Richard J. Sanders, Jr. , Francis G. Noser , Joseph L. Smith , Jak Yaemsiri , Camille A. Abu-Saba , Patrick M. Farrell , Wenkwei Rou , Victor W. Wilkerson , Mohammad S. Arani , Stephen C. Dunning , Keith Bernhardt , Dana Merrill , Michael Sutton
IPC分类号： H04J3/08 , H04J3/16 , H04Q11/04
CPC分类号： H04J3/1611 , H04J3/08 , H04J2203/0048 , H04J2203/006
摘要： A synchronous optical transmission system for interfacing SONET formatted channels to lower speed channels in either a SONET format or otherwise. The transmission system incorporates a fiber transmission system, terminal multiplexers and add/drop multiplexers that in turn incorporate a plurality of features, such as parallel scrambling circuitry, frame synchronization circuitry and the like.

2. 发明授权

US5033044A System for aligning transmission facility framing bits to the sonet H4 multiframe indicator byte 失效
标题翻译：将传输设备成帧位对准到sonet H4多帧指示符字节的系统
公开(公告)号：US5033044A
公开(公告)日：1991-07-16
申请号：US523596
申请日：1990-05-15
申请人： Timothy J. Williams , Ertugrul Baydar
发明人： Timothy J. Williams , Ertugrul Baydar
IPC分类号： H04J3/06
CPC分类号： H04J3/0623 , Y10S370/907
摘要： A system for aligning framing bits from independent digital transmission facilities with framing of a higher transmission rate facility includes a RAM memory. Received framing bits from the independent digital transmission facilities are stored at RAM locations in accordance with multiframe addresses of the framing bits relative to the multiframe format of the independent facility. Multiframe indicator bytes indicative of the framing of the higher transmission rate facility are used as addresses to read framing bits from RAM. The multiframe address of the independent digital transmission facilities is established by a counter for each independent facility, said counter being synchronized to the framing of the independent facility and incremented to provide addresses identical to the multiframe indicator bytes of the higher transmission rate facility.
摘要翻译：用于将来自独立数字传输设施的成帧位与更高传输速率设施的成帧对准的系统包括RAM存储器。来自独立数字传输设施的接收成帧比特根据独立设施的多帧格式，根据成帧比特的多帧地址存储在RAM位置。指示较高传输速率设施的帧的多帧指示符字节被用作从RAM中读取帧位的地址。独立数字传输设施的多帧地址由每个独立设施的计数器建立，所述计数器与独立设施的成帧同步并递增，以提供与较高传输速率设施的多帧指示符字节相同的地址。

3. 发明授权

US5134614A Sonet receive signaling translator 失效
标题翻译： SONET接收信号转换器
公开(公告)号：US5134614A
公开(公告)日：1992-07-28
申请号：US350591
申请日：1989-05-11
申请人： Ertugrul Baydar , Timothy J. Williams
发明人： Ertugrul Baydar , Timothy J. Williams
IPC分类号： H04J3/00 , H04J3/04 , H04J3/12 , H04J3/16 , H04Q11/04
CPC分类号： H04J3/1611 , H04J3/12 , H04J2203/0048
摘要： The four signaling bits contained in the eight-bit SONET signaling bytes are read from the SONET signaling row and are converted to four parallel signaling bits for storage in a RAM in quasi-SONET format, with sets of four A, four B, four C and four D bits for four consecutive channels being stored for an even and an odd tributary in one RAM memory row. Storing sets of four of the same bit for four consecutive channels simplifies the RAM write operation. A read-modify-write system is used for updating the RAM storage, wherein a row of RAM is read, modified by eight new signaling bits from two consecutive SONET signaling bytes, and is rewritten into the RAM. New signaling bits are stored to accumulate eight new signaling bits for two tributaries prior to updating the RAM with the new bits for both tributaries. The 32 signaling bits output during a RAM read operation are selectively multiplexed to output only four bits associated with a particular channel.
摘要翻译： 8位SONET信令字节中包含的四个信令位从SONET信令行读取，并被转换为四个并行信令位，用于以准SONET格式存储在RAM中，具有四个A，四个B，四个C 并且在一个RAM存储器行中为偶数和奇数支路存储四个连续通道的四个D位。存储四个连续通道的相同位的四个集合可简化RAM写操作。读取 - 修改 - 写入系统用于更新RAM存储器，其中RAM行的一行由两个连续的SONET信令字节的八个新的信令位进行修改，并被重写到RAM中。存储新的信令位以在两个支路的新位更新RAM之前为两个支路累积8个新的信令位。在RAM读操作期间输出的32个信令位被选择性地多路复用以仅输出与特定信道相关联的四个位。

4. 发明授权

US5214651A Sonet transmit signaling translator 失效
标题翻译： SONET发射信号转换器
公开(公告)号：US5214651A
公开(公告)日：1993-05-25
申请号：US350717
申请日：1989-05-11
申请人： Ertugrul Baydar , Timothy J. Williams
发明人： Ertugrul Baydar , Timothy J. Williams
IPC分类号： H04J3/00 , H04J3/04 , H04J3/06 , H04J3/12 , H04J3/16 , H04Q11/04
CPC分类号： H04J3/12 , H04J3/1611 , H04J2203/0048
摘要： In a SONET-access product, channel-associated signaling is rearranged into SONET-formatted signaling, with the signaling for added channels being multiplexed with the signaling for through channels, in accordance with a control signal received from a channel map RAM, which stores one bit of data for each channel to indicated whether it is a through channel or an add channel. The RAM is provisioned by a network control processor.

5. 发明授权

US5018132A SONET 4h byte receiver and filter 失效
标题翻译： SONET 4h字节接收器和滤波器
公开(公告)号：US5018132A
公开(公告)日：1991-05-21
申请号：US351538
申请日：1989-05-12
申请人： Timothy J. Williams , Ertugrul Baydar
发明人： Timothy J. Williams , Ertugrul Baydar
IPC分类号： H04J3/06 , H04J3/16 , H04Q11/04
CPC分类号： H04J3/0608 , H04J3/1611 , H04J2203/0089
摘要： A filtering algorithm for the SONET H4 byte is implemented with circuitry including an internal H4 counter which is incremented each frame and is locked to a received H4 byte once every 24 frames if a proper bit sequence is detected in a designated frame. If the designated bit sequence is not detected, the counter is not reset and continues to be incremented. If parity errors are detected, the counter is not reset and is allowed to free run to simulate the appropriate H4 byte input.
摘要翻译：用于SONET H4字节的滤波算法由包括内部H4计数器的电路来实现，该内部H4计数器在每帧被递增并且如果在指定的帧中检测到适当的比特序列，则每隔24帧被锁定到接收的H4字节一次。如果未检测到指定的位序列，则计数器不复位并继续递增。如果检测到奇偶校验错误，则计数器不复位，允许自由运行以模拟适当的H4字节输入。

6. 发明授权

US5001708A Sonet H4 byte generator 失效
标题翻译： Sonet H4字节发生器
公开(公告)号：US5001708A
公开(公告)日：1991-03-19
申请号：US351184
申请日：1989-05-12
申请人： Timothy J. Williams , Ertugrul Baydar
发明人： Timothy J. Williams , Ertugrul Baydar
IPC分类号： H04J3/12 , H04J3/16 , H04Q11/04
CPC分类号： H04J3/1611 , H04J3/12 , H04J2203/0089 , Y10S370/907
摘要： An H4 byte generating algorithm is implemented by circuitry which includes counters for generating the H4 byte. The circuit is provisioned to indicate whether it is operating in a terminal multiplexer mode or an add-drop multiplexer mode. In the terminal multiplexer mode the counters are allowed to free run and continually produce successive H4 byte outputs. In the add-drop multiplexer mode selected counter outputs are compared with the received H4 byte and the number of mismatches is accumulated by a mismatch counter. When the mismatch counter reaches a predetermined number the value of the received H4 byte is loaded into the H4 byte counters and the mismatch counter is reset. Each time a proper match between H4 counter outputs and the received H4 byte is sensed, the mismatch counter is reset to 0. The presence of a red alarm will also result in the resetting of the mismatch counter and free running of the H4 byte counters.
摘要翻译： H4字节生成算法由包括用于生成H4字节的计数器的电路实现。该电路被提供以指示其是在工作在终端多路复用器模式还是分插复用器模式。在终端复用器模式下，允许计数器自由运行，并持续产生连续的H4字节输出。在分插复用器模式中，选择的计数器输出与接收到的H4字节进行比较，并且不匹配的数量由不匹配计数器累积。当不匹配计数器达到预定数量时，接收的H4字节的值被加载到H4字节计数器中，并且不匹配计数器被复位。每次H4计数器输出和接收到的H4字节之间的匹配都被检测到时，不匹配计数器将复位为0.红色警报的存在还会导致不匹配计数器的复位和H4字节计数器的自由运行。

7. 发明申请

US20180145757A1 Latency Control In A Passive Optical Network 审中-公开
公开(公告)号：US20180145757A1
公开(公告)日：2018-05-24
申请号：US15817831
申请日：2017-11-20
申请人： William B. Weeber , Timothy J. Williams
发明人： William B. Weeber , Timothy J. Williams
IPC分类号： H04B10/27 , H04J14/02
摘要： A method and apparatus for latency control in an optical network. A management node such as an OLT in a PON sends a discovery message intending to prompt joining network nodes such as ONUs to send a response on a first wavelength during a quiet window established for this purpose. When a response is received, a secondary upstream-transmission wavelength is assigned to the ONU. When the ONU sends data upstream according to a schedule calculated by the ONT, which schedule may include transmission times using the assigned secondary wavelength. In this case, the assigned secondary wavelength will be scheduled using a relatively smaller or no quiet window. This scheduling may be determined in part by the service or services used by the ONU.

8. 发明授权

US08558578B1 Programmable input/output circuit 有权
标题翻译：可编程输入/输出电路
公开(公告)号：US08558578B1
公开(公告)日：2013-10-15
申请号：US13427264
申请日：2012-03-22
申请人： Timothy J. Williams , David G. Wright , Gregory J. Verge , Bruce E. Byrkett
发明人： Timothy J. Williams , David G. Wright , Gregory J. Verge , Bruce E. Byrkett
IPC分类号： H03K19/094
CPC分类号： H03K19/017581 , G06F5/065 , G06F12/0246 , G06F13/28 , G06F13/4072 , G06F2212/7201 , G11C7/1057 , G11C7/1084 , G11C16/102 , H03K19/01759
摘要： A programmable input/output circuit includes a programmable output circuit configured to drive an output signal to an input/output pad at a plurality of voltages, at least one of the plurality of voltages being supplied by an external circuit. The programmable input/output circuit further includes a programmable input configured to detect an input signal from the input/output pad at the plurality of voltages. The voltage levels of the input and output circuits may be independently and dynamically controllable.
摘要翻译：可编程输入/输出电路包括可编程输出电路，其被配置为以多个电压将输出信号驱动到输入/输出焊盘，所述多个电压中的至少一个由外部电路提供。可编程输入/输出电路还包括被配置为在多个电压下检测来自输入/输出焊盘的输入信号的可编程输入。输入和输出电路的电压电平可以是独立且可动态控制的。

9. 发明申请

US20100283647A1 PROGRAMMABLE DIGITAL-TO-ANALOG CONVERTER 有权
标题翻译：可编程数字到模拟转换器
公开(公告)号：US20100283647A1
公开(公告)日：2010-11-11
申请号：US12748085
申请日：2010-03-26
申请人： Timothy J. Williams , James H. Shutt , Warren Snyder , Dennis Seguine
发明人： Timothy J. Williams , James H. Shutt , Warren Snyder , Dennis Seguine
IPC分类号： H03M1/66 , H03M1/00
CPC分类号： H03M1/005 , H03M1/742
摘要： A multi-mode digital-to-analog converter (DAC) configured to operate in a plurality of modes.
摘要翻译：一种被配置为以多种模式操作的多模式数模转换器（DAC）。

10. 发明授权

US06745338B1 System for automatically selecting clock modes based on a state of clock input pin and generating a clock signal with an oscillator thereafter 有权
标题翻译：用于根据时钟输入引脚的状态自动选择时钟模式的系统，此后可以用振荡器产生时钟信号
公开(公告)号：US06745338B1
公开(公告)日：2004-06-01
申请号：US09659527
申请日：2000-09-12
申请人： Timothy J. Williams
发明人： Timothy J. Williams
IPC分类号： G06F108
CPC分类号： G06F1/04 , H03B5/36 , H03K5/04 , H03K5/08
摘要： An apparatus comprising a circuit configured to automatically select a clock mode in response to a state of a clock input.
摘要翻译：一种装置，包括被配置为响应于时钟输入的状态自动选择时钟模式的电路。

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