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1. 发明授权

US07079555B2 Integrated digital loop carrier system with virtual tributary mapper circuit 失效
公开(公告)号：US07079555B2
公开(公告)日：2006-07-18
申请号：US09985686
申请日：2001-11-05
申请人： Ertugrul Baydar , J. Bradley Boudreaux , Nicholas Carter , Chung Chen , Steven Klonsky , Michael Moran , Peter Renucci , Jeffrey Timbs , Thomas Tucker , Waleed Wardak
发明人： Ertugrul Baydar , J. Bradley Boudreaux , Nicholas Carter , Chung Chen , Steven Klonsky , Michael Moran , Peter Renucci , Jeffrey Timbs , Thomas Tucker , Waleed Wardak
IPC分类号： H04J3/04
CPC分类号： H04L41/0213 , H04J3/1611 , H04J2203/0028 , H04J2203/0041 , H04J2203/0046 , H04J2203/0048 , H04J2203/006 , H04L41/0226 , H04L41/046 , H04Q3/0095 , H04Q11/0407 , H04Q2213/13003 , H04Q2213/1301 , H04Q2213/13106 , H04Q2213/13176 , H04Q2213/13209 , H04Q2213/13292 , H04Q2213/1332 , H04Q2213/13367 , H04Q2213/13381
摘要： An integrated digital loop carrier (IDLC) system includes digital line feeders and signal processors to interface with the feeders an to ultimately provide data to subscriber instruments. The system can be employed as a central office terminal (COT) or remote digital terminal (RDT) with analog, T1 or SONET feeders and any conventional link medium. Data are put in DS1 format and multiplexed onto token ring optical loops for delivery to banks of channel units wherein the optical signals are translated to electrical signals for delivery to the Cus and subscribers. A method and apparatus is provided for mapping and demapping signals between virtual tributaries (VT) and digital signal formats in the RDT of an integrated digital loop carrier. An application-specific circuit provides such mapping and demapping functions as Floating Byte Synchronous VT to Locked Byte Synchronous VT, Floating Asynchronous VT to Locked Byte Synchronous VT, Floating Asynchronous VT to Floating Asynchronous VT, DS1 to Locked Byte Synchronous VT, DS1 to Floating Asynchronous VT, and DS1 to Floating Byte Synchronous VT.

2. 发明授权

US5185736A Synchronous optical transmission system 失效
标题翻译：同步光传输系统
公开(公告)号：US5185736A
公开(公告)日：1993-02-09
申请号：US351861
申请日：1989-05-12
申请人： Raymond E. Tyrrell , O. Lamar Bishop , William E. Powell , Dale L. Krisher , William H. Stephenson , M. Rodney Briscoe , Hal A. Thorne , Claude M. Hurlocker , V. Paul Runyon , Timothy J. Williams , Joseph E. Sutherland , William B. Weeber , Michael J. Gingell , Kenneth J. Stoia , William J. Fox , Jeffrey P. Jones , Richard M. Czerwiec , Ertugrul Baydar , Heinrich T. Sonnenberg , Richard Peters , Gus C. Sanders , Richard J. Sanders, Jr. , Francis G. Noser , Joseph L. Smith , Jak Yaemsiri , Camille A. Abu-Saba , Patrick M. Farrell , Wenkwei Rou , Victor W. Wilkerson , Mohammad S. Arani , Stephen C. Dunning , Keith Bernhardt , Dana Merrill , Michael Sutton
发明人： Raymond E. Tyrrell , O. Lamar Bishop , William E. Powell , Dale L. Krisher , William H. Stephenson , M. Rodney Briscoe , Hal A. Thorne , Claude M. Hurlocker , V. Paul Runyon , Timothy J. Williams , Joseph E. Sutherland , William B. Weeber , Michael J. Gingell , Kenneth J. Stoia , William J. Fox , Jeffrey P. Jones , Richard M. Czerwiec , Ertugrul Baydar , Heinrich T. Sonnenberg , Richard Peters , Gus C. Sanders , Richard J. Sanders, Jr. , Francis G. Noser , Joseph L. Smith , Jak Yaemsiri , Camille A. Abu-Saba , Patrick M. Farrell , Wenkwei Rou , Victor W. Wilkerson , Mohammad S. Arani , Stephen C. Dunning , Keith Bernhardt , Dana Merrill , Michael Sutton
IPC分类号： H04J3/08 , H04J3/16 , H04Q11/04
CPC分类号： H04J3/1611 , H04J3/08 , H04J2203/0048 , H04J2203/006
摘要： A synchronous optical transmission system for interfacing SONET formatted channels to lower speed channels in either a SONET format or otherwise. The transmission system incorporates a fiber transmission system, terminal multiplexers and add/drop multiplexers that in turn incorporate a plurality of features, such as parallel scrambling circuitry, frame synchronization circuitry and the like.

3. 发明授权

US5033044A System for aligning transmission facility framing bits to the sonet H4 multiframe indicator byte 失效
标题翻译：将传输设备成帧位对准到sonet H4多帧指示符字节的系统
公开(公告)号：US5033044A
公开(公告)日：1991-07-16
申请号：US523596
申请日：1990-05-15
申请人： Timothy J. Williams , Ertugrul Baydar
发明人： Timothy J. Williams , Ertugrul Baydar
IPC分类号： H04J3/06
CPC分类号： H04J3/0623 , Y10S370/907
摘要： A system for aligning framing bits from independent digital transmission facilities with framing of a higher transmission rate facility includes a RAM memory. Received framing bits from the independent digital transmission facilities are stored at RAM locations in accordance with multiframe addresses of the framing bits relative to the multiframe format of the independent facility. Multiframe indicator bytes indicative of the framing of the higher transmission rate facility are used as addresses to read framing bits from RAM. The multiframe address of the independent digital transmission facilities is established by a counter for each independent facility, said counter being synchronized to the framing of the independent facility and incremented to provide addresses identical to the multiframe indicator bytes of the higher transmission rate facility.
摘要翻译：用于将来自独立数字传输设施的成帧位与更高传输速率设施的成帧对准的系统包括RAM存储器。来自独立数字传输设施的接收成帧比特根据独立设施的多帧格式，根据成帧比特的多帧地址存储在RAM位置。指示较高传输速率设施的帧的多帧指示符字节被用作从RAM中读取帧位的地址。独立数字传输设施的多帧地址由每个独立设施的计数器建立，所述计数器与独立设施的成帧同步并递增，以提供与较高传输速率设施的多帧指示符字节相同的地址。

4. 发明授权

US6049550A Integrated digital loop carrier system with virtual tributary mapper circuit 失效
标题翻译：具有虚拟支路映射器电路的集成数字环路载波系统
公开(公告)号：US6049550A
公开(公告)日：2000-04-11
申请号：US28750
申请日：1998-02-24
申请人： Ertugrul Baydar , J. Bradley Boudreaux , Nicholas Carter , Chung Chen , Steven Klonsky , Michael Moran , Peter Renucci , Jeffrey Timbs , Thomas Tucker , Waleed Wardak
发明人： Ertugrul Baydar , J. Bradley Boudreaux , Nicholas Carter , Chung Chen , Steven Klonsky , Michael Moran , Peter Renucci , Jeffrey Timbs , Thomas Tucker , Waleed Wardak
IPC分类号： H04J3/16 , H04L12/24 , H04Q3/00 , H04Q11/04 , H04J3/02
CPC分类号： H04L41/0213 , H04J3/1611 , H04L41/0226 , H04L41/046 , H04Q11/0407 , H04Q3/0095 , H04J2203/0028 , H04J2203/0041 , H04J2203/0046 , H04J2203/0048 , H04J2203/006 , H04Q2213/13003 , H04Q2213/1301 , H04Q2213/13106 , H04Q2213/13176 , H04Q2213/13209 , H04Q2213/13292 , H04Q2213/1332 , H04Q2213/13367 , H04Q2213/13381
摘要： An integrated digital loop carrier (IDLC) system includes digital line feeders and signal processors to interface with the feeders and to ultimately provide data to subscriber instruments. The system can be employed as a central office terminal (COT) or remote digital terminal (RDT) with analog, T1 or SONET feeders and any conventional link medium. Data are put in DS1 format and multiplexed onto token ring optical loops for delivery to banks of channel units wherein the optical signals are translated to electrical signals for delivery to the CUs and subscribers. A method and apparatus is provided for mapping and demapping signals between virtual tributaries (VT) and digital signal formats in the RDT of an integrated digital loop carrier. An application-specific circuit provides such mapping and demapping functions as Floating Byte Synchronous VT to Locked Byte Synchronous VT, Floating Asynchronous VT to Locked Byte Synchronous VT, Floating Asynchronous VT to Floating Asynchronous VT, DS1 to Locked Byte Synchronous VT, DS1 to Floating Asynchronous VT, and DS1 to Floating Byte Synchronous VT.
摘要翻译：集成数字环路载波（IDLC）系统包括数字线路馈线和信号处理器，与馈线接口并最终向用户设备提供数据。该系统可以用作具有模拟，T1或SONET馈线和任何常规链路介质的中心局终端（COT）或远程数字终端（RDT）。数据采用DS1格式并复用到令牌环光环路上，用于传送到信道单元组，其中光信号被转换为电信号以传送到CU和用户。提供了一种用于在集成数字环路载波的RDT中的虚拟支路（VT）和数字信号格式之间映射和解映射信号的方法和装置。应用专用电路提供浮动字节同步VT到锁定字节同步VT，浮动异步VT到锁定字节同步VT，浮动异步VT到浮动异步VT，DS1到锁定字节同步VT，DS1到浮动异步的映射和解映射功能 VT和DS1到浮点字节同步VT。

5. 发明授权

US5134614A Sonet receive signaling translator 失效
标题翻译： SONET接收信号转换器
公开(公告)号：US5134614A
公开(公告)日：1992-07-28
申请号：US350591
申请日：1989-05-11
申请人： Ertugrul Baydar , Timothy J. Williams
发明人： Ertugrul Baydar , Timothy J. Williams
IPC分类号： H04J3/00 , H04J3/04 , H04J3/12 , H04J3/16 , H04Q11/04
CPC分类号： H04J3/1611 , H04J3/12 , H04J2203/0048
摘要： The four signaling bits contained in the eight-bit SONET signaling bytes are read from the SONET signaling row and are converted to four parallel signaling bits for storage in a RAM in quasi-SONET format, with sets of four A, four B, four C and four D bits for four consecutive channels being stored for an even and an odd tributary in one RAM memory row. Storing sets of four of the same bit for four consecutive channels simplifies the RAM write operation. A read-modify-write system is used for updating the RAM storage, wherein a row of RAM is read, modified by eight new signaling bits from two consecutive SONET signaling bytes, and is rewritten into the RAM. New signaling bits are stored to accumulate eight new signaling bits for two tributaries prior to updating the RAM with the new bits for both tributaries. The 32 signaling bits output during a RAM read operation are selectively multiplexed to output only four bits associated with a particular channel.
摘要翻译： 8位SONET信令字节中包含的四个信令位从SONET信令行读取，并被转换为四个并行信令位，用于以准SONET格式存储在RAM中，具有四个A，四个B，四个C 并且在一个RAM存储器行中为偶数和奇数支路存储四个连续通道的四个D位。存储四个连续通道的相同位的四个集合可简化RAM写操作。读取 - 修改 - 写入系统用于更新RAM存储器，其中RAM行的一行由两个连续的SONET信令字节的八个新的信令位进行修改，并被重写到RAM中。存储新的信令位以在两个支路的新位更新RAM之前为两个支路累积8个新的信令位。在RAM读操作期间输出的32个信令位被选择性地多路复用以仅输出与特定信道相关联的四个位。

6. 发明授权

US06333940B1 Integrated digital loop carrier system with virtual tributary mapper circuit 失效
标题翻译：具有虚拟支路映射器电路的集成数字环路载波系统
公开(公告)号：US06333940B1
公开(公告)日：2001-12-25
申请号：US09475507
申请日：1999-12-30
申请人： Ertugrul Baydar , J. Bradley Boudreaux , Nicholas Carter , Chung Chen , Steven Klonsky , Michael Moran , Peter Renucci , Jeffrey Timbs , Thomas Tucker , Waleed Wardak
发明人： Ertugrul Baydar , J. Bradley Boudreaux , Nicholas Carter , Chung Chen , Steven Klonsky , Michael Moran , Peter Renucci , Jeffrey Timbs , Thomas Tucker , Waleed Wardak
IPC分类号： H04J306
CPC分类号： H04L41/0213 , H04J3/1611 , H04J2203/0028 , H04J2203/0041 , H04J2203/0046 , H04J2203/0048 , H04J2203/006 , H04L41/0226 , H04L41/046 , H04Q3/0095 , H04Q11/0407 , H04Q2213/13003 , H04Q2213/1301 , H04Q2213/13106 , H04Q2213/13176 , H04Q2213/13209 , H04Q2213/13292 , H04Q2213/1332 , H04Q2213/13367 , H04Q2213/13381
摘要： An integrated digital loop carrier (IDLC) system includes digital line feeders and signal processors to interface with the feeders and to ultimately provide data to subscriber instruments. The system can be employed as a central office terminal (COT) or remote digital terminal (RDT) with analog, T1 or SONET feeders and any conventional link medium. Data are put in DS1 format and multiplexed onto token ring optical loops for delivery to banks of channel units wherein the optical signals are translated to electrical signals for delivery to the CUs and subscribers. A method and apparatus is provided for mapping and demapping signals between virtual tributaries (VT) and digital signal formats in the RDT of an integrated digital loop carrier. An application-specific circuit provides such mapping and demapping functions as Floating Byte Synchronous VT to Locked Byte Synchronous VT, Floating Asynchronous VT to Locked Byte Synchronous VT, Floating Asynchronous VT to Floating Asynchronous VT, DS1 to Locked Byte Synchronous VT, DS1 to Floating Asynchronous VT, and DS1 to Floating Byte Synchronous VT.
摘要翻译：集成数字环路载波（IDLC）系统包括数字线路馈线和信号处理器，与馈线接口并最终向用户设备提供数据。该系统可以用作具有模拟，T1或SONET馈线和任何常规链路介质的中心局终端（COT）或远程数字终端（RDT）。数据采用DS1格式并复用到令牌环光环路上，用于传送到信道单元组，其中光信号被转换为电信号以传送到CU和用户。提供了一种用于在集成数字环路载波的RDT中的虚拟支路（VT）和数字信号格式之间映射和解映射信号的方法和装置。应用专用电路提供浮动字节同步VT到锁定字节同步VT，浮动异步VT到锁定字节同步VT，浮动异步VT到浮动异步VT，DS1到锁定字节同步VT，DS1到浮动异步的映射和解映射功能 VT和DS1到浮点字节同步VT。

7. 发明授权

US06317439B1 Architecture for a SONET line unit including optical transceiver, cross-connect and synchronization subsystem 失效
标题翻译：包括光收发器，交叉连接和同步子系统的SONET线路单元架构
公开(公告)号：US06317439B1
公开(公告)日：2001-11-13
申请号：US09325153
申请日：1999-06-03
申请人： Gabriel E. Cardona , Charles M. Honaker, Jr. , Ertugrul Baydar
发明人： Gabriel E. Cardona , Charles M. Honaker, Jr. , Ertugrul Baydar
IPC分类号： H04J306
CPC分类号： H04L12/5601 , H04J3/0688 , H04J3/0691 , H04J3/0697 , H04J3/1617 , H04J2203/0025 , H04L49/1576 , H04L49/256 , H04L49/606 , H04L2012/5605 , H04L2012/5674 , H04L2012/5681
摘要： A SONET interface line unit which includes an interface to a SONET ring, an STM switch fabric, and STM synchronization function within a single module. The line unit includes an optical interface for communicating SONET traffic with a SONET ring, an ATM interface for communicating ATM traffic with an ATM switch fabric unit, and two or more service unit interfaces for communicating with service units having service interfaces to a service side of a network element. The service unit interfaces operate using the STM protocol. The line unit further includes forwarding logic for extracting ATM traffic and STM traffic from the composite traffic received from the SONET ring. The line unit further provides synchronization signals to other units within the network element, derived from a selected timing reference signal. An extended synchronization module is used to interface to a larger number of timing references within the device.
摘要翻译： SONET接口线路单元，其在单个模块内包括与SONET环的接口，STM交换结构和STM同步功能。线路单元包括用于与SONET环通信SONET业务的光接口，用于与ATM交换结构单元通信ATM业务的ATM接口，以及用于与具有业务接口的业务单元进行通信的两个或多个业务单元接口，网络元素。服务单元接口使用STM协议进行操作。线路单元还包括用于从从SONET环接收的复合业务中提取ATM业务和STM业务的转发逻辑。线路单元还从所选择的定时参考信号中提供同步信号给网络元件内的其他单元。扩展同步模块用于与设备内更多数量的定时参考进行接口。

8. 发明授权

US5809032A Time division multiplexed synchronous state machine having state memory 失效
标题翻译：具有状态存储器的时分复用同步状态机
公开(公告)号：US5809032A
公开(公告)日：1998-09-15
申请号：US783197
申请日：1997-01-15
申请人： William B. Weeber , Ertugrul Baydar , Sahabettin C. Demiray
发明人： William B. Weeber , Ertugrul Baydar , Sahabettin C. Demiray
IPC分类号： H04J3/06 , H04L7/04
CPC分类号： H04J3/0623
摘要： A receive SONET line interface includes an elastic store which receives and stores incoming signals from a pointer tracking circuit and retrieves stored signals for providing to a pointer generating circuit wherein, for both the pointer tracking and pointer generating circuits, separate state memories are provided for keeping track of the state of previous state pointer tracking and generating signals in time slots of repetitive frames of an incoming SONET signal.
摘要翻译：接收SONET线路接口包括弹性存储器，其接收并存储来自指针跟踪电路的输入信号，并检索存储的信号以提供给指针产生电路，其中，对于指针跟踪和指针产生电路两者，提供分离的状态存储器用于保持跟踪前一状态指针跟踪的状态，并在输入的SONET信号的重复帧的时隙中产生信号。

9. 发明授权

US5214651A Sonet transmit signaling translator 失效
标题翻译： SONET发射信号转换器
公开(公告)号：US5214651A
公开(公告)日：1993-05-25
申请号：US350717
申请日：1989-05-11
申请人： Ertugrul Baydar , Timothy J. Williams
发明人： Ertugrul Baydar , Timothy J. Williams
IPC分类号： H04J3/00 , H04J3/04 , H04J3/06 , H04J3/12 , H04J3/16 , H04Q11/04
CPC分类号： H04J3/12 , H04J3/1611 , H04J2203/0048
摘要： In a SONET-access product, channel-associated signaling is rearranged into SONET-formatted signaling, with the signaling for added channels being multiplexed with the signaling for through channels, in accordance with a control signal received from a channel map RAM, which stores one bit of data for each channel to indicated whether it is a through channel or an add channel. The RAM is provisioned by a network control processor.

10. 发明授权

US5784377A Integrated digital loop carrier system with virtual tributary mapper circuit 失效
标题翻译：具有虚拟支路映射器电路的集成数字环路载波系统
公开(公告)号：US5784377A
公开(公告)日：1998-07-21
申请号：US471224
申请日：1995-06-06
申请人： Ertugrul Baydar , J. Bradley Boudreaux , Nicholas Carter , Chung Chen , Steven Klonsky , Michael Moran , Peter Renucci , Jeffrey Timbs , Thomas Tucker , Waleed Wardak
发明人： Ertugrul Baydar , J. Bradley Boudreaux , Nicholas Carter , Chung Chen , Steven Klonsky , Michael Moran , Peter Renucci , Jeffrey Timbs , Thomas Tucker , Waleed Wardak
IPC分类号： H04J3/16 , H04L12/24 , H04Q3/00 , H04Q11/04 , H04J3/08
CPC分类号： H04L41/0213 , H04J3/1611 , H04L41/0226 , H04L41/046 , H04Q11/0407 , H04Q3/0095 , H04J2203/0028 , H04J2203/0041 , H04J2203/0046 , H04J2203/0048 , H04J2203/006 , H04Q2213/13003 , H04Q2213/1301 , H04Q2213/13106 , H04Q2213/13176 , H04Q2213/13209 , H04Q2213/13292 , H04Q2213/1332 , H04Q2213/13367 , H04Q2213/13381
摘要： An integrated digital loop carrier (IDLC) system includes digital line feeders and signal processors to interface with the feeders and to ultimately provide data to subscriber instruments. The system can be employed as a central office terminal (COT) or remote digital terminal (RDT) with analog, T1 or SONET feeders and any conventional link medium. Data are put in DS1 format and multiplexed onto optical loops for delivery to banks of channel units wherein the optical signals are translated to electrical signals for delivery to the channel units and subscribers. A method and apparatus is provided for mapping and demapping signals between virtual tributaries (VT) and digital signal formats in the RDT of an integrated digital loop carrier. An application-specific circuit provides such mapping and demapping functions as Floating Byte Synchronous VT to Locked Byte Synchronous VT, Floating Asynchronous VT to Locked Byte Synchronous VT, Floating Asynchronous VT to Floating Asynchronous VT, DS1 to Locked Byte Synchronous VT, DS1 to Floating Asynchronous VT, and DS1 to Floating Byte Synchronous VT.
摘要翻译：集成数字环路载波（IDLC）系统包括数字线路馈线和信号处理器，与馈线接口并最终向用户设备提供数据。该系统可以用作具有模拟，T1或SONET馈线和任何常规链路介质的中心局终端（COT）或远程数字终端（RDT）。数据采用DS1格式并被复用到光环路上，用于传输到信道单元组，其中光信号被转换为电信号以传送到信道单元和用户。提供了一种用于在集成数字环路载波的RDT中的虚拟支路（VT）和数字信号格式之间映射和解映射信号的方法和装置。应用专用电路提供浮动字节同步VT到锁定字节同步VT，浮动异步VT到锁定字节同步VT，浮动异步VT到浮动异步VT，DS1到锁定字节同步VT，DS1到浮动异步的映射和解映射功能 VT和DS1到浮点字节同步VT。

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