专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07797596B2 Method for monitoring and adjusting circuit performance 有权
标题翻译：监控和调整电路性能的方法
公开(公告)号：US07797596B2
公开(公告)日：2010-09-14
申请号：US11861403
申请日：2007-09-26
申请人： Anand Dixit , Raymond A. Heald , Steven R. Boyle
发明人： Anand Dixit , Raymond A. Heald , Steven R. Boyle
IPC分类号： G11C29/00
CPC分类号： G01R31/3187
摘要： A method for testing an integrated circuit implemented in an electronic system. The method includes placing an integrated circuit (or portion thereof) that is implemented in an operational system (e.g., in a computer system) in an offline status. An electrical parameter of the integrated system (e.g., a voltage, clock frequency, etc.) is set, and a built-in self-test (BIST) is conducted. Any failures that occur during the BIST are recorded. Testing is then repeated for each of a plurality of predetermined values of the electrical parameter, recording any failures that occur. Once testing is complete a failure rate/range is determined for each of the predetermined values.
摘要翻译：一种用于测试在电子系统中实现的集成电路的方法。该方法包括在离线状态下放置在操作系统（例如，计算机系统）中实现的集成电路（或其部分）。设置集成系统的电参数（例如，电压，时钟频率等），并且进行内置自检（BIST）。记录在BIST期间发生的任何故障。然后针对电参数的多个预定值中的每一个重复测试，记录发生的任何故障。一旦测试完成，则为每个预定值确定故障率/范围。

2. 发明授权

US06339542B2 Static random access memory (RAM) systems and storage cell for same 有权
标题翻译：静态随机存取存储器（RAM）系统和存储单元相同
公开(公告)号：US06339542B2
公开(公告)日：2002-01-15
申请号：US09876303
申请日：2001-06-06
申请人： Michael Anthony Ang , Raymond A. Heald , Roger Y. Lo
发明人： Michael Anthony Ang , Raymond A. Heald , Roger Y. Lo
IPC分类号： G11C1100
CPC分类号： G11C8/08 , G11C11/412 , G11C11/417
摘要： A method of continuously replenishing a four-transistor static RAM storage cell is described. Such method comprises biasing both the back gate terminals and the normal gate terminals of the two bit line coupling transistors in the static RAM storage cell to voltage levels for causing a flow of small compensating currents through such coupling transistors when they are in a standby or non-access condition. Such small compensating currents are supplied to the two storage transistors in the storage cell for replenishing leakage of charge from the parasitic capacitance in the storage cell. The bias voltages are supplied by adaptive bias circuits which adjust the bias voltages to track changes in the leakage of charge from the parasitic cell capacitance.
摘要翻译：描述了连续补充四晶体管静态RAM存储单元的方法。这种方法包括将静态RAM存储单元中的两个位线耦合晶体管的背栅极端子和正常栅极端子偏压到当它们处于备用或非等待状态时通过这种耦合晶体管流过小的补偿电流的电压电平 - 进入条件。这种小的补偿电流被提供给存储单元中的两个存储晶体管，用于从存储单元中的寄生电容补充电荷泄漏。偏置电压由自适应偏置电路提供，自适应偏置电路调整偏置电压以跟踪电荷从寄生电容器电容泄漏的变化。

3. 发明授权

US06301146B1 Static random access memory (RAM) systems and storage cell for same 有权
标题翻译：静态随机存取存储器（RAM）系统和存储单元相同
公开(公告)号：US06301146B1
公开(公告)日：2001-10-09
申请号：US09470788
申请日：1999-12-23
申请人： Michael Anthony Ang , Raymond A. Heald , Roger Y. Lo
发明人： Michael Anthony Ang , Raymond A. Heald , Roger Y. Lo
IPC分类号： G11C1100
CPC分类号： G11C8/08 , G11C11/412 , G11C11/417
摘要： A method of continuously replenishing a four-transistor static RAM storage cell is described. Such method comprises biasing both the back gate terminals and the normal gate terminals of the two bit line coupling transistors in the static RAM storage cell to voltage levels for causing a flow of small compensating currents through such coupling transistors when they are in a standby or non-access condition. Such small compensating currents are supplied to the two storage transistors in the storage cell for replenishing leakage of charge from the parasitic capacitance in the storage cell. The bias voltages arc supplied by adaptive bias circuits which adjust the bias voltages to track changes in the leakage of charge from the parasitic cell capacitance.
摘要翻译：描述了连续补充四晶体管静态RAM存储单元的方法。这种方法包括将静态RAM存储单元中的两个位线耦合晶体管的背栅极端子和正常栅极端子偏压到当它们处于备用或非等待状态时通过这种耦合晶体管流过小的补偿电流的电压电平 - 进入条件。这种小的补偿电流被提供给存储单元中的两个存储晶体管，用于从存储单元中的寄生电容补充电荷泄漏。偏置电压由自适应偏置电路提供，自适应偏置电路调整偏置电压以跟踪电荷从寄生电池电容泄漏的变化。

4. 发明申请

US20090083598A1 METHOD FOR MONITORING AND ADJUSTING CIRCUIT PERFORMANCE 有权
标题翻译：监测和调整电路性能的方法
公开(公告)号：US20090083598A1
公开(公告)日：2009-03-26
申请号：US11861403
申请日：2007-09-26
申请人： Anand Dixit , Raymond A. Heald , Steven R. Boyle
发明人： Anand Dixit , Raymond A. Heald , Steven R. Boyle
IPC分类号： G01R31/3187 , G06F11/27
CPC分类号： G01R31/3187
摘要： A method for testing an integrated circuit implemented in an electronic system. The method includes placing an integrated circuit (or portion thereof) that is implemented in an operational system (e.g., in a computer system) in an offline status. An electrical parameter of the integrated system (e.g., a voltage, clock frequency, etc.) is set, and a built-in self-test (BIST) is conducted. Any failures that occur during the BIST are recorded. Testing is then repeated for each of a plurality of predetermined values of the electrical parameter, recording any failures that occur. Once testing is complete a failure rate/range is determined for each of the predetermined values.
摘要翻译：一种用于测试在电子系统中实现的集成电路的方法。该方法包括在离线状态下放置在操作系统（例如，计算机系统）中实现的集成电路（或其部分）。设置集成系统的电参数（例如，电压，时钟频率等），并且进行内置自检（BIST）。记录在BIST期间发生的任何故障。然后针对电参数的多个预定值中的每一个重复测试，记录发生的任何故障。一旦测试完成，则为每个预定值确定故障率/范围。

5. 发明授权

US5825224A Edge-triggered dual-rail dynamic flip-flop with self-shut-off mechanism 失效
标题翻译：边缘触发双轨动态触发器，具有自我关闭机制
公开(公告)号：US5825224A
公开(公告)日：1998-10-20
申请号：US688057
申请日：1996-07-29
申请人： Edgardo F. Klass , David W. Poole , Chaim Amir , Raymond A. Heald
发明人： Edgardo F. Klass , David W. Poole , Chaim Amir , Raymond A. Heald
IPC分类号： H03K3/037 , H03K3/356 , H03K3/37
CPC分类号： H03K3/037 , H03K3/356139
摘要： A dynamic flip-flop includes a first input latch coupled to receive a data input signal and a second input latch coupled to receive the complement of the data put signal. The first and second input latches have first and second shutoff circuits, respectively. During a precharge phase, the first and second input latches each provide an output signal of a first logic level. During an evaluation phase, the first and second input latches sample the data input signal and complemented data input signal, respectively. In response to the samples of true and the complement of the data input signal, one input latch's output signal will transition to a second logic level, while the other input latch's output signal will remain at the first logic level. A first output latch and a second output latch are coupled to receive the output signals of the first and second input latches, respectively. The first and second output latches are inverting. During the precharge phase, the flip-flop provides output signals of the second logic level from both of the output latches. During the evaluation phase, one output latch will continue to provide an output signal of the second logic level and the other output latch will provide an output signal that transitions from the second logic level to the first logic level.
摘要翻译：动态触发器包括耦合以接收数据输入信号的第一输入锁存器和耦合以接收数据置放信号的补码的第二输入锁存器。第一和第二输入锁存器分别具有第一和第二截止电路。在预充电阶段期间，第一和第二输入锁存器都提供第一逻辑电平的输出信号。在评估阶段期间，第一和第二输入锁存器分别对数据输入信号和补码数据输入信号进行采样。响应于数据输入信号的真实和补码的样本，一个输入锁存器的输出信号将转换到第二逻辑电平，而另一个输入锁存器的输出信号将保持在第一逻辑电平。第一输出锁存器和第二输出锁存器分别耦合以接收第一和第二输入锁存器的输出信号。第一和第二输出锁存器正在反相。在预充电阶段期间，触发器从两个输出锁存器提供第二逻辑电平的输出信号。在评估阶段期间，一个输出锁存器将继续提供第二逻辑电平的输出信号，另一个输出锁存器将提供从第二逻辑电平转换到第一逻辑电平的输出信号。

6. 发明授权

US4821235A Translinear static memory cell with bipolar and MOS devices 失效
标题翻译：具有双极和MOS器件的线性静态存储单元
公开(公告)号：US4821235A
公开(公告)日：1989-04-11
申请号：US853297
申请日：1986-04-17
申请人： Raymond A. Heald
发明人： Raymond A. Heald
IPC分类号： G11C11/41 , G11C11/411 , G11C11/34 , G11C11/00 , H01L27/02
CPC分类号： G11C11/41 , G11C11/4113
摘要： A translinear static memory cell employs both bipolar and metal-oxide-semiconductor technologies. Bipolar transistors are employed as switching devices, whereas MOS transistors provide power supply and coupling functions. Among other advantages, the bipolar transistors provide large changes in output current for small changes in input voltage, thereby enabling high level read signals to be obtained. The MOS load and coupling transistors facilitate bidirectional current flow into and out of the cell, thereby enabling write operations to be achieved during relatively short periods of time.
摘要翻译：线性静态存储单元采用双极和金属氧化物半导体技术。双极晶体管用作开关器件，而MOS晶体管提供电源和耦合功能。除了其他优点之外，双极晶体管在输入电压的小变化中提供输出电流的大的变化，从而可以获得高电平的读取信号。 MOS负载和耦合晶体管便于双向电流流入和流出单元，从而使得能够在较短时间段内实现写入操作。

7. 发明授权

US06396149B1 Method for double-layer implementation of metal options in an integrated chip for efficient silicon debug 有权
标题翻译：用于双层实现集成芯片中金属选项的方法，用于高效硅调试
公开(公告)号：US06396149B1
公开(公告)日：2002-05-28
申请号：US09593284
申请日：2000-06-13
申请人： Xuejun Yuan , Xiaowei Jin , Rambabu Pyapali , Raymond A. Heald , James M. Kaku , Helen Dunn , Thelma C. Taylor , Peter F. Lai , Aharon Ostrer
发明人： Xuejun Yuan , Xiaowei Jin , Rambabu Pyapali , Raymond A. Heald , James M. Kaku , Helen Dunn , Thelma C. Taylor , Peter F. Lai , Aharon Ostrer
IPC分类号： H01L2710
CPC分类号： H01L22/22 , H01L23/525 , H01L2924/0002 , H01L2924/00
摘要： In one aspect of the present invention, a method provides a connecting path diversion through an upper layer of an integrated circuit by alteration of a connecting path through a lower layer of the integrated circuit. This method enables a circuit path in an integrated circuit to be modified in an accessible layer for testing before the modified circuit path is incorporated in a redesigned integrated circuit design. In another aspect of the present invention, a modified multi-layer integrated circuit chip includes a connecting path formed in a lower layer and a substitute connecting path that is etched in the lower layer. Subsequently, the connecting path formed in the lower layer may be severed.
摘要翻译：在本发明的一个方面中，一种方法是通过改变通过集成电路的下层的连接路径来提供通过集成电路的上层的连接路径。该方法使得在经修改的电路路径被并入重新设计的集成电路设计之后，集成电路中的电路路径能够在可访问层中进行修改以进行测试。在本发明的另一方面，一种修改的多层集成电路芯片包括形成在下层中的连接路径和在下层中蚀刻的替代连接路径。随后，形成在下层中的连接路径可能被切断。

8. 发明授权

US6098150A Method and apparatus for fetching information from a cache memory 失效
标题翻译：从高速缓冲存储器取出信息的方法和装置
公开(公告)号：US6098150A
公开(公告)日：2000-08-01
申请号：US559972
申请日：1995-11-17
申请人： Vernon Brethour , Raymond A. Heald
发明人： Vernon Brethour , Raymond A. Heald
IPC分类号： G06F9/38 , G06F12/08 , G06F12/00
CPC分类号： G06F12/0886
摘要： The present invention relates to a method and apparatus for efficiently outputting words from an N-way set-associative cache. In one embodiment, the cache tags contain information indicating which set contains a line holding data succeeding the last word in the line accessed during a cache read. For a cache which outputs M words for each access, when the addressed word is within M-1 words of the end of the line, the cache will output all the words from the accessed word to the end of the line and the remainder of the M words from a succeeding line in whatever set is indicated by the pointer.
摘要翻译：本发明涉及一种用于从N路组合关联高速缓存中有效地输出单词的方法和装置。在一个实施例中，高速缓存标签包含指示哪个集合包含保存在高速缓存读取期间被访问的行中的最后一个字的数据的行的信息。对于为每个访问输出M个字的高速缓存，当寻址字在行尾的M-1个字之内时，高速缓存将从访问的字输出所有字到行尾，剩余的来自任何集合中的后续行的M个单词由指针指示。

9. 发明授权

US4112511A Four transistor static bipolar memory cell using merged transistors 失效
标题翻译：使用合并晶体管的四晶体管静态双极存储单元
公开(公告)号：US4112511A
公开(公告)日：1978-09-05
申请号：US832940
申请日：1977-09-13
申请人： Raymond A. Heald
发明人： Raymond A. Heald
IPC分类号： G11C11/41 , G11C11/405 , G11C11/411 , G11C11/416 , H01L21/8229 , H01L21/8242 , H01L27/102 , H01L27/108 , G11C11/40 , G11C13/00
CPC分类号： G11C11/4113 , G11C11/416 , H01L27/1025
摘要： A bipolar memory cell of reduced size requires only four I.sup.2 L operated transistors and three access lines. Two current injection transistors supply operating current to two inversely operated flip-flop transistors and also function as load devices as well as coupling devices. The three access lines conduct power to the cells as well as the signals for the write and read operations. A write operation is performed by ratioing the currents supplied to a memory cell array such that only a selected cell is written.
摘要翻译：减小尺寸的双极性存储单元仅需要四个I2L操作晶体管和三条存取线。两个电流注入晶体管为两个反向操作的触发器晶体管提供工作电流，并且还用作负载器件以及耦合器件。三个接入线路对单元进行电源以及用于写入和读取操作的信号。通过将提供给存储单元阵列的电流比较，使得仅写入所选择的单元来执行写入操作。

10. 发明授权

US07215175B1 Fuse sensing scheme with auto current reduction 有权
标题翻译：具有自动电流降低的保险丝感测方案
公开(公告)号：US07215175B1
公开(公告)日：2007-05-08
申请号：US10932162
申请日：2004-09-01
申请人： Gurupada Mandal , Suresh Seshadri , David Hugh McIntyre , Raymond A. Heald , William Y. Mo
发明人： Gurupada Mandal , Suresh Seshadri , David Hugh McIntyre , Raymond A. Heald , William Y. Mo
IPC分类号： H01H37/76 , H01H85/00
CPC分类号： G11C17/18
摘要： An improved circuit for sensing and programming fuses in integrated circuits. The circuit is broadly comprised of a fuse cell, a reference circuit, a sense amplifier and a level detector. In one embodiment of the present invention, a two-stage sensing scheme is implemented. The improved fuse sensing circuit uses current-mode sensing and implements an auto-read current reduction scheme. Using a level-detect circuit, the virtual ground is raised automatically if the high-voltage power supply exceeds core supply (Vdd) by a fixed dc voltage. This reduces effective sensing voltage and the read current and thus helps preserve unblown fuse integrity. In one embodiment of the invention, four modes of operation are implemented: “Normal Read,” “Unblown_Read,” “Blown_Read_1” and “Blown_Read_2.” The default read mode is the “normal read” while the “Unblown” and “Blown” read modes are for fuse calibration purposes. In the “Unblown_Read” read mode, the circuit is operable to compare the fuse resistance against a lower reference resistance, closer to an unblown fuse resistance value, in order to make the comparison more stringent. Similarly, the “Blown_Read_1” and “Blown_Read_2” modes allow a more stringent comparison for a blown fuse resistance.
摘要翻译：一种用于在集成电路中感测和编程保险丝的改进电路。该电路广泛地包括熔丝单元，参考电路，读出放大器和电平检测器。在本发明的一个实施例中，实现了两级感测方案。改进的熔丝感测电路使用电流模式感测并实现自动读取电流降低方案。使用电平检测电路，如果高压电源以固定的直流电压超过磁芯电源（Vdd），则虚拟接地将自动升高。这降低了有效的感测电压和读取电流，从而有助于保持未熔断的保险丝完整性。在本发明的一个实施例中，实现了四种操作模式：“Normal Read”，“Unblown_Read”，“Blown_Read_1”和“Blown_Read_2”。 “Unblown”和“Blown”读取模式的默认读取模式是“正常读取”，用于保险丝校准。在“Unblown_Read”读取模式下，该电路可操作以将熔丝电阻与较低的参考电阻进行比较，更接近未熔断的保险丝电阻值，以使比较更加严格。类似地，“Blown_Read_1”和“Blown_Read_2”模式允许对熔断熔断器电阻进行更严格的比较。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式