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1. 发明授权

US5825224A Edge-triggered dual-rail dynamic flip-flop with self-shut-off mechanism 失效
标题翻译：边缘触发双轨动态触发器，具有自我关闭机制
公开(公告)号：US5825224A
公开(公告)日：1998-10-20
申请号：US688057
申请日：1996-07-29
申请人： Edgardo F. Klass , David W. Poole , Chaim Amir , Raymond A. Heald
发明人： Edgardo F. Klass , David W. Poole , Chaim Amir , Raymond A. Heald
IPC分类号： H03K3/037 , H03K3/356 , H03K3/37
CPC分类号： H03K3/037 , H03K3/356139
摘要： A dynamic flip-flop includes a first input latch coupled to receive a data input signal and a second input latch coupled to receive the complement of the data put signal. The first and second input latches have first and second shutoff circuits, respectively. During a precharge phase, the first and second input latches each provide an output signal of a first logic level. During an evaluation phase, the first and second input latches sample the data input signal and complemented data input signal, respectively. In response to the samples of true and the complement of the data input signal, one input latch's output signal will transition to a second logic level, while the other input latch's output signal will remain at the first logic level. A first output latch and a second output latch are coupled to receive the output signals of the first and second input latches, respectively. The first and second output latches are inverting. During the precharge phase, the flip-flop provides output signals of the second logic level from both of the output latches. During the evaluation phase, one output latch will continue to provide an output signal of the second logic level and the other output latch will provide an output signal that transitions from the second logic level to the first logic level.
摘要翻译：动态触发器包括耦合以接收数据输入信号的第一输入锁存器和耦合以接收数据置放信号的补码的第二输入锁存器。第一和第二输入锁存器分别具有第一和第二截止电路。在预充电阶段期间，第一和第二输入锁存器都提供第一逻辑电平的输出信号。在评估阶段期间，第一和第二输入锁存器分别对数据输入信号和补码数据输入信号进行采样。响应于数据输入信号的真实和补码的样本，一个输入锁存器的输出信号将转换到第二逻辑电平，而另一个输入锁存器的输出信号将保持在第一逻辑电平。第一输出锁存器和第二输出锁存器分别耦合以接收第一和第二输入锁存器的输出信号。第一和第二输出锁存器正在反相。在预充电阶段期间，触发器从两个输出锁存器提供第二逻辑电平的输出信号。在评估阶段期间，一个输出锁存器将继续提供第二逻辑电平的输出信号，另一个输出锁存器将提供从第二逻辑电平转换到第一逻辑电平的输出信号。

2. 发明授权

US5889417A Apparatus and method for improving the noise immunity of a dynamic logic signal repeater 失效
标题翻译：用于提高动态逻辑信号中继器的抗噪声能力的装置和方法
公开(公告)号：US5889417A
公开(公告)日：1999-03-30
申请号：US653381
申请日：1996-05-24
申请人： Edgardo F. Klass , Chaim Amir , David W. Poole , Alan C. Rogers
发明人： Edgardo F. Klass , Chaim Amir , David W. Poole , Alan C. Rogers
IPC分类号： H03K19/003 , H03K19/096 , H03K17/16
CPC分类号： H03K19/00361
摘要： A dynamic logic signal repeater includes a complementary dynamic logic circuit with an input node to receive an input signal and an output node storing a precharge signal. The complementary dynamic logic circuit configuration, transistor sizing, and the use of a precharge driver results in a signal transition trip point for the precharge signal on the output node that is substantially equivalent to the signal transition trip point of a static logic circuit. Thus, the dynamic logic signal repeater has improved noise immunity. An evaluation locking transistor is connected to the complementary dynamic logic circuit and the output node. The evaluation locking transistor prevents the charging of the output node during a dynamic logic evaluation period.
摘要翻译：动态逻辑信号中继器包括具有用于接收输入信号的输入节点和存储预充电信号的输出节点的互补动态逻辑电路。补充动态逻辑电路配置，晶体管尺寸以及预充电驱动器的使用导致输出节点上的预充电信号的信号转换跳变点，其基本上等于静态逻辑电路的信号转换跳变点。因此，动态逻辑信号中继器具有改善的抗噪声能力。评估锁定晶体管连接到互补动态逻辑电路和输出节点。评估锁定晶体管在动态逻辑评估期间防止输出节点的充电。

3. 发明授权

US06222404B1 Edge-triggered dual-rail dynamic flip-flop with an enhanced self-shut-off mechanism 有权
标题翻译：边缘触发双轨动态触发器，具有增强的自我关闭机制
公开(公告)号：US06222404B1
公开(公告)日：2001-04-24
申请号：US09340745
申请日：1999-06-28
申请人： Anup S. Mehta , Chaim Amir , Edgardo F. Klass , Ashutosh K. Das
发明人： Anup S. Mehta , Chaim Amir , Edgardo F. Klass , Ashutosh K. Das
IPC分类号： H03K3037
CPC分类号： H03K3/0375
摘要： A shut-off circuit included in a dynamic flip-flop isolates output terminals of the dynamic flip-flop from circuitry within the flip-flop that could introduce noise on either output terminal during a portion of the evaluation phase. Since the output terminals are isolated from the input terminals during this portion of the evaluation phase, spurious input signals have no affect on the output signal levels. Similarly, charge within the dynamic flip-flop that is not completely dissipated in the transition from a precharge phase to the evaluation phase has no affect on the output signal levels during this portion of the evaluation phase.
摘要翻译：包括在动态触发器中的截止电路将触发器内的电路与电路中的电路隔离，以便在评估阶段的一部分期间在任一输出端子上引入噪声。由于在评估阶段的这一部分期间输出端子与输入端子隔离，寄生输入信号对输出信号电平没有影响。类似地，动态触发器中在从预充电阶段到评估阶段的转变中未完全消耗的电荷在评估阶段的该部分期间对输出信号电平没有影响。

4. 发明授权

US5920218A Single-phase edge-triggered dual-rail dynamic flip-flop 失效
标题翻译：单相边沿触发双轨动态触发器
公开(公告)号：US5920218A
公开(公告)日：1999-07-06
申请号：US710692
申请日：1996-09-19
申请人： Edgardo F. Klass , Chaim Amir
发明人： Edgardo F. Klass , Chaim Amir
IPC分类号： H03K3/356 , H03K3/37
CPC分类号： H03K3/356121
摘要： A single phase edge-triggered dual-rail dynamic flip-flop circuit for use with dynamic logic gates includes an input stage, precharge stage and buffer. The input stage is coupled to receive a data-input signal and a clock signal. During the precharge phase, the input stage provides an output signal that is the complement of the data input signal. When the data input signal is provided by a dynamic logic gate, the input stage output signal is precharged to a logic high level. During the evaluation phase, the input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low. The precharge stage receives the output signal from the input stage and the clock signal. During the precharge phase, the precharge stage generates a logic high level output signal independently of the signal received from the input stage. However, the logic high level signal from the input stage turns on hard a n-channel transistor in the precharge stage, which minimizes the delay through the precharge stage during the evaluation phase. During the evaluation phase, the precharge stage outputs the complement of the output signal received from the input stage. The buffer is coupled to receive the output signal from the precharge stage. During both the precharge and evaluation phases, the buffer outputs the complement of the output signal received from the precharge stage.
摘要翻译：用于动态逻辑门的单相边沿触发双轨动态触发器电路包括输入级，预充电级和缓冲器。输入级被耦合以接收数据输入信号和时钟信号。在预充电阶段期间，输入级提供作为数据输入信号的补码的输出信号。当数据输入信号由动态逻辑门提供时，输入级输出信号被预充电到逻辑高电平。在评估阶段期间，输入级产生一个输出信号，保持在逻辑高电平或从高到低转换。预充电阶段接收来自输入级的输出信号和时钟信号。在预充电阶段期间，预充电阶段独立于从输入级接收的信号产生逻辑高电平输出信号。然而，来自输入级的逻辑高电平信号在预充电阶段打开硬通道n沟道晶体管，这在评估阶段期间通过预充电阶段的延迟最小化。在评估阶段，预充电阶段输出从输入级接收的输出信号的补码。缓冲器被耦合以从预充电阶段接收输出信号。在预充电和评估阶段期间，缓冲器输出从预充电阶段接收的输出信号的补码。

5. 发明授权

US06536022B1 Two pole coupling noise analysis model for submicron integrated circuit design verification 有权
标题翻译：用于亚微米集成电路设计验证的双极耦合噪声分析模型
公开(公告)号：US06536022B1
公开(公告)日：2003-03-18
申请号：US09513545
申请日：2000-02-25
申请人： Kathirgamar Aingaran , Edgardo F. Klass , Chaim Amir , Chin-Man Kim
发明人： Kathirgamar Aingaran , Edgardo F. Klass , Chaim Amir , Chin-Man Kim
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： An automated method of analyzing crosstalk in a digital logic integrated circuit, the method operating on a digital computer, is described. The method uses available software to make an extracted, parameterized netlist from a layout of the integrated circuit. For at least one potential victim wire of the plurality of wires, determining a subset of the wires of the chip are found to be potential aggressor wires that may couple to the victim wire. The aggressor wires are combined into a common aggressor. A risetime of the common aggressor is calculated and used to calculate the magnitude of coupled noise on the victim wire induced by the aggressor wires. An alarm threshold for each potential victim wire is determined based upon the type of logic gate that receives the victim wire. The alarm thresholds for each potential victim wire are compared to the calculated height of a coupled noise on the victim wire to determine which, if any, wires of the design suffer enough crosstalk noise that they should be redesigned.
摘要翻译：描述了在数字逻辑集成电路中分析串扰的自动化方法，该方法在数字计算机上操作。该方法使用可用的软件从集成电路的布局中提取一个提取的参数化网表。对于多条电线中的至少一个潜在的受损线，确定芯片的导线的子集被发现是潜在的可能耦合到受电线的电缆。侵略者的电线被组合成一个共同的侵略者。计算共同侵略者的上升时间，并用于计算由侵略线引起的受害线上的耦合噪声的幅度。基于接收到受扰线的逻辑门的类型，确定每个潜在受害线的报警阈值。将每个潜在的受扰物线的报警阈值与受害线上的耦合噪声的计算高度进行比较，以确定设计中的哪一条线（如果有的话）遭受足够的串扰噪声，则应重新设计。

6. 发明授权

US6121807A Single phase edge-triggered dual-rail dynamic flip-flop 有权
标题翻译：单相边沿触发双轨动态触发器
公开(公告)号：US6121807A
公开(公告)日：2000-09-19
申请号：US317656
申请日：1999-05-24
申请人： Edgardo F. Klass , Chaim Amir
发明人： Edgardo F. Klass , Chaim Amir
IPC分类号： H03K3/356 , H03K3/037
CPC分类号： H03K3/356121
摘要： A single phase edge-triggered dual-rail dynamic flip-flop circuit for use with dynamic logic gates includes an input stage, precharge stage and buffer. The input stage is coupled to receive a data-input signal and a clock signal. During the precharge phase, the input stage provides an output signal that is the complement of the data input signal. When the data input signal is provided by a dynamic logic gate, the input stage output signal is precharged to a logic high level. During the evaluation phase, the input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low. The precharge stage receives the output signal from the input stage and the clock signal. During the precharge phase, the precharge stage generates a logic high level output signal independently of the signal received from the input stage. However, the logic high level signal from the input stage turns on hard a n-channel transistor in the precharge stage, which minimizes the delay through the precharge stage during the evaluation phase. During the evaluation phase, the precharge stage outputs the complement of the output signal received from the input stage. The buffer is coupled to receive the output signal from the precharge stage. During both the precharge and evaluation phases, the buffer outputs the complement of the output signal received from the precharge stage.
摘要翻译：用于动态逻辑门的单相边沿触发双轨动态触发器电路包括输入级，预充电级和缓冲器。输入级被耦合以接收数据输入信号和时钟信号。在预充电阶段期间，输入级提供作为数据输入信号的补码的输出信号。当数据输入信号由动态逻辑门提供时，输入级输出信号被预充电到逻辑高电平。在评估阶段期间，输入级产生一个输出信号，保持在逻辑高电平或从高到低转换。预充电阶段接收来自输入级的输出信号和时钟信号。在预充电阶段期间，预充电阶段独立于从输入级接收的信号产生逻辑高电平输出信号。然而，来自输入级的逻辑高电平信号在预充电阶段打开硬通道n沟道晶体管，这在评估阶段期间通过预充电阶段的延迟最小化。在评估阶段，预充电阶段输出从输入级接收的输出信号的补码。缓冲器被耦合以从预充电阶段接收输出信号。在预充电和评估阶段期间，缓冲器输出从预充电阶段接收的输出信号的补码。

7. 发明授权

US6018254A Non-blocking delayed clocking system for domino logic 失效
标题翻译：用于多米诺骨牌的非阻塞延迟计时系统
公开(公告)号：US6018254A
公开(公告)日：2000-01-25
申请号：US884841
申请日：1997-06-30
申请人： Alan C. Rogers , Edgardo F. Klass , Chaim Amir , Jason M. Hart
发明人： Alan C. Rogers , Edgardo F. Klass , Chaim Amir , Jason M. Hart
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A non-blocking multiple-phase clocking system for use with domino-type dynamic logic provides clock phases with overlapping evaluation phases to a circuit including a several cascaded dynamic logic gates. The circuit also includes a first flip-flop that is coupled to provide input signal(s) to the first dynamic logic gate of the cascade and a second flip-flop that is coupled to receive output signal(s) from the last dynamic logic gate of the cascade. The clocking system provides a first clock phase to the first dynamic logic gate, a second clock phase to the second dynamic logic gate and so on. A timing analysis is performed of each logic path in the circuit to determine the arrival time of each critical input signals to each dynamic logic gate. The delay between adjacent clock phase is then predetermined so that each dynamic logic gate enters its evaluation phase before the critical input signal(s) to the particular dynamic logic gate arrives. This adjustment of the clock phases maximizes the logic evaluation speed of the dynamic logic circuit.
摘要翻译：与多米诺式动态逻辑一起使用的非阻塞多相时钟系统为包括多个级联动态逻辑门的电路提供具有重叠评估阶段的时钟相位。电路还包括第一触发器，其被耦合以向级联的第一动态逻辑门提供输入信号;以及第二触发器，其被耦合以从最后的动态逻辑门接收输出信号的级联。时钟系统向第一动态逻辑门提供第一时钟相位，向第二动态逻辑门等提供第二时钟相位。对电路中的每个逻辑路径进行定时分析，以确定每个关键输入信号到达每个动态逻辑门的到达时间。然后预定相邻时钟相位之间的延迟，使得每个动态逻辑门在特定动态逻辑门的关键输入信号到达之前进入其评估阶段。时钟相位的这种调整使动态逻辑电路的逻辑评估速度最大化。

8. 发明授权

US5983013A Method for generating non-blocking delayed clocking signals for domino logic 失效
标题翻译：用于产生用于多米诺骨牌逻辑的非阻塞延迟时钟信号的方法
公开(公告)号：US5983013A
公开(公告)日：1999-11-09
申请号：US884840
申请日：1997-06-30
申请人： Alan C. Rogers , Edgardo F. Klass , Chaim Amir , Jason M. Hart
发明人： Alan C. Rogers , Edgardo F. Klass , Chaim Amir , Jason M. Hart
IPC分类号： G06F1/06 , H03K19/096 , G06F1/04 , H03K19/00
CPC分类号： G06F1/06 , H03K19/0963
摘要： A method for generating non-blocking multiple-phase clocking system for use with domino-type dynamic logic includes receiving a primary clock signal and generating several delayed phases of the received primary clock signal. The number of clock phases equals the number of dynamic logic gates in the circuit. The method provides a first clock phase to the first dynamic logic gate of the circuit, a second clock phase to the second dynamic logic gate and so on. A timing analysis is performed of each logic path in the circuit to determine the arrival time of each critical input signals to each dynamic logic gate. The delay between adjacent clock phase is then predetermined so that each dynamic logic gate enters its evaluation phase before the critical input signal(s) to the particular dynamic logic gate arrives. This adjustment of the clock phases maximizes the logic evaluation speed of the dynamic logic circuit.
摘要翻译：一种用于产生与多米诺式动态逻辑一起使用的无阻塞多相时钟系统的方法包括接收主时钟信号并产生接收的主时钟信号的几个延迟相位。时钟相位的数量等于电路中动态逻辑门的数量。该方法为电路的第一动态逻辑门提供第一时钟相位，向第二动态逻辑门等提供第二时钟相位。对电路中的每个逻辑路径进行定时分析，以确定每个关键输入信号到达每个动态逻辑门的到达时间。然后预定相邻时钟相位之间的延迟，使得每个动态逻辑门在特定动态逻辑门的关键输入信号到达之前进入其评估阶段。时钟相位的这种调整使动态逻辑电路的逻辑评估速度最大化。

9. 发明授权

US5880609A Non-blocking multiple phase clocking scheme for dynamic logic 失效
标题翻译：用于动态逻辑的非阻塞多相时钟方案
公开(公告)号：US5880609A
公开(公告)日：1999-03-09
申请号：US788710
申请日：1997-01-23
申请人： Edgardo F. Klass , David W. Poole , Gary R. Gouldsberry
发明人： Edgardo F. Klass , David W. Poole , Gary R. Gouldsberry
IPC分类号： H03K19/096 , H03K19/00
CPC分类号： H03K19/0963
摘要： A non-blocking multiple-phase clocking system for use with dynamic logic provides clock phases with overlapping evaluation phases to a circuit including a several cascaded dynamic logic gates. The circuit also includes a first flip-flop that is coupled to provide input signal(s) to the first dynamic logic gate of the cascade and a second flip-flop that is coupled to receive output signal(s) from the last dynamic logic gate of the cascade. Through the use of the overlapping evaluation phases and proper assignment of the clock signals to the dynamic logic gates, the output signal(s) generated by the dynamic logic gates receiving a particular clock phase are used as input signals to the dynamic logic gates receiving the next clock phase. Because of the overlapping of the clock phases, no latch is used. The clock phases are assigned to a particular dynamic logic gate so that the this dynamic logic gate enters the evaluation phase before the input signal(s) to the particular dynamic logic gate arrives (i.e., a "non-blocking") manner so that delay through the dynamic logic circuit can be minimized. To ensure that valid output signals are received by the dynamic logic gates receiving the next clock phase, the clock phases are assigned so that this particular dynamic logic gate receives its input signal(s) before the start of the evaluation phase of any subsequent clock phase.
摘要翻译：与动态逻辑一起使用的非阻塞多相时钟系统为包括多个级联动态逻辑门的电路提供具有重叠评估阶段的时钟相位。电路还包括第一触发器，其被耦合以向级联的第一动态逻辑门提供输入信号;以及第二触发器，其被耦合以从最后的动态逻辑门接收输出信号的级联。通过使用重叠评估阶段和将时钟信号正确地分配给动态逻辑门，由接收特定时钟相位的动态逻辑门产生的输出信号被用作输入信号给动态逻辑门，下一个时钟阶段由于时钟相位重叠，因此不使用锁存器。时钟相位被分配给特定的动态逻辑门，使得该动态逻辑门在到达特定动态逻辑门的输入信号（即，“非阻塞”）方式之前进入评估阶段，从而延迟通过动态逻辑电路可以最小化。为了确保接收下一个时钟相位的动态逻辑门接收到有效的输出信号，分配时钟相位，使得该特定动态逻辑门在任何后续时钟相位的评估阶段开始之前接收其输入信号。

10. 发明授权

US08947070B2 Apparatus and method for testing driver writeability strength on an integrated circuit 有权
标题翻译：在集成电路上测试驱动器可写性强度的装置和方法
公开(公告)号：US08947070B2
公开(公告)日：2015-02-03
申请号：US13351313
申请日：2012-01-17
申请人： Ashish R. Jain , Edgardo F. Klass
发明人： Ashish R. Jain , Edgardo F. Klass
IPC分类号： G11C8/00 , G01R31/3185 , G01R31/319
CPC分类号： G01R31/318572 , G01R31/31924
摘要： An apparatus and method for testing driver write-ability strength on an integrated circuit includes one or more drive detection units each including a number of drivers. At least some of the drivers may have a different drive strength and each may drive a voltage onto a respective driver output line. Each drive detection unit may include a number of keeper circuits, each coupled to a separate output line and configured to retain a given voltage on the output line to which it is coupled. Each detection unit may also include a number of detection circuits coupled to detect the drive voltage on each of the output lines. In one implementation, the drive voltage appearing at the output line of each driver may be indicative of that the driver was able to overdrive the voltage being retained on the output line to which it is coupled by the respective keeper circuits.
摘要翻译：用于在集成电路上测试驱动器写入能力强度的装置和方法包括一个或多个驱动器检测单元，每个驱动器检测单元包括多个驱动器。至少一些驱动器可能具有不同的驱动强度，并且每个驱动器可以将电压驱动到相应的驱动器输出线上。每个驱动器检测单元可以包括多个保持器电路，每个保持器电路分别耦合到单独的输出线并被配置为将给定电压保持在与其耦合的输出线上。每个检测单元还可以包括多个检测电路，其被耦合以检测每条输出线上的驱动电压。在一个实施方案中，出现在每个驱动器的输出线处的驱动电压可以指示驾驶员能够过度驱动保持在由相应保持器电路耦合到的输出线上的电压。

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