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1. 发明授权

US07890909B2 Automatic block composition tool for composing custom blocks having non-standard library cells in an integrated circuit design flow 有权
标题翻译：用于在集成电路设计流程中组合具有非标准库单元的定制块的自动块组合工具
公开(公告)号：US07890909B2
公开(公告)日：2011-02-15
申请号：US11968311
申请日：2008-01-02
申请人： Rambabu Pyapali , Peter F. Lai , Ju H. Yew , Xi-An Xu , Xiaochun Gao
发明人： Rambabu Pyapali , Peter F. Lai , Ju H. Yew , Xi-An Xu , Xiaochun Gao
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5072 , G06F17/5077 , G06F2217/66
摘要： An automatic custom block composition tool for composing custom blocks of an integrated circuit (IC) design that may include non-standard library cells. The tool includes program instructions that are executable to create and use a placement control file that includes instructions for use by the custom block composition tool to place the one or more non-standard library cells into the custom block layout. In addition, the program instructions may instantiate a leafcell for each non-standard and each standard library cell included in a netlist. The program instructions may access the placement control file and place each leafcell in a row of the custom block layout according to the placement control file. The program instructions may also pre-route power, clock and critical network signals, and generate a router control file used during remaining routing of the custom block by a conventional router tool.
摘要翻译：用于组合可能包括非标准库单元的集成电路（IC）设计的定制块的自动定制块组合工具。该工具包括可执行以创建和使用放置控制文件的程序指令，该文件包括自定义块组合工具用于将一个或多个非标准库单元放置到自定义块布局中的指令。此外，程序指令可以为网表中包括的每个非标准和每个标准库单元实例化叶单元。程序指令可以访问放置控制文件，并根据放置控制文件将每个叶单元格放置在自定义块布局的一行中。程序指令还可以预先布线电源，时钟和关键网络信号，并且生成在通过常规路由器工具剩余路由定制块期间使用的路由器控制文件。

2. 发明授权

US06775813B2 Aggregation of storage elements into stations and placement of same into an integrated circuit or design 有权
标题翻译：将存储元件聚合到站中并将其放置到集成电路或设计中
公开(公告)号：US06775813B2
公开(公告)日：2004-08-10
申请号：US10238357
申请日：2002-09-10
申请人： Sachin Chopra , Yu-Yen Mo , Shyam Sundar , Peter F. Lai , Kong-Fai Woo , Venkat Podduturi , Vishal Chopra
发明人： Sachin Chopra , Yu-Yen Mo , Shyam Sundar , Peter F. Lai , Kong-Fai Woo , Venkat Podduturi , Vishal Chopra
IPC分类号： G06F945
CPC分类号： G06F17/5072 , G06F17/5031
摘要： The present invention describes a method and apparatus for placing flops in a complex circuit design. Initially, the method calculates a physical range for every net that requires a flop, within which the flop can be placed satisfying the timing requirement. After the physical range is defined, the method groups these flops and determines a block where these grouped flops can be placed. Grouping these flops into one block (flop station) can preserve a compact layout for the design. The flops are then connected to appropriate nets.
摘要翻译：本发明描述了一种用于将触发器放置在复杂电路设计中的方法和装置。最初，该方法计算需要触发器的每个网络的物理范围，其中可以放置触发器以满足定时要求。在定义了物理范围之后，该方法将这些触发器分组并确定可以放置这些分组的触发器的块。将这些触发器分组到一个块（翻牌站）可以保留设计的紧凑布局。触发器然后连接到适当的网络。

3. 发明申请

US20090172622A1 AUTOMATIC BLOCK COMPOSITION TOOL FOR COMPOSING CUSTOM BLOCKS HAVING NON-STANDARD LIBRARY CELLS IN AN INTEGRATED CIRCUIT DESIGN FLOW 有权
标题翻译：用于在一体化电路设计流程中组合具有非标准图书馆的自定义块的自动块组合工具
公开(公告)号：US20090172622A1
公开(公告)日：2009-07-02
申请号：US11968311
申请日：2008-01-02
申请人： Rambabu Pyapali , Peter F. Lai , Ju H. Yew , Xi-An Xu , Xiaochun Gao
发明人： Rambabu Pyapali , Peter F. Lai , Ju H. Yew , Xi-An Xu , Xiaochun Gao
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5072 , G06F17/5077 , G06F2217/66
摘要： An automatic custom block composition tool for composing custom blocks of an integrated circuit (IC) design that may include non-standard library cells. The tool includes program instructions that are executable to create and use a placement control file that includes instructions for use by the custom block composition tool to place the one or more non-standard library cells into the custom block layout. In addition, the program instructions may instantiate a leafcell for each non-standard and each standard library cell included in a netlist. The program instructions may access the placement control file and place each leafcell in a row of the custom block layout according to the placement control file. The program instructions may also pre-route power, clock and critical network signals, and generate a router control file used during remaining routing of the custom block by a conventional router tool.
摘要翻译：用于组合可能包括非标准库单元的集成电路（IC）设计的定制块的自动定制块组合工具。该工具包括可执行以创建和使用放置控制文件的程序指令，该文件包括自定义块组合工具用于将一个或多个非标准库单元放置到自定义块布局中的指令。此外，程序指令可以为网表中包括的每个非标准和每个标准库单元实例化叶单元。程序指令可以访问放置控制文件，并根据放置控制文件将每个叶单元格放置在自定义块布局的一行中。程序指令还可以预先布线电源，时钟和关键网络信号，并且生成在通过常规路由器工具剩余路由定制块期间使用的路由器控制文件。

4. 发明授权

US07036096B1 Estimating capacitances using information including feature sizes extracted from a netlist 有权
标题翻译：使用从网表提取的包括特征尺寸的信息估算电容
公开(公告)号：US07036096B1
公开(公告)日：2006-04-25
申请号：US10657431
申请日：2003-09-08
申请人： Aveek Sarkar , Yongning Sheng , Peter F. Lai , Rambabu Pyapali
发明人： Aveek Sarkar , Yongning Sheng , Peter F. Lai , Rambabu Pyapali
IPC分类号： G06F17/50
CPC分类号： G06F17/5009
摘要： The capacitances of one or more inputs/outputs of a circuit are estimated by using an extraction tool (120) to extract information associated with the inputs/outputs from a netlist. The information includes information associated with circuit devices directly connected to the inputs/outputs, particularly information related to device connectivity and the feature sizes of the device. Once the information is extracted, a capacitance determination element (130) aggregates the feature sizes of all the circuit devices connected to each respective input or output, to obtain aggregate feature sizes for each respective input/output. The aggregate feature size is used in determining the total capacitance of the input/output. The total capacitance thus determined can be provided to a timing analysis tool (140), which uses the total capacitance of each input or output to generate a timing model for the circuit.
摘要翻译：通过使用提取工具（120）来从网表提取与输入/输出相关联的信息来估计电路的一个或多个输入/输出的电容。信息包括与直接连接到输入/输出的电路设备相关联的信息，特别是与设备连接性和设备的特征尺寸有关的信息。一旦提取了信息，电容确定元件（130）聚合连接到每个相应输入或输出的所有电路设备的特征尺寸，以获得每个相应输入/输出的聚集特征尺寸。聚合特征尺寸用于确定输入/输出的总电容。这样确定的总电容可以提供给定时分析工具（140），其使用每个输入或输出的总电容来产生电路的定时模型。

5. 发明授权

US07007256B2 Method and apparatus for power consumption analysis in global nets 有权
标题翻译：全球网络功耗分析方法与装置
公开(公告)号：US07007256B2
公开(公告)日：2006-02-28
申请号：US10383092
申请日：2003-03-06
申请人： Aveek Sarkar , Shyam Sundar , Peter F. Lai , Rambabu Pyapali
发明人： Aveek Sarkar , Shyam Sundar , Peter F. Lai , Rambabu Pyapali
IPC分类号： G06F9/45 , G06F9/455 , G06F17/50
CPC分类号： G06F17/5022 , G06F17/505 , G06F2217/78
摘要： The present invention describes a method and an apparatus for determining switching power consumption of global devices (e.g., repeaters, flops or the like) in an integrated circuit design during high-level design phase after the global routing for the integrated circuit is available. The clock cycle is divided into various timing intervals and the timing reports are generated for each cycle to determine a time-domain staggered distribution of each device's switching activity within a given timing interval. Each device's switching activity is analyzed within the given timing interval (or segment thereof). The power consumption is determined for each device that switches in the given timing interval.
摘要翻译：本发明描述了在集成电路的全局路由可用之后在高级设计阶段期间在集成电路设计中确定全局设备（例如，中继器，触发器等）的开关功耗的方法和装置。时钟周期分为不同的定时间隔，并为每个周期生成定时报告，以确定给定时间间隔内每个设备的交换活动的时域交错分布。在给定的时间间隔（或其段）内分析每个设备的切换活动。确定在给定时间间隔内切换的每个设备的功耗。

6. 发明授权

US06396149B1 Method for double-layer implementation of metal options in an integrated chip for efficient silicon debug 有权
标题翻译：用于双层实现集成芯片中金属选项的方法，用于高效硅调试
公开(公告)号：US06396149B1
公开(公告)日：2002-05-28
申请号：US09593284
申请日：2000-06-13
申请人： Xuejun Yuan , Xiaowei Jin , Rambabu Pyapali , Raymond A. Heald , James M. Kaku , Helen Dunn , Thelma C. Taylor , Peter F. Lai , Aharon Ostrer
发明人： Xuejun Yuan , Xiaowei Jin , Rambabu Pyapali , Raymond A. Heald , James M. Kaku , Helen Dunn , Thelma C. Taylor , Peter F. Lai , Aharon Ostrer
IPC分类号： H01L2710
CPC分类号： H01L22/22 , H01L23/525 , H01L2924/0002 , H01L2924/00
摘要： In one aspect of the present invention, a method provides a connecting path diversion through an upper layer of an integrated circuit by alteration of a connecting path through a lower layer of the integrated circuit. This method enables a circuit path in an integrated circuit to be modified in an accessible layer for testing before the modified circuit path is incorporated in a redesigned integrated circuit design. In another aspect of the present invention, a modified multi-layer integrated circuit chip includes a connecting path formed in a lower layer and a substitute connecting path that is etched in the lower layer. Subsequently, the connecting path formed in the lower layer may be severed.
摘要翻译：在本发明的一个方面中，一种方法是通过改变通过集成电路的下层的连接路径来提供通过集成电路的上层的连接路径。该方法使得在经修改的电路路径被并入重新设计的集成电路设计之后，集成电路中的电路路径能够在可访问层中进行修改以进行测试。在本发明的另一方面，一种修改的多层集成电路芯片包括形成在下层中的连接路径和在下层中蚀刻的替代连接路径。随后，形成在下层中的连接路径可能被切断。

7. 发明授权

US07284215B1 Method to solve similar timing paths 有权
标题翻译：解决类似时序路径的方法
公开(公告)号：US07284215B1
公开(公告)日：2007-10-16
申请号：US10798046
申请日：2004-03-11
申请人： Von-Kyoung Kim , Dakshesh Amin , Sriram Satakopan , Peter F. Lai
发明人： Von-Kyoung Kim , Dakshesh Amin , Sriram Satakopan , Peter F. Lai
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A technique for improving multiple critical timing paths that exhibit similar characteristics has been discovered. The technique efficiently improves multiple critical timing paths by reducing the number of unique critical timing path patterns for analysis. In some embodiments of the present invention a method for use in connection with an integrated circuit design includes identifying distinct timing paths of the integrated circuit design. The distinct timing paths have timing violations. The method includes associating a first plurality of the distinct timing paths with a first set of timing paths. Individual ones of the first plurality belonging to a second set of timing paths and include a first common characteristic. The method includes improving the first set of timing paths based at least in part on an improvement to an individual timing path of the first set of timing paths.
摘要翻译：已经发现了用于改进表现出相似特征的多个关键时序路径的技术。该技术通过减少用于分析的唯一关键时序路径模式的数量来有效地改善多个关键定时路径。在本发明的一些实施例中，结合集成电路设计使用的方法包括识别集成电路设计的不同的定时路径。不同的定时路径具有定时违规。该方法包括将第一多个不同的定时路径与第一组定时路径相关联。属于第二组定时路径的第一个复数个体中的各个包括第一共同特性。该方法包括至少部分地基于对第一组定时路径的单个定时路径的改进来改进第一组定时路径。

8. 发明授权

US07109757B2 Leakage-tolerant dynamic wide-NOR circuit structure 有权
标题翻译：耐漏电动态宽NOR电路结构
公开(公告)号：US07109757B2
公开(公告)日：2006-09-19
申请号：US10990140
申请日：2004-11-15
申请人： Xeujun Yuan , Ye Xiong , Peter F. Lai
发明人： Xeujun Yuan , Ye Xiong , Peter F. Lai
IPC分类号： H03K19/096
CPC分类号： G11C7/12 , H03K19/0963
摘要： One embodiment of the present invention provides a circuit which blocks a keeper from interfering with a dynamic node during an evaluation phase for a dynamic wide-NOR structure. The circuit contains a precharge device which is coupled to the dynamic node. The precharge device precharges the dynamic node during a precharge phase. The circuit also contains a plurality of parallel pull-down transistors which are coupled to the dynamic node. The pull-down transistors conditionally discharge the dynamic node during the evaluate phase. The keeper sustains a precharged value on the dynamic node, thereby preventing a false evaluation caused by a leakage current through the parallel pull-down transistors. In addition, the circuit contains a feedback gating device which is coupled between the keeper and the dynamic node. During the evaluation phase, the feedback gating device blocks the keeper, so that the parallel pull-down transistors can discharge the dynamic node without interference from the keeper.
摘要翻译：本发明的一个实施例提供一种在动态宽NOR结构的评估阶段期间阻止保持器干扰动态节点的电路。电路包含耦合到动态节点的预充电装置。预充电装置在预充电阶段预充电动态节点。电路还包含耦合到动态节点的多个并联下拉晶体管。在评估阶段，下拉晶体管有条件地放电动态节点。保持器在动态节点上保持预充电值，从而防止由并联下拉晶体管的漏电流引起的虚假评估。另外，该电路包含耦合在保持器和动态节点之间的反馈门控装置。在评估阶段期间，反馈门控装置阻止保持器，使得并联下拉晶体管可以放电动态节点而不受到保持器的干扰。

9. 发明授权

US06954914B2 Method and apparatus for signal electromigration analysis 有权
标题翻译：用于信号电迁移分析的方法和装置
公开(公告)号：US06954914B2
公开(公告)日：2005-10-11
申请号：US10395436
申请日：2003-03-24
申请人： Shyam Sundar , Aveek Sarkar , Peter F. Lai , Rambabu Pyapali , Teong Ming Cheah
发明人： Shyam Sundar , Aveek Sarkar , Peter F. Lai , Rambabu Pyapali , Teong Ming Cheah
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5036
摘要： The present application describes various embodiments of a method and an apparatus for determining electromigration risks for signal nets in integrated circuits. A model for each one of the global nets connecting various circuit blocks in an integrated circuit is created using circuit blocks' timing model and detailed standard parasitic format representation (DSPF) of each global net. The final layout of the integrated circuit is not necessary to determine the electromigration risks. The models can be generated during the early stages of the design cycle once the DSPF of the global nets is available.
摘要翻译：本申请描述了用于确定集成电路中的信号网的电迁移风险的方法和装置的各种实施例。使用电路块的定时模型和每个全局网络的详细标准寄生格式表示（DSPF），创建连接集成电路中的各种电路块的每个全球网络的模型。集成电路的最终布局不需要确定电迁移风险。一旦全球网络的DSPF可用，这些模型可以在设计周期的早期阶段生成。

10. 发明授权

US06596563B2 Method for double-layer implementation of metal options in an integrated chip for efficient silicon debug 有权
公开(公告)号：US06596563B2
公开(公告)日：2003-07-22
申请号：US10091620
申请日：2002-03-04
申请人： Xuejun Yuan , Xiaowei Jin , Rambabu Pyapali , Raymond A. Heald , James M. Kaku , Helen Dunn , Thelma C. Taylor , Peter F. Lai , Aharon Ostrer
发明人： Xuejun Yuan , Xiaowei Jin , Rambabu Pyapali , Raymond A. Heald , James M. Kaku , Helen Dunn , Thelma C. Taylor , Peter F. Lai , Aharon Ostrer
IPC分类号： H01L2144
CPC分类号： H01L22/22 , H01L23/525 , H01L2924/0002 , H01L2924/00
摘要： In one aspect of the present invention, a method provides a connecting path diversion through an upper layer of an integrated circuit by alteration of a connecting path through a lower layer of the integrated circuit. This method enables a circuit path in an integrated circuit to be modified in an accessible layer for testing before the modified circuit path is incorporated in a redesigned integrated circuit design. In another aspect of the present invention, a modified multi-layer integrated circuit chip includes a connecting path formed in a lower layer and a substitute connecting path that is etched in the lower layer. Subsequently, the connecting path formed in the lower layer may be severed.

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