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1. 发明授权

US07215175B1 Fuse sensing scheme with auto current reduction 有权
标题翻译：具有自动电流降低的保险丝感测方案
公开(公告)号：US07215175B1
公开(公告)日：2007-05-08
申请号：US10932162
申请日：2004-09-01
申请人： Gurupada Mandal , Suresh Seshadri , David Hugh McIntyre , Raymond A. Heald , William Y. Mo
发明人： Gurupada Mandal , Suresh Seshadri , David Hugh McIntyre , Raymond A. Heald , William Y. Mo
IPC分类号： H01H37/76 , H01H85/00
CPC分类号： G11C17/18
摘要： An improved circuit for sensing and programming fuses in integrated circuits. The circuit is broadly comprised of a fuse cell, a reference circuit, a sense amplifier and a level detector. In one embodiment of the present invention, a two-stage sensing scheme is implemented. The improved fuse sensing circuit uses current-mode sensing and implements an auto-read current reduction scheme. Using a level-detect circuit, the virtual ground is raised automatically if the high-voltage power supply exceeds core supply (Vdd) by a fixed dc voltage. This reduces effective sensing voltage and the read current and thus helps preserve unblown fuse integrity. In one embodiment of the invention, four modes of operation are implemented: “Normal Read,” “Unblown_Read,” “Blown_Read_1” and “Blown_Read_2.” The default read mode is the “normal read” while the “Unblown” and “Blown” read modes are for fuse calibration purposes. In the “Unblown_Read” read mode, the circuit is operable to compare the fuse resistance against a lower reference resistance, closer to an unblown fuse resistance value, in order to make the comparison more stringent. Similarly, the “Blown_Read_1” and “Blown_Read_2” modes allow a more stringent comparison for a blown fuse resistance.
摘要翻译：一种用于在集成电路中感测和编程保险丝的改进电路。该电路广泛地包括熔丝单元，参考电路，读出放大器和电平检测器。在本发明的一个实施例中，实现了两级感测方案。改进的熔丝感测电路使用电流模式感测并实现自动读取电流降低方案。使用电平检测电路，如果高压电源以固定的直流电压超过磁芯电源（Vdd），则虚拟接地将自动升高。这降低了有效的感测电压和读取电流，从而有助于保持未熔断的保险丝完整性。在本发明的一个实施例中，实现了四种操作模式：“Normal Read”，“Unblown_Read”，“Blown_Read_1”和“Blown_Read_2”。 “Unblown”和“Blown”读取模式的默认读取模式是“正常读取”，用于保险丝校准。在“Unblown_Read”读取模式下，该电路可操作以将熔丝电阻与较低的参考电阻进行比较，更接近未熔断的保险丝电阻值，以使比较更加严格。类似地，“Blown_Read_1”和“Blown_Read_2”模式允许对熔断熔断器电阻进行更严格的比较。

2. 发明授权

US08788789B2 Power filter in data translation look-aside buffer based on an input linear address 有权
标题翻译：基于输入线性地址的数据转换后备缓冲器中的电源滤波器
公开(公告)号：US08788789B2
公开(公告)日：2014-07-22
申请号：US12968613
申请日：2010-12-15
申请人： Deepika Kapil , David Hugh McIntyre
发明人： Deepika Kapil , David Hugh McIntyre
IPC分类号： G06F9/34
CPC分类号： G06F12/1027 , G06F2212/1028 , Y02D10/13
摘要： A method and an apparatus for power filtering in a Translation Look-aside Buffer (TLB) are described. In the method and apparatus, power consumption reduction is achieved by suppressing physical address (PA) reads from random access memory (RAM) if the previously translated linear address (LA), or virtual address (VA), is the same as the currently requested LA. To provide the correct translation, the output of the TLB is maintained if the previously translated LA and the LA currently requested for translation are the same.
摘要翻译：描述了翻译后备缓冲器（TLB）中的功率滤波的方法和装置。在该方法和装置中，如果先前翻译的线性地址（LA）或虚拟地址（VA）与当前请求的数据相同，则通过抑制来自随机存取存储器（RAM）的物理地址（PA）读取来实现功耗降低洛杉矶为了提供正确的翻译，如果先前翻译的LA和LA当前要求翻译的LA是相同的，则保持TLB的输出。

3. 发明授权

US08374039B2 Multi-port memory array 有权
标题翻译：多端口存储器阵列
公开(公告)号：US08374039B2
公开(公告)日：2013-02-12
申请号：US12975718
申请日：2010-12-22
申请人： David Hugh McIntyre , Jimmy L. Reaves
发明人： David Hugh McIntyre , Jimmy L. Reaves
IPC分类号： G11C7/06
CPC分类号： G11C7/1075
摘要： A multi-port memory array is disclosed. The memory array includes a plurality of memory subblocks and an output network. Each memory subblock includes a plurality of single-read-port memory cells. The output network is configured to redirect information read for a first read port to a second read port on a condition that an equivalence signal indicates that read addresses for the first read port and the second read port are the same. The latching and multiplexing operation may be integrated. The memory cells may be 6-transistor synchronous random access memory (SRAM) cells, 8-transistor SRAM cells, or any type of memory cells.
摘要翻译：公开了一种多端口存储器阵列。存储器阵列包括多个存储器子块和输出网络。每个存储器子块包括多个单个读取端口存储器单元。输出网络被配置为在等效信号指示第一读取端口和第二读取端口的读取地址相同的条件下将用于第一读取端口读取的信息重定向到第二读取端口。锁存和复用操作可以被集成。存储单元可以是6晶体管同步随机存取存储器（SRAM）单元，8晶体管SRAM单元或任何类型的存储单元。

4. 发明申请

US20120159056A1 POWER FILTER IN DATA TRANSLATION LOOK-ASIDE BUFFER BASED ON AN INPUT LINEAR ADDRESS 有权
标题翻译：基于输入线性地址的数据转换中的电源滤波器
公开(公告)号：US20120159056A1
公开(公告)日：2012-06-21
申请号：US12968613
申请日：2010-12-15
申请人： Deepika Kapil , David Hugh McIntyre
发明人： Deepika Kapil , David Hugh McIntyre
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G06F12/1027 , G06F2212/1028 , Y02D10/13
摘要： A method and an apparatus for power filtering in a Translation Look-aside Buffer (TLB) are described. In the method and apparatus, power consumption reduction is achieved by suppressing physical address (PA) reads from random access memory (RAM) if the previously translated linear address (LA), or virtual address (VA), is the same as the currently requested LA. To provide the correct translation, the output of the TLB is maintained if the previously translated LA and the LA currently requested for translation are the same.
摘要翻译：描述了翻译后备缓冲器（TLB）中的功率滤波的方法和装置。在该方法和装置中，如果先前翻译的线性地址（LA）或虚拟地址（VA）与当前请求的数据相同，则通过抑制来自随机存取存储器（RAM）的物理地址（PA）读取来实现功耗降低洛杉矶为了提供正确的翻译，如果先前翻译的LA和LA当前要求翻译的LA是相同的，则保持TLB的输出。

5. 发明申请

US20120137109A1 METHOD AND APPARATUS FOR PERFORMING STORE-TO-LOAD FORWARDING FROM AN INTERLOCKING STORE USING AN ENHANCED LOAD/STORE UNIT IN A PROCESSOR 有权
标题翻译：使用处理器中的增强负载/存储单元从互连存储进行存储负载转发的方法和装置
公开(公告)号：US20120137109A1
公开(公告)日：2012-05-31
申请号：US12956299
申请日：2010-11-30
申请人： Krishnan Ramani , Chitresh C. Narasimhaiah , David Hugh McIntyre
发明人： Krishnan Ramani , Chitresh C. Narasimhaiah , David Hugh McIntyre
IPC分类号： G06F9/312
CPC分类号： G06F9/3834 , G06F9/3826
摘要： A method and a processor load/store unit (LSU) are described for performing store-to-load forwarding (STLF) from an interlocking store. STLF is performed when a starting address of the store and the load do not match, or when a data size of the store is smaller than a data size of the load. The LSU detects a load that interlocks with a store, and determines whether all or only a portion of data bytes needed by the load can be provided by the interlocking store. If it is determined that only a portion of the data bytes needed by the load can be provided by the interlocking store, then that portion of the data bytes is provided by a store data buffer (SDB) and the remaining portion of the data bytes needed by the load is provided by a data cache (DC). Otherwise, the SDB provides all of the data bytes.
摘要翻译：描述了一种从联锁商店执行存储到负载转发（STLF）的方法和处理器加载/存储单元（LSU）。当存储的起始地址和负载不匹配时，或者当存储的数据大小小于负载的数据大小时，执行STLF。 LSU检测与存储互锁的负载，并且确定负载所需的全部或仅一部分数据字节可以由联锁存储提供。如果确定只能通过联锁存储器提供负载所需的数据字节的一部分，则该部分数据字节由存储数据缓冲器（SDB）提供，并且数据字节的剩余部分需要由负载由数据缓存（DC）提供。否则，SDB提供所有数据字节。

6. 发明申请

US20120163059A1 CONDITIONALLY PRECHARGED DYNAMIC CONTENT ADDRESSABLE MEMORY 失效
标题翻译：条件预先动态内容可寻址记忆
公开(公告)号：US20120163059A1
公开(公告)日：2012-06-28
申请号：US12975601
申请日：2010-12-22
申请人： Mandeep Singh , David Hugh McIntyre , Hung Phuong Ngo
发明人： Mandeep Singh , David Hugh McIntyre , Hung Phuong Ngo
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： A conditionally precharged content addressable memory (CAM) includes forcing a mismatch on a matchline of the CAM if a data entry in the CAM is invalid. The matchline of the CAM is precharged only if the data entry is valid.
摘要翻译：如果CAM中的数据条目无效，则条件预充电的内容可寻址存储器（CAM）包括强制CAM的匹配线上的不匹配。仅当数据输入有效时，CAM的匹配线才被预充电。

7. 发明授权

US5831302A Voltage reference circuit 失效
标题翻译：电压参考电路
公开(公告)号：US5831302A
公开(公告)日：1998-11-03
申请号：US559490
申请日：1995-11-15
申请人： David Hugh McIntyre
发明人： David Hugh McIntyre
IPC分类号： G01R1/28 , G01R19/165 , G05F3/24 , G05F3/30 , G11C5/14 , G11C16/06 , G11C17/00 , G05F3/16 , G05F3/20
CPC分类号： G05F3/247 , G11C5/147
摘要： The voltage reference circuit is provided particularly but not exclusively for use in flash EPROM chips. The reference circuit is intended to be inhibited until proper start-up conditions have been established to allow the reference circuit to operate properly. This is achieved by incorporating an enable signal generating circuit which is responsive to start-up circuitry for generating an enable signal at an appropriate signal level.
摘要翻译：电压参考电路特别但非专门用于闪存EPROM芯片。参考电路旨在被禁止，直到建立适当的启动条件以使参考电路正常工作。这通过结合使能信号发生电路来实现，该电路响应启动电路，以在适当的信号电平产生使能信号。

8. 发明授权

US08683179B2 Method and apparatus for performing store-to-load forwarding from an interlocking store using an enhanced load/store unit in a processor 有权
标题翻译：用于使用处理器中的增强的加载/存储单元从联锁商店执行存储到负载转发的方法和装置
公开(公告)号：US08683179B2
公开(公告)日：2014-03-25
申请号：US12956299
申请日：2010-11-30
申请人： Krishnan Ramani , Chitresh C. Narasimhaiah , David Hugh McIntyre
发明人： Krishnan Ramani , Chitresh C. Narasimhaiah , David Hugh McIntyre
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3834 , G06F9/3826
摘要： A method and a processor load/store unit (LSU) are described for performing store-to-load forwarding (STLF) from an interlocking store. STLF is performed when a starting address of the store and the load do not match, or when a data size of the store is smaller than a data size of the load. The LSU detects a load that interlocks with a store, and determines whether all or only a portion of data bytes needed by the load can be provided by the interlocking store. If it is determined that only a portion of the data bytes needed by the load can be provided by the interlocking store, then that portion of the data bytes is provided by a store data buffer (SDB) and the remaining portion of the data bytes needed by the load is provided by a data cache (DC). Otherwise, the SDB provides all of the data bytes.
摘要翻译：描述了一种从联锁商店执行存储到负载转发（STLF）的方法和处理器加载/存储单元（LSU）。当存储的起始地址和负载不匹配时，或者当存储的数据大小小于负载的数据大小时，执行STLF。 LSU检测与存储互锁的负载，并且确定负载所需的全部或仅一部分数据字节可以由联锁存储提供。如果确定只能通过联锁存储器提供负载所需的一部分数据字节，则该部分数据字节由存储数据缓冲器（SDB）提供，并且数据字节的剩余部分需要由负载由数据缓存（DC）提供。否则，SDB提供所有数据字节。

9. 发明授权

US08503210B2 Conditionally precharged dynamic content addressable memory 失效
标题翻译：有条件预充电动态内容可寻址内存
公开(公告)号：US08503210B2
公开(公告)日：2013-08-06
申请号：US12975601
申请日：2010-12-22
申请人： Mandeep Singh , David Hugh McIntyre , Hung Phuong Ngo
发明人： Mandeep Singh , David Hugh McIntyre , Hung Phuong Ngo
IPC分类号： G11C15/04 , G11C15/00
CPC分类号： G11C15/04
摘要： A conditionally precharged content addressable memory (CAM) includes forcing a mismatch on a matchline of the CAM if a data entry in the CAM is invalid. The matchline of the CAM is precharged only if the data entry is valid.
摘要翻译：如果CAM中的数据条目无效，则条件预充电的内容可寻址存储器（CAM）包括强制CAM的匹配线上的不匹配。仅当数据输入有效时，CAM的匹配线才被预充电。

10. 发明申请

US20120163102A1 MULTI-PORT MEMORY ARRAY 有权
标题翻译：多端口存储阵列
公开(公告)号：US20120163102A1
公开(公告)日：2012-06-28
申请号：US12975718
申请日：2010-12-22
申请人： David Hugh McIntyre , Jimmy L. Reaves
发明人： David Hugh McIntyre , Jimmy L. Reaves
IPC分类号： G11C7/00 , G11C8/16 , G11C8/00
CPC分类号： G11C7/1075
摘要： A multi-port memory array is disclosed. The memory array includes a plurality of memory subblocks and an output network. Each memory subblock includes a plurality of single-read-port memory cells. The output network is configured to redirect information read for a first read port to a second read port on a condition that an equivalence signal indicates that read addresses for the first read port and the second read port are the same. The latching and multiplexing operation may be integrated. The memory cells may be 6-transistor synchronous random access memory (SRAM) cells, 8-transistor SRAM cells, or any type of memory cells.
摘要翻译：公开了一种多端口存储器阵列。存储器阵列包括多个存储器子块和输出网络。每个存储器子块包括多个单个读取端口存储器单元。输出网络被配置为在等效信号指示第一读取端口和第二读取端口的读取地址相同的条件下将用于第一读取端口读取的信息重定向到第二读取端口。锁存和复用操作可以被集成。存储单元可以是6晶体管同步随机存取存储器（SRAM）单元，8晶体管SRAM单元或任何类型的存储单元。

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