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1. 发明授权

US08742570B2 Backplate interconnect with integrated passives 有权
标题翻译：带集成无源器件的背板互连
公开(公告)号：US08742570B2
公开(公告)日：2014-06-03
申请号：US13229561
申请日：2011-09-09
申请人： Ravindra V. Shenoy , Marc Maurice Mignard , Manish Kothari , Clarence Chui
发明人： Ravindra V. Shenoy , Marc Maurice Mignard , Manish Kothari , Clarence Chui
IPC分类号： H01L23/34
CPC分类号： H01L24/09 , B81C1/00238 , H01L23/5389 , H01L24/03 , H01L24/89 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/12044 , H01L2924/1306 , H01L2924/13091 , H01L2924/1461 , H01L2924/15788 , H01L2924/00
摘要： This disclosure provides systems, methods and apparatus for manufacturing display devices having electronic components mounted within a display device package. In one aspect, the electronic component connects to the exterior of the display device through pads that run below a seal that holds a substrate and a backplate of the display device together. In another aspect the electronic components also connect to an electromechanical device within the display device, as well as connecting to pads that are external to the display device.
摘要翻译：本公开提供了用于制造具有安装在显示装置封装内的电子部件的显示装置的系统，方法和装置。在一个方面，电子部件通过在保持显示装置的基板和背板的密封件下面的垫片连接到显示装置的外部。在另一方面，电子部件还连接到显示装置内的机电装置，以及连接到显示装置外部的焊盘。

2. 发明申请

US20130063415A1 BACKPLATE INTERCONNECT WITH INTEGRATED PASSIVES 有权
标题翻译：具有集成式失效的背板互连
公开(公告)号：US20130063415A1
公开(公告)日：2013-03-14
申请号：US13229561
申请日：2011-09-09
申请人： Ravindra V. Shenoy , Marc Maurice Mignard , Manish Kothari , Clarence Chui
发明人： Ravindra V. Shenoy , Marc Maurice Mignard , Manish Kothari , Clarence Chui
IPC分类号： G06T1/00 , H01J9/00 , H01J9/26 , H05K7/02
CPC分类号： H01L24/09 , B81C1/00238 , H01L23/5389 , H01L24/03 , H01L24/89 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/12044 , H01L2924/1306 , H01L2924/13091 , H01L2924/1461 , H01L2924/15788 , H01L2924/00
摘要： This disclosure provides systems, methods and apparatus for manufacturing display devices having electronic components mounted within a display device package. In one aspect, the electronic component connects to the exterior of the display device through pads that run below a seal that holds a substrate and a backplate of the display device together. In another aspect the electronic components also connect to an electromechanical device within the display device, as well as connecting to pads that are external to the display device.
摘要翻译：本公开提供了用于制造具有安装在显示装置封装内的电子部件的显示装置的系统，方法和装置。在一个方面，电子部件通过在保持显示装置的基板和背板的密封件下面的垫片连接到显示装置的外部。在另一方面，电子部件还连接到显示装置内的机电装置，以及连接到显示装置外部的焊盘。

3. 发明授权

US09045332B2 Thin back glass interconnect 有权
标题翻译：薄背玻璃互连
公开(公告)号：US09045332B2
公开(公告)日：2015-06-02
申请号：US13306284
申请日：2011-11-29
申请人： Ravindra V. Shenoy
发明人： Ravindra V. Shenoy
IPC分类号： A61F13/00 , B81C1/00
CPC分类号： B81C1/00047 , B81B2203/0315 , B81B2207/092 , B81B2207/095 , B81C1/00301 , B81C2203/0127
摘要： This disclosure provides systems, methods and apparatus for providing packaged microelectromechanical systems (MEMS) devices. In one aspect, package can include a cover glass joined to a device substrate, the cover glass including integrated electrical connectivity and configured to encapsulate one or more MEMS devices on the device substrate. The cover glass can include one or more spin-on glass layers and electrically conductive routing and interconnects. The package can include a narrow seal surrounding the one or more encapsulated MEMS devices.
摘要翻译：本公开提供了用于提供封装的微机电系统（MEMS）装置的系统，方法和装置。在一个方面，封装可以包括接合到器件衬底的覆盖玻璃，所述覆盖玻璃包括集成的电连接并且被配置为将一个或多个MEMS器件封装在所述器件衬底上。盖玻璃可以包括一个或多个旋涂玻璃层和导电布线和互连。封装可以包括围绕一个或多个封装的MEMS器件的窄密封。

4. 发明申请

US20130241939A1 HIGH CAPACITANCE DENSITY METAL-INSULATOR-METAL CAPACITORS 审中-公开
标题翻译：高电容密度金属绝缘体 - 金属电容器
公开(公告)号：US20130241939A1
公开(公告)日：2013-09-19
申请号：US13454949
申请日：2012-04-24
申请人： Jon Bradley Lasiter , Ravindra V. Shenoy , Justin Phelps Black , Donald William Kidwell
发明人： Jon Bradley Lasiter , Ravindra V. Shenoy , Justin Phelps Black , Donald William Kidwell
IPC分类号： H05K1/00 , G06T1/00 , H05K3/00 , H05K1/09
CPC分类号： H01L28/40 , H01G4/1209 , H01G4/33 , H01L23/642 , H01L28/60 , H01L2924/0002 , Y10T29/49124 , H01L2924/00
摘要： This disclosure provides systems, methods, and apparatus for high capacitance density metal-insulator-metal capacitors. In one aspect, an apparatus may include a first base metal layer on a first side of a substrate. A first polymer layer may be disposed on the first base metal layer and on the first side of the substrate. The first polymer layer may define a first plurality of vias though the first polymer layer, the first plurality of vias exposing portions of the first base metal layer. A first electrode layer may be disposed on the first polymer layer. The first electrode layer may contact the portions of the first base metal layer. A first dielectric layer may be disposed on the first electrode layer. A second electrode layer may be disposed on the first dielectric layer. The first dielectric layer may electrically isolate the first electrode layer from the second electrode layer.
摘要翻译：本公开提供了用于高电容密度金属 - 绝缘体 - 金属电容器的系统，方法和装置。在一个方面，设备可以包括在基板的第一侧上的第一基底金属层。第一聚合物层可以设置在第一基底金属层上和衬底的第一侧上。第一聚合物层可以通过第一聚合物层限定第一多个通孔，第一多个通孔暴露第一基底金属层的部分。第一电极层可以设置在第一聚合物层上。第一电极层可以接触第一基底金属层的部分。第一电介质层可以设置在第一电极层上。第二电极层可以设置在第一电介质层上。第一电介质层可以将第一电极层与第二电极层电隔离。

5. 发明申请

US20130050227A1 GLASS AS A SUBSTRATE MATERIAL AND A FINAL PACKAGE FOR MEMS AND IC DEVICES 审中-公开
标题翻译：作为基板材料的玻璃和用于MEMS和IC器件的最终封装
公开(公告)号：US20130050227A1
公开(公告)日：2013-02-28
申请号：US13221701
申请日：2011-08-30
申请人： Kurt Edward Petersen , Ravindra V. Shenoy , Justin Phelps Black , David William Burns , Srinivasan Kodaganallur Ganapathi , Philip Jason Stephanou , Nicholas Ian Buchan
发明人： Kurt Edward Petersen , Ravindra V. Shenoy , Justin Phelps Black , David William Burns , Srinivasan Kodaganallur Ganapathi , Philip Jason Stephanou , Nicholas Ian Buchan
IPC分类号： G06T1/00 , H01L29/04 , B65D85/00 , H01L23/48
CPC分类号： H01L23/10 , B81B7/007 , B81B2201/047 , B81B2207/012 , B81B2207/095 , B81B2207/096 , B81B2207/097 , B81C2203/0118 , B81C2203/0792 , H01L23/053 , H01L23/055 , H01L23/057 , H01L23/08 , H01L23/15 , H01L23/49827 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2924/01322 , H01L2924/01327 , H01L2924/10253 , H01L2924/12044 , H01L2924/13091 , H01L2924/1461 , H01L2924/3025 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： This disclosure provides systems, methods and apparatus for glass packaging of integrated circuit (IC) and electromechanical systems (EMS) devices. In one aspect, a glass package may include a glass substrate, a cover glass and one or more devices encapsulated between the glass substrate and the cover glass. The cover glass may be bonded to the glass substrate with an adhesive such as an epoxy, or a metal bond ring. The glass package also may include one or more signal transmission pathways between the one or more devices and the package exterior. In some implementations, a glass package including an EMS and/or IC device is configured to be directly attached to a printed circuit board (PCB) or other integration substrate by surface mount technology.
摘要翻译：本公开提供了用于集成电路（IC）和机电系统（EMS）装置的玻璃封装的系统，方法和装置。在一个方面，玻璃包装可以包括玻璃基板，玻璃盖和一个或多个封装在玻璃基板和盖玻璃之间的装置。覆盖玻璃可以用诸如环氧树脂或金属粘结环的粘合剂结合到玻璃基板上。玻璃包装还可以包括在一个或多个装置和包装外部之间的一个或多个信号传输路径。在一些实施方案中，包括EMS和/或IC器件的玻璃封装被配置为通过表面贴装技术直接附接到印刷电路板（PCB）或其它集成基板。

6. 发明申请

US20080241482A1 RHODIUM ELECTROPLATED STRUCTURES AND METHODS OF MAKING SAME 审中-公开
标题翻译： RHODIUM电镀结构及其制备方法
公开(公告)号：US20080241482A1
公开(公告)日：2008-10-02
申请号：US12026471
申请日：2008-02-05
申请人： Michael Armstrong , Gayle Herman , Greg Omweg , Ravindra V. Shenoy
发明人： Michael Armstrong , Gayle Herman , Greg Omweg , Ravindra V. Shenoy
IPC分类号： B32B3/00
CPC分类号： C25D3/54 , Y10T428/12 , Y10T428/24612 , Y10T428/265
摘要： A halide based stress reducing agent is added to the bath of a rhodium plating solution. The stress reducing agent reduces stress in the plated rhodium, increasing the thickness of the rhodium that can be plated without cracking. In addition, the stress reducing agent does not appreciably decrease the wear resistance or hardness of the plated rhodium.
摘要翻译：将卤化物基应力降低剂加入到镀铑溶液的浴中。减压剂可减少电镀铑中的应力，增加可镀而不开裂的铑的厚度。此外，应力降低剂不会显着降低镀覆铑的耐磨性或硬度。

7. 发明授权

US5567304A Elimination of island formation and contact resistance problems during electroetching of blanket or patterned thin metallic layers on insulating substrate 失效
标题翻译：在绝缘衬底上的毯子或图案化的薄金属层的电蚀刻期间消除岛形成和接触电阻问题
公开(公告)号：US5567304A
公开(公告)日：1996-10-22
申请号：US367550
申请日：1995-01-03
申请人： Madhav Datta , Lubomyr T. Romankiw , Ravindra V. Shenoy
发明人： Madhav Datta , Lubomyr T. Romankiw , Ravindra V. Shenoy
IPC分类号： B23H3/00 , B23H9/06 , C25F3/14 , H05K3/07 , H05K3/08 , B23H3/02 , B23H7/18
CPC分类号： C25F3/14 , B23H3/00 , B23H9/06 , H05K3/07 , H05K3/08
摘要： In through-mask electroetching of a metal film on top of an insulating substrate, the shape of the metal film being etched is a function of the mask opening, the spacing between the openings and the thickness of the mask. An analysis of the electric field around the mask and the metal film is used to determine conditions leading to the formation of islands of unetched metal films within the openings. The analysis is then used to design the mask pattern and eliminate these islands. The increase in the ratio of the mask thickness to the opening width for eliminating the islands also lowers the undercutting of the mask. Premature stoppage of the electroetching process arising from the isolation of the sample film from the contact is also addressed. The electrical contact to the sample is made at one end and a nozzle jet of electrolyte is slowly swept from the far end of the sample towards the electrical contact. The nozzle speed is matched with the metal removal rate and the electrical contact is exposed to the electrolyte at the end of the process.
摘要翻译：在绝缘基板顶部的金属膜的通孔掩模电蚀刻中，被蚀刻的金属膜的形状是掩模开口，开口间距和掩模厚度的函数。使用掩模和金属膜周围的电场的分析来确定导致在开口内形成未蚀刻金属膜岛的条件。然后分析用于设计掩模图案并消除这些岛。掩模厚度与用于消除岛的开口宽度的比率的增加也降低了掩模的底切。也解决了从接触中分离样品膜引起的电蚀过程的过早停止。与样品的电接触在一端制成，并且电解质的喷嘴射流从样品的远端缓慢地扫过电接点。喷嘴速度与金属去除速率相匹配，并且在过程结束时电接触暴露于电解质。

8. 发明授权

US5543032A Electroetching method and apparatus 失效
标题翻译：电蚀方法和装置
公开(公告)号：US5543032A
公开(公告)日：1996-08-06
申请号：US459760
申请日：1995-06-02
申请人： Madhav Datta , Ravindra V. Shenoy
发明人： Madhav Datta , Ravindra V. Shenoy
IPC分类号： C25F3/14 , H01L21/60 , C25F7/00
CPC分类号： C25F3/14 , H01L24/11 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14
摘要： A tool and process for electroetching metal films or layers on a substrate employs a linear electrode and a linear jet of electrolyte squirted from the electrode. The electrode is slowly scanned over the film by a drive mechanism. The current is preferably intermittent. In one embodiment a single wafer surface (substrate) is inverted and the jet is scanned underneath. In another embodiment wafers are held vertically on opposite sides of a holder and two linear electrodes, oriented horizontally and on opposite sides of the holder, are scanned vertically upward at a rate such that the metal layers are completely removed in one pass. The process is especially adapted for fabricating C4 solder balls with triple seed layers of Ti--W (titanium-tungsten alloy) on a substrate, phased Cr--Cu consisting of 50% chromium (Cr) and 50% copper (Cu), and substantially pure Cu. Solder alloys are through-mask electrodeposited on the Cu layer. The seed layers conduct the plating current. During etching the seed layers are removed between the solder bumps to isolate them. The phased Cr--Cu and Cu layers are removed by a single electroetching operation in aqueous potassium sulfate and glycerol with cell voltage set to dissolve the phased layer more quickly than the Cu, avoiding excessive solder bump undercutting in the copper layer. The cell voltage may be such that the solder bump is only slightly undercut so as to form a stepped base C4 structure upon reflowing. Ti--W is removed by a chemical process.
摘要翻译：用于在基板上电蚀金属膜或层的工具和方法采用线性电极和从电极喷射的电解质的线性射流。通过驱动机构将电极缓慢扫描在膜上。电流优选是间歇的。在一个实施例中，单个晶片表面（基板）被倒置并且在下面扫描射流。在另一个实施例中，晶片垂直地保持在保持器的相对侧上，并且水平定向并且在保持器的相对侧上的两个线性电极以一定速度被垂直向上扫描，使得金属层在一次通过中完全去除。该方法特别适用于在基体上制造具有Ti-W（钛 - 钨合金）三重种子层的C4焊球，由50％铬（Cr）和50％铜（Cu）组成的相位Cr-Cu，纯铜。焊接合金是电沉积在Cu层上的通孔掩模。种子层进行电镀电流。在蚀刻期间，在焊料凸块之间移除种子层以隔离它们。通过在硫酸钾水溶液和甘油中通过单次电蚀操作除去相位的Cr-Cu和Cu层，其电池电压设置为比Cu更快地溶解相位层，避免了铜层中过多的焊料凹凸。电池电压可以使得焊料凸块仅略微下切，以便在回流时形成阶梯式基底C4结构。 Ti-W通过化学工艺除去。

9. 发明申请

US20130278610A1 TOPPED-POST DESIGNS FOR EVANESCENT-MODE ELECTROMAGNETIC-WAVE CAVITY RESONATORS 审中-公开
标题翻译：用于EVANESCENT-MODE电磁波腔谐振器的TOPPED-POST设计
公开(公告)号：US20130278610A1
公开(公告)日：2013-10-24
申请号：US13451392
申请日：2012-04-19
申请人： Philip Jason Stephanou , Sang-June Park , Ravindra V. Shenoy
发明人： Philip Jason Stephanou , Sang-June Park , Ravindra V. Shenoy
IPC分类号： G06T1/00 , H01P7/06
CPC分类号： H01P1/208 , H01P7/06
摘要： This disclosure provides implementations of electromechanical systems (EMS) resonator structures, devices, apparatus, systems, and related processes. In one aspect, a device includes an evanescent-mode electromagnetic-wave cavity resonator that includes a cavity operable to support one or more evanescent electromagnetic wave modes. The resonator includes a cavity ceiling arranged to form a volume in conjunction with the cavity. The resonator also includes a capacitive tuning structure. In some implementations, the resonator also includes a post top positioned at a distal surface of the capacitive tuning structure. In some implementations, the post top has a dimension that is larger than a corresponding dimension of the capacitive tuning structure. In some implementations, a distal surface of the post top is separated from a surface by a gap distance, a resonant electromagnetic wave mode of the cavity resonator being dependent at least partially upon the gap distance and the dimension of the post top.
摘要翻译：本公开提供了机电系统（EMS）谐振器结构，设备，装置，系统和相关过程的实现。在一个方面，一种装置包括ev逝模式电磁波谐振腔谐振器，其包括可操作以支持一个或多个ev逝电磁波模式的空腔。谐振器包括设置成与空腔结合形成体积的空腔顶板。谐振器还包括电容调谐结构。在一些实施方案中，谐振器还包括位于电容调谐结构的远端表面处的柱顶。在一些实施方案中，柱顶具有大于电容调谐结构的对应尺寸的尺寸。在一些实施方案中，柱顶部的远端表面与表面分开间隙距离，空腔谐振器的谐振电磁波模式至少部分地取决于间隙距离和柱顶的尺寸。

10. 发明申请

US20130278359A1 TWO- AND THREE-SUBSTRATE LEVEL PROCESSES FOR PRODUCING EVANESCENT MODE ELECTROMAGNETIC WAVE CAVITY RESONATORS 审中-公开
标题翻译：用于生产EVANESCENT模式电磁波腔谐振器的两基板和三基板级
公开(公告)号：US20130278359A1
公开(公告)日：2013-10-24
申请号：US13451400
申请日：2012-04-19
申请人： Philip Jason Stephanou , Sang-June Park , Ravindra V. Shenoy
发明人： Philip Jason Stephanou , Sang-June Park , Ravindra V. Shenoy
IPC分类号： H01P7/06 , H01P11/00 , H01L41/22
CPC分类号： H01P1/2088 , H01P7/065 , Y10T29/42 , Y10T29/4902
摘要： This disclosure provides implementations of electromechanical systems (EMS) resonator structures, devices, apparatus, systems, and related processes. In one aspect, a method includes providing a first substrate and a second substrate. In some implementations, the first substrate includes a cavity ceiling, an array of dielectric spacers, and an assembly platform arranged adjacent the array of dielectric spacers opposite the cavity ceiling surface. The assembly platform includes a plurality of post tops. In some implementations, the second substrate has an array of cavities and an array of resonator posts. In some implementations, the method includes mating the first substrate with the second substrate, connecting the post tops with the posts to form an array that includes a plurality of evanescent-mode electromagnetic wave cavity resonators, wherein at least a statically-defined magnitude of a gap distance between the distal surface of each post top and the cavity ceiling is defined by the dielectric spacers.
摘要翻译：本公开提供了机电系统（EMS）谐振器结构，设备，装置，系统和相关过程的实现。一方面，一种方法包括提供第一基底和第二基底。在一些实施方案中，第一衬底包括空腔顶板，电介质间隔件的阵列以及与腔体顶表面相对的电介质隔片阵列附近布置的组装平台。组装平台包括多个柱顶。在一些实施方案中，第二衬底具有空腔阵列和谐振器柱阵列。在一些实施方式中，该方法包括将第一衬底与第二衬底配合，将柱顶与柱连接以形成包括多个渐逝模式电磁波腔共振器的阵列，其中至少一个静态限定的量级每个柱顶的远端表面和腔顶之间的间隙距离由介电间隔物限定。

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