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1. 发明授权

US07698508B2 System and method for reducing unnecessary cache operations 失效
标题翻译：减少不必要的缓存操作的系统和方法
公开(公告)号：US07698508B2
公开(公告)日：2010-04-13
申请号：US11674960
申请日：2007-02-14
申请人： Ramakrishnan Rajamony , Hazim Shafi , William Evan Speight , Lixin Zhang
发明人： Ramakrishnan Rajamony , Hazim Shafi , William Evan Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/0817
摘要： A system and method for cache management in a data processing system. The data processing system includes a processor and a memory hierarchy. The memory hierarchy includes at least an upper memory cache, at least a lower memory cache, and a write-back data structure. In response to replacing data from the upper memory cache, the upper memory cache examines the write-back data structure to determine whether or not the data is present in the lower memory cache. If the data is present in the lower memory cache, the data is replaced in the upper memory cache without casting out the data to the lower memory cache.
摘要翻译：一种用于数据处理系统中缓存管理的系统和方法。数据处理系统包括处理器和存储器层级。存储器层级至少包括上部存储器高速缓存，至少下部存储器高速缓存和回写数据结构。响应于从上部存储器高速缓存替换数据，上部存储器高速缓存检查回写数据结构以确定数据是否存在于下部存储器高速缓存中。如果数据存在于较低存储器高速缓存中，则数据将在上部存储器高速缓存中替换，而不会将数据丢弃到较低的内存高速缓存。

2. 发明申请

US20070136535A1 System and Method for Reducing Unnecessary Cache Operations 失效
标题翻译：减少不必要的缓存操作的系统和方法
公开(公告)号：US20070136535A1
公开(公告)日：2007-06-14
申请号：US11674960
申请日：2007-02-14
申请人： Ramakrishnan Rajamony , Hazim Shafi , William Speight , Lixin Zhang
发明人： Ramakrishnan Rajamony , Hazim Shafi , William Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/0817
摘要： A system and method for cache management in a data processing system. The data processing system includes a processor and a memory hierarchy. The memory hierarchy includes at least an upper memory cache, at least a lower memory cache, and a write-back data structure. In response to replacing data from the upper memory cache, the upper memory cache examines the write-back data structure to determine whether or not the data is present in the lower memory cache. If the data is present in the lower memory cache, the data is replaced in the upper memory cache without casting out the data to the lower memory cache.
摘要翻译：一种用于数据处理系统中缓存管理的系统和方法。数据处理系统包括处理器和存储器层级。存储器层级至少包括上部存储器高速缓存，至少下部存储器高速缓存和回写数据结构。响应于从上部存储器高速缓存替换数据，上部存储器高速缓存检查回写数据结构以确定数据是否存在于下部存储器高速缓存中。如果数据存在于较低存储器高速缓存中，则数据将在上部存储器高速缓存中替换，而不会将数据丢弃到较低的内存高速缓存。

3. 发明申请

US20060277366A1 System and method of managing cache hierarchies with adaptive mechanisms 失效
标题翻译：用自适应机制管理缓存层次的系统和方法
公开(公告)号：US20060277366A1
公开(公告)日：2006-12-07
申请号：US11143328
申请日：2005-06-02
申请人： Ramakrishnan Rajamony , Hazim Shafi , William Speight , Lixin Zhang
发明人： Ramakrishnan Rajamony , Hazim Shafi , William Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0817 , G06F12/0822
摘要： A system and method of managing cache hierarchies with adaptive mechanisms. A preferred embodiment of the present invention includes, in response to selecting a data block for eviction from a memory cache (the source cache) out of a collection of memory caches, examining a data structure to determine whether an entry exists that indicates that the data block has been evicted from the source memory cache, or another peer cache, to a slower cache or memory and subsequently retrieved from the slower cache or memory into the source memory cache or other peer cache. Also, a preferred embodiment of the present invention includes, in response to determining the entry exists in the data structure, selecting a peer memory cache out of the collection of memory caches at the same level in the hierarchy to receive the data block from the source memory cache upon eviction.
摘要翻译：一种使用自适应机制管理缓存层次结构的系统和方法。本发明的优选实施例包括响应于从存储器高速缓存的集合中的存储器高速缓存（源高速缓存）中选择用于逐出的数据块，检查数据结构以确定是否存在指示数据块已经从源存储器高速缓存或另一个对等缓存驱逐到较慢的高速缓存或存储器，并随后从较慢的高速缓存或存储器检索到源存储器高速缓存或其他对等高速缓存。此外，本发明的优选实施例包括响应于确定条目存在于数据结构中，从层级中的相同级别的存储器高速缓存的集合中选择对等存储器高速缓存以从源接收数据块内存缓存被驱逐。

4. 发明申请

US20070283101A1 Just-In-Time Prefetching 失效
标题翻译：即时预取
公开(公告)号：US20070283101A1
公开(公告)日：2007-12-06
申请号：US11422459
申请日：2006-06-06
申请人： Wael R. El-Essawy , Ramakrishnan Rajamony , Hazim Shafi , William E. Speight , Lixin Zhang
发明人： Wael R. El-Essawy , Ramakrishnan Rajamony , Hazim Shafi , William E. Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/0862
摘要： A method and an apparatus for performing just-in-time data prefetching within a data processing system comprising a processor, a cache or prefetch buffer, and at least one memory storage device. The apparatus comprises a prefetch engine having means for issuing a data prefetch request for prefetching a data cache line from the memory storage device for utilization by the processor. The apparatus further comprises logic/utility for dynamically adjusting a prefetch distance between issuance by the prefetch engine of the data prefetch request and issuance by the processor of a demand (load request) targeting the data/cache line being returned by the data prefetch request, so that a next data prefetch request for a subsequent cache line completes the return of the data/cache line at effectively the same time that a demand for that subsequent data/cache line is issued by the processor.
摘要翻译：一种用于在包括处理器，高速缓存或预取缓冲器的数据处理系统中执行即时数据预取的方法和装置，以及至少一个存储器存储装置。该装置包括预取引擎，具有用于发出数据预取请求的装置，用于从存储器存储装置预取数据高速缓存行以供处理器利用。该装置还包括逻辑/实用程序，用于动态地调整数据预取请求的预取引擎的发布之间的预取距离，并且由处理器发出针对由数据预取请求返回的数据/高速缓存线的需求（加载请求）使得对于后续高速缓存行的下一个数据预取请求在处理器发出对后续数据/高速缓存行的请求的同时有效地完成数据/高速缓存行的返回。

5. 发明授权

US07281092B2 System and method of managing cache hierarchies with adaptive mechanisms 失效
标题翻译：用自适应机制管理缓存层次的系统和方法
公开(公告)号：US07281092B2
公开(公告)日：2007-10-09
申请号：US11143328
申请日：2005-06-02
申请人： Ramakrishnan Rajamony , Hazim Shafi , William E. Speight , Lixin Zhang
发明人： Ramakrishnan Rajamony , Hazim Shafi , William E. Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0817 , G06F12/0822
摘要： A system and method of managing cache hierarchies with adaptive mechanisms. A preferred embodiment of the present invention includes, in response to selecting a data block for eviction from a memory cache (the source cache) out of a collection of memory caches, examining a data structure to determine whether an entry exists that indicates that the data block has been evicted from the source memory cache, or another peer cache, to a slower cache or memory and subsequently retrieved from the slower cache or memory into the source memory cache or other peer cache. Also, a preferred embodiment of the present invention includes, in response to determining the entry exists in the data structure, selecting a peer memory cache out of the collection of memory caches at the same level in the hierarchy to receive the data block from the source memory cache upon eviction.
摘要翻译：一种使用自适应机制管理缓存层次结构的系统和方法。本发明的优选实施例包括响应于从存储器高速缓存的集合中的存储器高速缓存（源高速缓存）中选择用于逐出的数据块，检查数据结构以确定是否存在指示数据块已经从源存储器高速缓存或另一个对等缓存驱逐到较慢的高速缓存或存储器，并随后从较慢的高速缓存或存储器检索到源存储器高速缓存或其他对等高速缓存。此外，本发明的优选实施例包括响应于确定条目存在于数据结构中，从层级中的相同级别的存储器高速缓存的集合中选择对等存储器高速缓存以从源接收数据块内存缓存被驱逐。

6. 发明申请

US20060155934A1 System and method for reducing unnecessary cache operations 审中-公开
标题翻译：减少不必要的缓存操作的系统和方法
公开(公告)号：US20060155934A1
公开(公告)日：2006-07-13
申请号：US11032875
申请日：2005-01-11
申请人： Ramakrishnan Rajamony , Hazim Shafi , William Speight , Lixin Zhang
发明人： Ramakrishnan Rajamony , Hazim Shafi , William Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/0817
摘要： A system and method for cache management in a data processing system. The data processing system includes a processor and a memory hierarchy. The memory hierarchy includes at least an upper memory cache, at least a lower memory cache, and a write-back data structure. In response to replacing data from the upper memory cache, the upper memory cache examines the write-back data structure to determine whether or not the data is present in the lower memory cache. If the data is present in the lower memory cache, the data is replaced in the upper memory cache without casting out the data to the lower memory cache.
摘要翻译：一种用于数据处理系统中缓存管理的系统和方法。数据处理系统包括处理器和存储器层级。存储器层级至少包括上部存储器高速缓存，至少下部存储器高速缓存和回写数据结构。响应于从上部存储器高速缓存替换数据，上部存储器高速缓存检查回写数据结构以确定数据是否存在于下部存储器高速缓存中。如果数据存在于较低存储器高速缓存中，则数据将在上部存储器高速缓存中替换，而不会将数据丢弃到较低的内存高速缓存。

7. 发明授权

US07657729B2 Efficient multiple-table reference prediction mechanism 失效
标题翻译：高效多表参考预测机制
公开(公告)号：US07657729B2
公开(公告)日：2010-02-02
申请号：US11457178
申请日：2006-07-13
申请人： Wael R. El-Essawy , Ramakrishnan Rajamony , Hazim Shafi , William E. Speight , Lixin Zhang
发明人： Wael R. El-Essawy , Ramakrishnan Rajamony , Hazim Shafi , William E. Speight , Lixin Zhang
IPC分类号： G06F9/00
CPC分类号： G06F12/0862 , G06F9/3455 , G06F9/383 , G06F9/3832 , G06F12/0897 , G06F2212/6026
摘要： A method and an apparatus for enabling a prefetch engine to detect and support hardware prefetching with different streams in received accesses. Multiple (simple) history tables are provided within (or associated with) the prefetch engine. Each of the multiple tables is utilized to detect different access patterns. The tables are indexed by different parts of the address and are accessed in a preset order to reduce the interference between different patterns. When an address does not fit the patterns of a first table, the address is passed to the next table to be checked for a match of different patterns. In this manner, different patterns may be detected at different tables within a single prefetch engine.
摘要翻译：一种用于使预取引擎能够在接收的访问中检测和支持不同流的硬件预取的方法和装置。在预取引擎（或与其相关联）中提供了多个（简单）历史表。多个表中的每一个用于检测不同的访问模式。这些表由地址的不同部分索引，并以预设顺序访问，以减少不同模式之间的干扰。当地址不符合第一个表的模式时，该地址将传递给下一个表，以便检查不同模式的匹配。以这种方式，可以在单个预取引擎内的不同表处检测不同的模式。

8. 发明授权

US07487297B2 Dynamically adjusting a pre-fetch distance to enable just-in-time prefetching within a processing system 失效
标题翻译：动态调整预取距离，以便在处理系统中实现即时预取
公开(公告)号：US07487297B2
公开(公告)日：2009-02-03
申请号：US11422459
申请日：2006-06-06
申请人： Wael R. El-Essawy , Ramakrishnan Rajamony , Hazim Shafi , William E. Speight , Lixin Zhang
发明人： Wael R. El-Essawy , Ramakrishnan Rajamony , Hazim Shafi , William E. Speight , Lixin Zhang
IPC分类号： G06F13/00
CPC分类号： G06F12/0862
摘要： A method and an apparatus for performing just-in-time data prefetching within a data processing system comprising a processor, a cache or prefetch buffer, and at least one memory storage device. The apparatus comprises a prefetch engine having means for issuing a data prefetch request for prefetching a data cache line from the memory storage device for utilization by the processor. The apparatus further comprises logic/utility for dynamically adjusting a prefetch distance between issuance by the prefetch engine of the data prefetch request and issuance by the processor of a demand (load request) targeting the data/cache line being returned by the data prefetch request, so that a next data prefetch request for a subsequent cache line completes the return of the data/cache line at effectively the same time that a demand for that subsequent data/cache line is issued by the processor.
摘要翻译：一种用于在包括处理器，高速缓存或预取缓冲器的数据处理系统中执行即时数据预取的方法和装置，以及至少一个存储器存储装置。该装置包括预取引擎，具有用于发出数据预取请求的装置，用于从存储器存储装置预取数据高速缓存行以供处理器利用。该装置还包括逻辑/实用程序，用于动态地调整数据预取请求的预取引擎的发布之间的预取距离，并且由处理器发出针对由数据预取请求返回的数据/高速缓存线的需求（加载请求）使得对于后续高速缓存行的下一个数据预取请求在处理器发出对后续数据/高速缓存行的请求的同时有效地完成数据/高速缓存行的返回。

9. 发明申请

US20080016330A1 Efficient Multiple-Table Reference Prediction Mechanism 失效
标题翻译：高效多表参考预测机制
公开(公告)号：US20080016330A1
公开(公告)日：2008-01-17
申请号：US11457178
申请日：2006-07-13
申请人： Wael R. El-Essawy , Ramakrishnan Rajamony , Hazim Shafi , William E. Speight , Lixin Zhang
发明人： Wael R. El-Essawy , Ramakrishnan Rajamony , Hazim Shafi , William E. Speight , Lixin Zhang
IPC分类号： G06F9/44
CPC分类号： G06F12/0862 , G06F9/3455 , G06F9/383 , G06F9/3832 , G06F12/0897 , G06F2212/6026
摘要： A method and an apparatus for enabling a prefetch engine to detect and support hardware prefetching with different streams in received accesses. Multiple (simple) history tables are provided within (or associated with) the prefetch engine. Each of the multiple tables is utilized to detect different access patterns. The tables are indexed by different parts of the address and are accessed in a preset order to reduce the interference between different patterns. When an address does not fit the patterns of a first table, the address is passed to the next table to be checked for a match of different patterns. In this manner, different patterns may be detected at different tables within a single prefetch engine.
摘要翻译：一种用于使预取引擎能够在接收的访问中检测和支持不同流的硬件预取的方法和装置。在预取引擎（或与其相关联）中提供了多个（简单）历史表。多个表中的每一个用于检测不同的访问模式。这些表由地址的不同部分索引，并以预设顺序访问，以减少不同模式之间的干扰。当地址不符合第一个表的模式时，该地址将传递给下一个表，以便检查不同模式的匹配。以这种方式，可以在单个预取引擎内的不同表处检测不同的模式。

10. 发明申请

US20120198459A1 ASSIST THREAD FOR INJECTING CACHE MEMORY IN A MICROPROCESSOR 有权
标题翻译：在微处理器中注入高速缓存存储器的辅助螺纹
公开(公告)号：US20120198459A1
公开(公告)日：2012-08-02
申请号：US13434423
申请日：2012-03-29
申请人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
发明人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
IPC分类号： G06F9/46 , G06F12/08
CPC分类号： G06F9/383 , G06F9/3851 , G06F9/4881 , G06F12/0862
摘要： A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.
摘要翻译：数据处理系统包括具有访问多级缓存存储器的微处理器。微处理器执行从源代码对象编译的主线程。该系统包括用于执行也源自源代码对象的辅助线程的处理器。辅助线程包括主线程的存储器参考指令和仅解析存储器参考指令所需的算术指令。配置成与对应的执行线程一起调度辅助线程的调度器被配置为通过诸如主处理器周期的数量或代码指令的数量的可确定的阈值来执行执行线程之前的辅助线程。辅助线程可以在主处理器或专用辅助处理器中执行，该处理器直接对下一级高速缓冲存储器元件之一进行存储器访问。

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