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1. 发明授权

US5942780A Integrated circuit having, and process providing, different oxide layer thicknesses on a substrate 失效
标题翻译：具有在衬底上提供不同氧化层厚度的工艺的集成电路
公开(公告)号：US5942780A
公开(公告)日：1999-08-24
申请号：US689523
申请日：1996-08-09
申请人： Radu M. Barsan , Xiao-Yu Li , Sunil Mehta
发明人： Radu M. Barsan , Xiao-Yu Li , Sunil Mehta
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11558
摘要： An integrated circuit ("IC") having three different oxide layer thicknesses and a process for manufacturing the IC using a single oxide growth step is provided. A first region is formed on a substrate surface with oxidation enhancing properties. A second region is formed on the substrate surface with a dose of nitrogen that retards oxidation. An oxide layer is grown from the first and the second regions and a third region of the substrate such that the first, second, and third regions yield a first oxide layer for the capacitor, a second oxide layer for the read transistor and a third oxide layer for the write transistor.
摘要翻译：提供具有三种不同氧化物层厚度的集成电路（“IC”）和使用单一氧化物生长步骤制造该IC的工艺。第一区域形成在具有氧化增强性质的基板表面上。在衬底表面上形成一个第二区域，其中氮气的量减少了氧化。从基板的第一和第二区域和第三区域生长氧化物层，使得第一，第二和第三区域产生用于电容器的第一氧化物层，用于读取晶体管的第二氧化物层和第三氧化物层写入晶体管层。

2. 发明授权

US5672521A Method of forming multiple gate oxide thicknesses on a wafer substrate 失效
标题翻译：在晶圆基板上形成多个栅极氧化物厚度的方法
公开(公告)号：US5672521A
公开(公告)日：1997-09-30
申请号：US561306
申请日：1995-11-21
申请人： Radu M. Barsan , Xiao-Yu Li , Sunil Mehta
发明人： Radu M. Barsan , Xiao-Yu Li , Sunil Mehta
IPC分类号： H01L21/28 , H01L21/8234 , H01L29/51 , H01L21/266
CPC分类号： H01L21/28185 , H01L21/2822 , H01L21/823462 , H01L29/518 , H01L21/28211 , Y10S148/116 , Y10S148/163 , Y10S438/981
摘要： An integrated circuit device and manufacturing process wherein a first region is formed in a substrate with a dopant that enhances oxide formation and a second region is formed in the substrate with a dose of nitrogen that retards oxide formation. An oxide layer is grown over the first and the second regions and over a third region of the substrate such that the first, second, and third regions yield differing thicknesses of the oxide layer.
摘要翻译：一种集成电路器件和制造方法，其中第一区域形成在具有增强氧化物形成的掺杂剂的衬底中，并且在衬底中形成具有延迟氧化物形成的氮的剂量的第二区域。在衬底的第一和第二区域和第三区域上生长氧化物层，使得第一，第二和第三区域产生不同厚度的氧化物层。

3. 发明授权

US5885904A Method to incorporate, and a device having, oxide enhancement dopants using gas immersion laser doping (GILD) for selectively growing an oxide layer 失效
标题翻译：使用气体浸渍激光掺杂（GILD）来选择生长氧化物层的掺入方法和具有氧化物增强掺杂剂的器件
公开(公告)号：US5885904A
公开(公告)日：1999-03-23
申请号：US799235
申请日：1997-02-14
申请人： Sunil Mehta , Emi Ishida , Xiao-Yu Li
发明人： Sunil Mehta , Emi Ishida , Xiao-Yu Li
IPC分类号： H01L21/311 , H01L21/316 , H01L21/461 , H01L21/31
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/0231 , H01L21/02312 , H01L21/31138 , H01L21/31144 , H01L21/31662
摘要： A method for forming a uniform and reliable oxide layer on the surface of a semiconductor substrate using projection gas immersion laser doping (P-GILD) is provided. A semiconductor substrate is immersed in an oxide enhancing compound containing atmosphere. The oxide enhancing compound containing atmosphere may include phosphorus, arsenic, boron or an equivalent. A 308 nm excimer laser is then applied to a portion of the substrate to induce incorporation of the oxide enhancing compound into a portion of the substrate. The deposition depth is dependent upon the strength of the laser energy directed at the surface of the substrate. A uniform and reliable oxide layer is then formed on the surface of the substrate by heating the substrate. The laser may be applied with a reflective reticle or mask formed on the substrate. An E.sup.2 PROM memory cell having a program junction region in a silicon substrate is also provided. An oxide layer is positioned between a program junction and a floating gate. The oxide layer is formed by a single or multiple thermal oxidation step(s) to have at least a first oxide thickness due to a GILD oxide enhancing compound underlying a region of the oxide having at least the first oxide thickness.
摘要翻译：提供了使用投影气体浸渍激光掺杂（P-GILD）在半导体衬底的表面上形成均匀且可靠的氧化物层的方法。将半导体衬底浸入含氧化物增强化合物的气氛中。含氧化物增强化合物的气氛可以包括磷，砷，硼或等价物。然后将308nm准分子激光器施加到衬底的一部分以诱导氧化物增强化合物掺入衬底的一部分中。沉积深度取决于指向衬底表面的激光能量的强度。然后通过加热衬底在衬底的表面上形成均匀且可靠的氧化物层。可以在基板上形成反射型掩模版或掩模来施加激光。还提供了具有硅衬底中的程序接合区的E2PROM存储单元。氧化物层位于程序结和浮动栅之间。通过单个或多个热氧化步骤形成氧化物层，以至少具有第一氧化物厚度，这是由于至少具有第一氧化物厚度的氧化物区域下面的GILD氧化物增强化合物。

4. 发明授权

US5841701A Method of charging and discharging floating gage transistors to reduce leakage current 失效
标题翻译：浮栅晶体管充放电方法，以减少漏电流
公开(公告)号：US5841701A
公开(公告)日：1998-11-24
申请号：US785096
申请日：1997-01-21
申请人： Xiao-Yu Li , Radu Barsan , Sunil Mehta
发明人： Xiao-Yu Li , Radu Barsan , Sunil Mehta
IPC分类号： G11C16/10 , G11C16/12 , G11C11/34
CPC分类号： G11C16/12 , G11C16/10
摘要： A method for improving the endurance and reliability of a floating gate transistor often used in memory applications by controlling the electric field induced across the tunnel oxide region of the floating gate when discharging electrons from the floating gate. The method comprises the steps of: allowing the active region to ground; and applying a program voltage to the floating gate over a period of time and at a magnitude, by increasing the voltage from zero volts to the magnitude over a first period of at least 1 millisecond (ms.), maintaining the voltage at the magnitude for a second period of around 10 ms.-100 ms. sufficient to place charge on the floating gate, and decreasing the voltage from the magnitude during a third period to zero volts in not greater than 50 microseconds.
摘要翻译：常用于存储器应用中的浮栅晶体管的耐久性和可靠性通过控制在浮置栅极放电电子时跨越浮栅的隧道氧化物区域感应的电场的方法。该方法包括以下步骤：允许有源区域接地; 并且通过在至少1毫秒（ms）的第一周期上将电压从零伏特增加到幅度，在一段时间和幅度上将编程电压施加到浮动栅极，将电压保持在大小为大约10 ms.-100 ms的第二个周期。足以在浮动栅极上放置电荷，并将电压从第三周期内的幅度降低到零伏特以不大于50微秒。

5. 发明授权

US5795627A Method for annealing damaged semiconductor regions allowing for enhanced oxide growth 失效
标题翻译：用于退火损坏的半导体区域以允许增强的氧化物生长的方法
公开(公告)号：US5795627A
公开(公告)日：1998-08-18
申请号：US799236
申请日：1997-02-14
申请人： Sunil Mehta , Emi Ishida , Xiao-Yu Li
发明人： Sunil Mehta , Emi Ishida , Xiao-Yu Li
IPC分类号： H01L21/316 , H01L21/762 , H01L27/115 , C23C14/04
CPC分类号： H01L21/76213 , H01L21/316 , H01L27/115
摘要： A method of forming an oxide enhancing region, such as phosphorus, in a semiconductor substrate with minimal damage is provided. The method includes the steps of forming an oxide enhancing region in the semiconductor substrate to a depth below the semiconductor substrate. A 308 nm excimer laser is then applied to the oxide enhancing region in order to reduce the damage caused by forming the oxide enhancing region. A uniform and reliable oxide layer is then formed on the surface of the substrate over the damage reduced oxide enhancing region.
摘要翻译：提供了在具有最小损伤的半导体衬底中形成诸如磷的氧化物增强区域的方法。该方法包括以下步骤：在半导体衬底中形成半导体衬底下方的深度的氧化物增强区。然后将308nm准分子激光器施加到氧化物增强区域，以便减少由形成氧化物增强区域引起的损伤。然后在损伤还原氧化物增强区域上的衬底的表面上形成均匀且可靠的氧化物层。

6. 发明申请

US20140204824A1 MULTI-GROUP COMMUNICATIONS AND RELATED DEVICES 有权
标题翻译：多组通信和相关设备
公开(公告)号：US20140204824A1
公开(公告)日：2014-07-24
申请号：US14009008
申请日：2011-03-30
申请人： Liang Chen , Xiao-Yu Li , Jason Xu
发明人： Liang Chen , Xiao-Yu Li , Jason Xu
IPC分类号： H04W4/06
CPC分类号： H04W4/06 , H04W4/08
摘要： Methods and apparatus are provided for communicating a message to multiple radio groups (102, 104). An exemplary method (300) involves configuring, by an initiating radio device (120), a header portion of a message (308) for a multi-group communication session including the plurality of radio groups (102, 104) and transmitting the message (310). Each respective radio device (110) of each respective radio group (102, 104) is configured to provide output (408) corresponding to a content portion of the message in response to identifying its own radio group (406) in the header portion of the message (404).
摘要翻译：提供了用于将消息传送到多个无线电组（102,104）的方法和装置。示例性方法（300）涉及通过发起无线电设备（120）配置用于包括多个无线电组（102,104）的多组通信会话的消息（308）的报头部分，并发送消息（ 310）。每个相应无线电组（102,104）的每个相应无线电设备（110）被配置为响应于在其中的标题部分中识别其自己的无线电组（406）来提供与消息的内容部分相对应的输出（408）消息（404）。

7. 发明授权

US08402412B1 Increasing circuit speed and reducing circuit leakage by utilizing a local surface temperature effect 有权
标题翻译：通过利用局部表面温度效应提高电路速度并减少电路漏电
公开(公告)号：US08402412B1
公开(公告)日：2013-03-19
申请号：US13112896
申请日：2011-05-20
申请人： Cinti X. Chen , Xiao-Yu Li , Joe W. Zhao
发明人： Cinti X. Chen , Xiao-Yu Li , Joe W. Zhao
IPC分类号： G06F17/50
CPC分类号： H01L27/0251 , G06F17/5072 , H01L27/0207 , H01L27/11807 , H01L29/0692
摘要： An embodiment of an integrated circuit is disclosed. For this embodiment, the integrated circuit includes circuit blocks. At least one transistor of a circuit block of the circuit blocks includes a portion of a semiconductor substrate having a diffusion layer. The circuit block has a relatively high diffusion pattern density as compared with others of the circuit blocks. The diffusion layer has an exposed surface active area constrained responsive to a design rule. The design rule is to limit to a maximum amount the surface active area in order to improve at least one parameter of the at least one transistor selected from a group consisting of an increase in switching speed and a decrease in leakage current of the at least one transistor of the circuit block having the relatively high diffusion pattern density.
摘要翻译：公开了一种集成电路的实施例。对于该实施例，集成电路包括电路块。电路块的电路块的至少一个晶体管包括具有扩散层的半导体衬底的一部分。与其他电路块相比，电路块具有相对较高的扩散图案密度。扩散层具有受到响应于设计规则约束的暴露表面有源面积的限制。设计规则是限制到表面有效面积的最大量，以便改进至少一个晶体管的至少一个参数，该至少一个晶体管选自由开关速度的增加和至少一个的开关速度的降低引起的具有较高扩散图案密度的电路块的晶体管。

8. 发明授权

US06172392B2 Boron doped silicon capacitor plate 失效
标题翻译：硼掺杂硅电容器板
公开(公告)号：US06172392B2
公开(公告)日：2001-01-09
申请号：US09280887
申请日：1999-03-29
申请人： Christopher O. Schmidt , Sunil D. Mehta , Xiao-Yu Li
发明人： Christopher O. Schmidt , Sunil D. Mehta , Xiao-Yu Li
IPC分类号： H01L29788
CPC分类号： H01L27/11558 , H01L27/115 , H01L27/11521
摘要： A nonvolatile memory device utilizing a program junction region of a p-type impurity and oxide grown thereon. In one aspect, the device comprises a programming structure and a program junction separated from said programming structure by a field oxide region. A program junction oxide layer overlies said program junction region. A floating gate is provided over the oxide which covers said programming structure, said program junction oxide layer, and in some embodiments the gate oxide of a sense transistor.
摘要翻译：一种利用p型杂质的程序结区域和在其上生长的氧化物的非易失性存储器件。一方面，该装置包括编程结构和通过场氧化物区与所述编程结构分离的程序结。程序结氧化物层覆盖所述程序结区域。在覆盖所述编程结构，所述程序结氧化物层的氧化物上提供浮置栅极，并且在一些实施例中，提供感测晶体管的栅极氧化物。

9. 发明授权

US6075293A Semiconductor device having a multi-layer metal interconnect structure 有权
标题翻译：具有多层金属互连结构的半导体器件
公开(公告)号：US6075293A
公开(公告)日：2000-06-13
申请号：US263412
申请日：1999-03-05
申请人： Xiao-Yu Li , Sunil D. Mehta , Van H. Pham , Amit P. Marathe
发明人： Xiao-Yu Li , Sunil D. Mehta , Van H. Pham , Amit P. Marathe
IPC分类号： H01L23/532 , H01L23/48
CPC分类号： H01L23/53223 , H01L2924/0002
摘要： A multi-level metal interconnect structure in a semiconductor device includes a plurality of overlying metal layers separated by ILD layers and electrically connected by filled vias in the ILD layers. Each metal layer includes a relatively thick antireflective layer for improved electromigration resistance. Each metal layer also includes a metal lining layer and a metal interconnect layer overlying the metal lining layer. Enhanced electromigration resistance is obtained by forming the antireflective layer to a thickness of no less than the thickness of the metal lining layer. In a preferred embodiment of the invention, the antireflective layer has a thickness of about 1000 angstroms.
摘要翻译：半导体器件中的多级金属互连结构包括由ILD层分离并由ILD层中的填充通孔电连接的多个上覆金属层。每个金属层包括相对较厚的抗反射层，用于改善电迁移阻力。每个金属层还包括覆盖金属衬里层的金属衬里层和金属互连层。通过将抗反射层形成为不小于金属衬里层的厚度的厚度来获得增强的电迁移电阻。在本发明的优选实施例中，抗反射层的厚度为约1000埃。

10. 发明授权

US06326663B1 Avalanche injection EEPROM memory cell with P-type control gate 失效
标题翻译：雪崩注入EEPROM存储单元，带P型控制门
公开(公告)号：US06326663B1
公开(公告)日：2001-12-04
申请号：US09277441
申请日：1999-03-26
申请人： Xiao-Yu Li , Steven J. Fong , Sunil D. Mehta
发明人： Xiao-Yu Li , Steven J. Fong , Sunil D. Mehta
IPC分类号： H01L29788
CPC分类号： H01L27/11517 , H01L27/115
摘要： A non-volatile memory cell, comprising a semiconductor substrate having a first conductivity type. A control region is formed of said first conductivity type in the substrate and a control region oxide formed over the control region. The cell includes a program element having a first active region of a second conductivity type formed in said substrate, a doped or implanted region adjacent to said first active region, and a gate oxide overlying at least the channel region. An active region oxide covers a portion of the first active region. A floating gate is formed over said semiconductor substrate on said active region oxide and said control region oxide.
摘要翻译：一种非易失性存储单元，包括具有第一导电类型的半导体衬底。控制区域由衬底中的所述第一导电类型形成，并且在控制区域上形成控制区氧化物。单元包括具有形成在所述衬底中的第二导电类型的第一有源区，与所述第一有源区相邻的掺杂或注入区以及覆盖至少沟道区的栅极氧化物的程序元件。有源区氧化物覆盖第一有源区的一部分。在所述有源区氧化物和所述控制区氧化物上的所述半导体衬底上形成浮栅。

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