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1. 发明授权

US5885904A Method to incorporate, and a device having, oxide enhancement dopants using gas immersion laser doping (GILD) for selectively growing an oxide layer 失效
标题翻译：使用气体浸渍激光掺杂（GILD）来选择生长氧化物层的掺入方法和具有氧化物增强掺杂剂的器件
公开(公告)号：US5885904A
公开(公告)日：1999-03-23
申请号：US799235
申请日：1997-02-14
申请人： Sunil Mehta , Emi Ishida , Xiao-Yu Li
发明人： Sunil Mehta , Emi Ishida , Xiao-Yu Li
IPC分类号： H01L21/311 , H01L21/316 , H01L21/461 , H01L21/31
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/0231 , H01L21/02312 , H01L21/31138 , H01L21/31144 , H01L21/31662
摘要： A method for forming a uniform and reliable oxide layer on the surface of a semiconductor substrate using projection gas immersion laser doping (P-GILD) is provided. A semiconductor substrate is immersed in an oxide enhancing compound containing atmosphere. The oxide enhancing compound containing atmosphere may include phosphorus, arsenic, boron or an equivalent. A 308 nm excimer laser is then applied to a portion of the substrate to induce incorporation of the oxide enhancing compound into a portion of the substrate. The deposition depth is dependent upon the strength of the laser energy directed at the surface of the substrate. A uniform and reliable oxide layer is then formed on the surface of the substrate by heating the substrate. The laser may be applied with a reflective reticle or mask formed on the substrate. An E.sup.2 PROM memory cell having a program junction region in a silicon substrate is also provided. An oxide layer is positioned between a program junction and a floating gate. The oxide layer is formed by a single or multiple thermal oxidation step(s) to have at least a first oxide thickness due to a GILD oxide enhancing compound underlying a region of the oxide having at least the first oxide thickness.
摘要翻译：提供了使用投影气体浸渍激光掺杂（P-GILD）在半导体衬底的表面上形成均匀且可靠的氧化物层的方法。将半导体衬底浸入含氧化物增强化合物的气氛中。含氧化物增强化合物的气氛可以包括磷，砷，硼或等价物。然后将308nm准分子激光器施加到衬底的一部分以诱导氧化物增强化合物掺入衬底的一部分中。沉积深度取决于指向衬底表面的激光能量的强度。然后通过加热衬底在衬底的表面上形成均匀且可靠的氧化物层。可以在基板上形成反射型掩模版或掩模来施加激光。还提供了具有硅衬底中的程序接合区的E2PROM存储单元。氧化物层位于程序结和浮动栅之间。通过单个或多个热氧化步骤形成氧化物层，以至少具有第一氧化物厚度，这是由于至少具有第一氧化物厚度的氧化物区域下面的GILD氧化物增强化合物。

2. 发明授权

US5795627A Method for annealing damaged semiconductor regions allowing for enhanced oxide growth 失效
标题翻译：用于退火损坏的半导体区域以允许增强的氧化物生长的方法
公开(公告)号：US5795627A
公开(公告)日：1998-08-18
申请号：US799236
申请日：1997-02-14
申请人： Sunil Mehta , Emi Ishida , Xiao-Yu Li
发明人： Sunil Mehta , Emi Ishida , Xiao-Yu Li
IPC分类号： H01L21/316 , H01L21/762 , H01L27/115 , C23C14/04
CPC分类号： H01L21/76213 , H01L21/316 , H01L27/115
摘要： A method of forming an oxide enhancing region, such as phosphorus, in a semiconductor substrate with minimal damage is provided. The method includes the steps of forming an oxide enhancing region in the semiconductor substrate to a depth below the semiconductor substrate. A 308 nm excimer laser is then applied to the oxide enhancing region in order to reduce the damage caused by forming the oxide enhancing region. A uniform and reliable oxide layer is then formed on the surface of the substrate over the damage reduced oxide enhancing region.
摘要翻译：提供了在具有最小损伤的半导体衬底中形成诸如磷的氧化物增强区域的方法。该方法包括以下步骤：在半导体衬底中形成半导体衬底下方的深度的氧化物增强区。然后将308nm准分子激光器施加到氧化物增强区域，以便减少由形成氧化物增强区域引起的损伤。然后在损伤还原氧化物增强区域上的衬底的表面上形成均匀且可靠的氧化物层。

3. 发明授权

US6040019A Method of selectively annealing damaged doped regions 失效
标题翻译：选择性退火损伤掺杂区域的方法
公开(公告)号：US6040019A
公开(公告)日：2000-03-21
申请号：US799230
申请日：1997-02-14
申请人： Emi Ishida , Xiao-Yu Li , Sunil D. Mehta
发明人： Emi Ishida , Xiao-Yu Li , Sunil D. Mehta
IPC分类号： H01L21/265 , H01L21/268 , H01L21/8247 , C23C14/00 , B05D3/06 , H01L21/263
CPC分类号： H01L27/11521 , H01L21/26506 , H01L21/26513 , H01L21/268 , H01L27/11558
摘要： A method of forming a region of impurity in a semiconductor substrate with minimal damage. The method includes the steps of: forming a reaction-inhibiting impurity region in the semiconductor substrate to a depth below the semiconductor substrate; and applying laser energy to the semiconductor substrate at a sufficient magnitude to liquify the semiconductor substrate in the region.
摘要翻译：一种以最小的损伤在半导体衬底中形成杂质区域的方法。该方法包括以下步骤：在半导体衬底的深度下方形成反应抑制杂质区; 以及将激光能量以足够大的量施加到所述半导体衬底以在所述区域中液化所述半导体衬底。

4. 发明授权

US5904575A Method and apparatus incorporating nitrogen selectively for differential oxide growth 失效
标题翻译：选择性地掺入氮用于差异氧化物生长的方法和装置
公开(公告)号：US5904575A
公开(公告)日：1999-05-18
申请号：US799153
申请日：1997-02-14
申请人： Emi Ishida , Xiao-Yu Li , Sunil D. Mehta
发明人： Emi Ishida , Xiao-Yu Li , Sunil D. Mehta
IPC分类号： H01L21/265 , H01L21/266 , H01L21/316 , H01L21/8234 , H01L27/115 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/0231 , H01L21/02312 , H01L21/26506 , H01L21/266 , H01L21/31662 , H01L21/823462 , H01L27/115 , Y10S148/126 , Y10S438/981
摘要： A method for forming an oxide on the surface of a semiconductor substrate. The method includes the steps of: placing the semiconductor substrate in an atmosphere containing an atmosphere of an oxide growth inhibiting compound; applying laser energy to at least a first portion of the substrate; and forming the oxide on the surface of the substrate by heating the substrate. In a further aspect of the invention, the method comprises applying laser energy through a patterned, reflective reticle. Alternatively, prior to the step of placing, a reflective mask layer may be applied to the surface of the semiconductor substrate. In addition, the invention comprises an EEPROM memory cell having a program junction region in a semiconductor substrate. The cell comprises at least a first program junction provided in the silicon substrate and a floating gate having a portion positioned over the program junction. In addition, an oxide layer is positioned between the program junction and the floating gate, the gate oxide formed by a single thermal oxidation step to have at least a first oxide thickness and a second oxide thickness due to gas immersion laser doped nitrogen underlying a region of the oxide having said at least first oxide thickness.
摘要翻译：一种在半导体衬底的表面上形成氧化物的方法。该方法包括以下步骤：将半导体衬底放置在含有氧化物生长抑制化合物气氛的气氛中; 将激光能量施加到所述衬底的至少第一部分; 以及通过加热衬底在衬底的表面上形成氧化物。在本发明的另一方面，该方法包括通过图案化的反射光罩施加激光能量。或者，在放置步骤之前，可以将反射掩模层施加到半导体衬底的表面。此外，本发明包括一个在半导体衬底中具有编程结区的EEPROM存储单元。该单元包括设置在硅衬底中的至少第一程序段和具有位于程序结上方的部分的浮动栅极。此外，氧化物层位于程序结和浮置栅极之间，栅极氧化物通过单个热氧化步骤形成，以由于气体浸没激光掺杂氮在下面的区域具有至少第一氧化物厚度和第二氧化物厚度的具有所述至少第一氧化物厚度的氧化物。

5. 发明申请

US20070112176A1 Lipid membrane structure containing anti-mt-mmp monoclonal antibody 审中-公开
标题翻译：含有抗-mt-mmp单克隆抗体的脂质膜结构
公开(公告)号：US20070112176A1
公开(公告)日：2007-05-17
申请号：US10551780
申请日：2004-04-02
申请人： Motoharu Seiki , Ikuo Yana , Takanori Aoki , Junko Yasuda , Hiroshi Kikuchi , Emi Ishida
发明人： Motoharu Seiki , Ikuo Yana , Takanori Aoki , Junko Yasuda , Hiroshi Kikuchi , Emi Ishida
IPC分类号： A61K9/127 , C07K14/82
CPC分类号： A61K31/704 , A61K9/127 , A61K47/6871 , A61K47/6901 , A61K48/00
摘要： A lipid membrane structure containing an anti-membrane-type matrix metalloproteinase monoclonal antibody such as an anti-MT1-MMP monoclonal antibody as a component of the lipid membrane structure. Said structure can be utilized as a drug delivery system for efficiently delivering a medicinally active ingredient and/or a gene to tumor cells, neoplastic vessel and the like in which a membrane-type matrix metalloproteinase (MT-MMP) is expressed.
摘要翻译：含有抗 - 膜型基质金属蛋白酶单克隆抗体如抗MT1-MMP单克隆抗体作为脂质膜结构的组分的脂质膜结构。所述结构可用作药物递送系统，用于向其中表达膜型基质金属蛋白酶（MT-MMP）的肿瘤细胞，肿瘤血管等有效递送药物活性成分和/或基因。

6. 发明授权

US06642134B2 Semiconductor processing employing a semiconductor spacer 有权
标题翻译：采用半导体衬垫的半导体处理
公开(公告)号：US06642134B2
公开(公告)日：2003-11-04
申请号：US09401797
申请日：1999-09-22
申请人： Emi Ishida , Scott Luning
发明人： Emi Ishida , Scott Luning
IPC分类号： H01L213205
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/823864 , H01L29/6656
摘要： A semiconductor device is provided with semiconducting sidewall spacers used in the formation of source/drain regions. The semiconducting sidewall spacers also reduce the possibility of suicide shorting through shallow source/drain junctions. Embodiments include doping the semiconducting sidewall spacers so that they serve as a source of impurities for forming source/drain extensions during activation annealing.
摘要翻译：半导体器件设置有用于形成源极/漏极区域的半导体侧壁间隔物。半导体侧壁间隔物还减少了通过浅源极/漏极结的自杀性短路的可能性。实施例包括掺杂半导体侧壁间隔物，使得它们用作在激活退火期间形成源极/漏极延伸的杂质源。

7. 发明授权

US06403433B1 Source/drain doping technique for ultra-thin-body SOI MOS transistors 有权
标题翻译：超薄体SOI MOS晶体管的源极/漏极掺杂技术
公开(公告)号：US06403433B1
公开(公告)日：2002-06-11
申请号：US09397217
申请日：1999-09-16
申请人： Bin Yu , Jonathan Kluth , Emi Ishida
发明人： Bin Yu , Jonathan Kluth , Emi Ishida
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L29/78618
摘要： An ultra-large-scale integrated (ULSI) circuit includes MOSFETs on an SOI substrate. The MOSFETs include elevated source and drain regions. The elevated source and drain regions are amorphized before doping. Neutral ion species can be utilized to amorphize the elevated source and drain region. Dopants are activated in a low-temperature rapid thermal anneal process.
摘要翻译：超大规模集成（ULSI）电路包括SOI衬底上的MOSFET。 MOSFET包括升高的源极和漏极区域。在掺杂之前，升高的源极和漏极区非晶化。中性离子物质可用于使提升的源极和漏极区域非晶化。掺杂剂在低温快速热退火工艺中被激活。

8. 发明授权

US06277698B1 Method of manufacturing semiconductor devices having uniform, fully doped gate electrodes 有权
标题翻译：具有均匀的，完全掺杂的栅电极的半导体器件的制造方法
公开(公告)号：US06277698B1
公开(公告)日：2001-08-21
申请号：US09382580
申请日：1999-08-25
申请人： Emi Ishida , Dong-Hyuk Ju , David Wu
发明人： Emi Ishida , Dong-Hyuk Ju , David Wu
IPC分类号： H01L21336
CPC分类号： H01L29/66583 , H01L21/823842
摘要： A semiconductor device is provided with a gate electrode having a substantially rectangular profile by forming a dielectric film prior to depositing the gate electrode layer. The dielectric film is patterned and etched to form regions having a rectangular profile separated by open regions. A gate electrode layer is then deposited followed by planarization to form gate electrodes having a substantially rectangular profile.
摘要翻译：通过在沉积栅极电极层之前形成电介质膜，半导体器件设置有具有大致矩形轮廓的栅电极。对电介质膜进行图案化和蚀刻以形成具有由开放区域分开的矩形轮廓的区域。然后沉积栅极电极层，然后平坦化以形成具有基本上矩形轮廓的栅电极。

9. 发明授权

US6143632A Deuterium doping for hot carrier reliability improvement 失效
标题翻译：氘掺杂热载体可靠性提高
公开(公告)号：US6143632A
公开(公告)日：2000-11-07
申请号：US993049
申请日：1997-12-18
申请人： Emi Ishida , Peng Fang
发明人： Emi Ishida , Peng Fang
IPC分类号： H01L21/265 , H01L21/28 , H01L29/32 , H01L29/49 , H01L29/51 , H01L29/76
CPC分类号： H01L21/28185 , H01L21/26506 , H01L21/28176 , H01L21/28202 , H01L21/28211 , H01L29/32 , H01L29/4983 , H01L29/518
摘要： A semiconductor device having reduced hot carrier degradation is achieved by doping the semiconductor substrate and gate oxide with deuterium. A conventional semiconductor device is formed with sequentially deposited metal layers and dielectric layers and a topside protective dielectric layer deposited thereon. Deuterium is introduced to the semiconductor device by using deuterium-containing reactants in at least one of the semiconductor manufacturing steps to passivate dangling silicon bonds at the silicon/oxide interface region.
摘要翻译：具有减少的热载流子劣化的半导体器件通过用氘掺杂半导体衬底和栅极氧化物来实现。常规的半导体器件形成有顺序沉积的金属层和介电层以及沉积在其上的顶侧保护电介质层。通过在半导体制造步骤中的至少一个中使用含氘的反应物，在硅/氧化物界面区域钝化悬挂的硅键，将氘引入半导体器件。

10. 发明授权

US06472283B1 MOS transistor processing utilizing UV-nitride removable spacer and HF etch 失效
标题翻译：使用UV氮化物可移除间隔物和HF蚀刻的MOS晶体管处理
公开(公告)号：US06472283B1
公开(公告)日：2002-10-29
申请号：US09667787
申请日：2000-09-22
申请人： Emi Ishida , Srinath Krishman , Ming Yin Hao , Effiong Ibok
发明人： Emi Ishida , Srinath Krishman , Ming Yin Hao , Effiong Ibok
IPC分类号： H01L21336
CPC分类号： H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which is readily etched in its as-deposited, undensified state but difficult-to-etch in its thermally annealed, densified state. The as-deposited, undensified spacers are removed by etching with dilute aqueous HF after implantation of moderately or heavily-doped source/drain regions but prior to annealing of the implants for dopant diffusion/activation and lattice damage relaxation. Lightly- or moderately doped, shallow-depth source/drain extensions are implanted and annealed after spacer removal.
摘要翻译：亚微米尺寸的MOS和/或CMOS晶体管通过采用由诸如UV氮化物的材料制成的可移除的侧壁间隔的工艺制造，其易于以其沉积的未增稠的状态蚀刻，但在其热退火，致密化状态。通过在植入中等或重掺杂的源极/漏极区域之后但在用于掺杂剂扩散/激活和晶格损伤弛豫的植入物退火之前用稀释的HF水溶液去除沉积的未增塑的间隔物。轻微或中度掺杂的浅深度源极/漏极延伸部分在去除间隔物之后被植入和退火。

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