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热词
    • 9. 发明授权
    • Apparatus and method for address pipelining of dynamic random access
memory utilizing transparent page address latches to reduce wait states
    • 使用透明页地址锁存器来动态随机存取存储器地址流水线化以减少等待状态的装置和方法
    • US5640527A
    • 1997-06-17
    • US521259
    • 1995-08-30
    • Victor PeconeJoseph A. Vivio
    • Victor PeconeJoseph A. Vivio
    • G06F13/16G11C7/10G06F12/00G11C8/00G11C11/408
    • G06F13/161G06F13/1615G11C7/1039
    • An apparatus and method for address pipelining of a computer system that reduce the average number of wait states required to access a dynamic random access memory (DRAM) subsystem. A memory controller addresses a plurality of random access memory integrated circuits in pages of addresses wherein contiguous address pages are in different ones of the plurality of dynamic random access memory integrated circuits. Transparent latches associated with each of the different ones of the plurality of dynamic random access memory integrated circuits allow pipelining of address setups for more than one memory page at substantially the same time. The apparatus and method improve the write access times of a computer system and, when used with a computer system having address pipelining, both read and write accesses are improved because address set up latency time is reduced.
    • 一种用于减少访问动态随机存取存储器(DRAM)子系统所需的等待状态的平均数量的计算机系统的地址流水线的装置和方法。 存储器控制器在地址页中寻址多个随机存取存储器集成电路,其中连续的地址页在多个动态随机存取存储器集成电路中的不同的地址页中。 与多个动态随机存取存储器集成电路中的每个不同的动态随机存取存储器集成电路中的每一个相关联的透明锁存器允许基本上同时地对多于一个存储器页面的地址设置进行流水线化。 该装置和方法改善了计算机系统的写入访问时间,并且当与具有地址流水线的计算机系统一起使用时,读取和写入访问都被改进,因为地址设置延迟时间被减少。