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    • 1. 发明申请
    • DYNAMIC WRITE CACHE SIZE ADJUSTMENT IN RAID CONTROLLER WITH CAPACITOR BACKUP ENERGY SOURCE
    • 具有电容器备份能量源的RAID控制器中的动态写入缓存大小调整
    • US20070033433A1
    • 2007-02-08
    • US11422003
    • 2006-06-02
    • Victor PeconeYuanru Wang
    • Victor PeconeYuanru Wang
    • G06F11/00
    • G06F1/305
    • A high data availability write-caching storage controller has a volatile memory with a write cache for caching write cache data, a non-volatile memory, a capacitor pack for supplying power for backing up the write cache to the non-volatile memory in response to a loss of main power, and a CPU that determines whether reducing an operating voltage of the capacitor pack to a new value would cause the capacitor pack to be storing less energy than required for backing up the current size write cache to the non-volatile memory. If so, the CPU reduces the size of the write cache prior to reducing the operating voltage. The CPU estimates the capacity of the capacitor pack to store the required energy based on a history of operational temperature and voltage readings of the capacitor pack, such as on an accumulated normalized running time and warranted lifetime of the capacitor pack.
    • 高数据可用性写缓存存储控制器具有易失性存储器,具有用于缓存写高速缓存数据的写高速缓存,非易失性存储器,用于提供电力的电容器组,用于将写高速缓存备份到非易失性存储器,以响应于 主电源的损失以及确定是否将电容器组的工作电压降低到新值的CPU将导致电容器组比将当前大小的写高速缓存备份到非易失性存储器所需的能量少 。 如果是这样,则在降低工作电压之前,CPU会减小写入高速缓存的大小。 CPU基于电容器组的工作温度和电压读数的历史,估计电容器组的容量以存储所需的能量,例如累积的归一化运行时间和电容器组的寿命。
    • 2. 发明申请
    • STORAGE CONTROLLER SUPER CAPACITOR DYNAMIC VOLTAGE THROTTLING
    • 存储控制器超级电容器动态电压曲线
    • US20070033432A1
    • 2007-02-08
    • US11421995
    • 2006-06-02
    • Victor PeconeYuanru Wang
    • Victor PeconeYuanru Wang
    • G06F11/00
    • G06F1/305
    • A storage controller has a capacitor pack for storing energy to supply power during a main power loss, a temperature sensor that senses the capacitor pack temperature, and a CPU, which detects that the temperature of the capacitor pack has risen above a predetermined threshold while operating at a first voltage value and determines whether a projected lifetime of the capacitor pack is less than the warranted lifetime. If the projected lifetime is less than the warranted lifetime, the CPU reduces the operating voltage of the capacitor pack to a second value, in order to increase the capacitor pack lifetime. In one embodiment, the CPU reduces the voltage if an accumulated normalized running time of the capacitor pack is greater than an accumulated calendar running time. In another embodiment, the CPU reduces the voltage if a percentage capacitance drop of the capacitor pack is greater than a calendar percentage capacitance drop.
    • 存储控制器具有用于存储在主功率损耗期间供电以及感测电容器组件温度的温度传感器的能量的电容器组件,以及检测电容器组件的温度在操作时已经升高到高于预定阈值的CPU 并且确定电容器组的预计寿命是否小于保证的寿命。 如果投影寿命小于安全寿命,则CPU将电容器组的工作电压降低到第二个值,以增加电容器的使用寿命。 在一个实施例中,如果电容器组的累积归一化运行时间大于累积的日历运行时间,则CPU降低电压。 在另一实施例中,如果电容器组的百分比电容降大于日历百分比电容下降,则CPU降低电压。
    • 3. 发明申请
    • METHOD FOR ADOPTING AN ORPHAN I/O PORT IN A REDUNDANT STORAGE CONTROLLER
    • 在冗余存储控制器中采用ORPHAN I / O端口的方法
    • US20060282701A1
    • 2006-12-14
    • US11466382
    • 2006-08-22
    • Ian DaviesVictor Pecone
    • Ian DaviesVictor Pecone
    • G06F11/00
    • G06F11/2092G06F11/2005G06F11/2033
    • A method for adopting an orphaned I/O port of a storage controller is disclosed. The storage controller has first and second redundant field-replaceable units (FRU) for processing I/O requests and a third FRU having at least one I/O port for receiving the I/O requests from host computers coupled to it. Initially the first FRU processes the I/O requests received by the I/O port and the third FRU routes to the first FRU interrupt requests generated by the I/O port in response to receiving the I/O requests. Subsequently, the second FRU determines that the first FRU has failed and is no longer processing I/O requests received by the I/O port, and configures the third FRU to route the interrupt requests from the I/O port to the second FRU rather than the first FRU, in response to the determining that the first FRU has failed.
    • 公开了采用存储控制器的孤立I / O端口的方法。 存储控制器具有用于处理I / O请求的第一和第二冗余现场可替换单元(FRU)和具有至少一个I / O端口的第三FRU,用于从耦合到其的主计算机接收I / O请求。 最初,第一个FRU将I / O端口和第三个FRU路由接收的I / O请求处理为I / O端口响应于接收到I / O请求而产生的第一个FRU中断请求。 随后,第二FRU确定第一FRU失败并且不再处理由I / O端口接收的I / O请求,并且将第三FRU配置为将来自I / O端口的中断请求路由到第二FRU,而不是 比第一个FRU响应确定第一个FRU失败。
    • 5. 发明申请
    • Network storage appliance with an integrated switch
    • 具有集成开关的网络存储设备
    • US20050102549A1
    • 2005-05-12
    • US10979510
    • 2004-11-02
    • Ian DaviesGeorge KalwitzVictor Pecone
    • Ian DaviesGeorge KalwitzVictor Pecone
    • G06F7/00G06F11/00
    • G06F11/2089G06F11/201G06F11/2015G06F11/2028G06F11/2035H04L67/1097
    • A network storage appliance including one or more integrated switching devices is disclosed. The appliance includes redundant storage controllers that transfer frames of data between storage devices and host computers. The integrated switching devices include a plurality of I/O ports and a data transfer path between each of the I/O ports for providing simultaneous data transfers between multiple pairs thereof. The switches enable the appliance to simultaneously transfer frames between its I/O ports and storage device I/O ports and/or host I/O ports, thereby providing increased data transfer bandwidth over arbitrated loop configurations. Additionally, the switches are intelligent and may be programmed to achieve improved fault isolation. The appliance may also include servers that include I/O ports coupled to the switches for simultaneously transferring data with the storage controllers and/or I/O ports of devices external to the appliance.
    • 公开了一种包括一个或多个集成交换设备的网络存储设备。 该设备包括在存储设备和主机之间传输数据帧的冗余存储控制器。 集成交换设备包括多个I / O端口和每个I / O端口之间的数据传输路径,用于在其多对之间提供同时的数据传输。 交换机使设备能够在其I / O端口和存储设备I / O端口和/或主机I / O端口之间同时传输帧,从而在仲裁环路配置上提供增加的数据传输带宽。 另外,这些开关是智能的,并且可以被编程以实现改进的故障隔离。 该设备还可以包括服务器,其包括耦合到交换机的I / O端口,用于与设备外部的设备的存储控制器和/或I / O端口同时传送数据。
    • 10. 发明授权
    • Apparatus and method for address pipelining of dynamic random access
memory utilizing transparent page address latches to reduce wait states
    • 使用透明页地址锁存器来动态随机存取存储器地址流水线化以减少等待状态的装置和方法
    • US5640527A
    • 1997-06-17
    • US521259
    • 1995-08-30
    • Victor PeconeJoseph A. Vivio
    • Victor PeconeJoseph A. Vivio
    • G06F13/16G11C7/10G06F12/00G11C8/00G11C11/408
    • G06F13/161G06F13/1615G11C7/1039
    • An apparatus and method for address pipelining of a computer system that reduce the average number of wait states required to access a dynamic random access memory (DRAM) subsystem. A memory controller addresses a plurality of random access memory integrated circuits in pages of addresses wherein contiguous address pages are in different ones of the plurality of dynamic random access memory integrated circuits. Transparent latches associated with each of the different ones of the plurality of dynamic random access memory integrated circuits allow pipelining of address setups for more than one memory page at substantially the same time. The apparatus and method improve the write access times of a computer system and, when used with a computer system having address pipelining, both read and write accesses are improved because address set up latency time is reduced.
    • 一种用于减少访问动态随机存取存储器(DRAM)子系统所需的等待状态的平均数量的计算机系统的地址流水线的装置和方法。 存储器控制器在地址页中寻址多个随机存取存储器集成电路,其中连续的地址页在多个动态随机存取存储器集成电路中的不同的地址页中。 与多个动态随机存取存储器集成电路中的每个不同的动态随机存取存储器集成电路中的每一个相关联的透明锁存器允许基本上同时地对多于一个存储器页面的地址设置进行流水线化。 该装置和方法改善了计算机系统的写入访问时间,并且当与具有地址流水线的计算机系统一起使用时,读取和写入访问都被改进,因为地址设置延迟时间被减少。