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1. 发明授权

US08516422B1 Method and mechanism for implementing electronic designs having power information specifications background 有权
标题翻译：实现具有电力信息规格背景的电子设计的方法和机制
公开(公告)号：US08516422B1
公开(公告)日：2013-08-20
申请号：US12815239
申请日：2010-06-14
申请人： Qi Wang , Ankur Gupta , Pinhong Chen , Christina Chu , Manish Pandey , Huan-Chih Tsai , Sandeep Bhatia , Yonghao Chen , Steven Sharp , Vivek Chickermane , Patrick Gallagher
发明人： Qi Wang , Ankur Gupta , Pinhong Chen , Christina Chu , Manish Pandey , Huan-Chih Tsai , Sandeep Bhatia , Yonghao Chen , Steven Sharp , Vivek Chickermane , Patrick Gallagher
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022 , G06F17/5081 , G06F2217/78
摘要： A method for implementing a single file format for power-related information for an IC comprising: providing a circuit design in at least one design file in a non-transitory computer readable storage device; providing power-related design information in a file in the computer readable storage device that is separate from the at least one design file and that specifies multiple power domains within the circuit design, each power domain including one or more design object instances from within the circuit design and that specifies multiple power modes each power mode corresponding to a different combination of on/off states of the multiple specified power domains and that specifies isolation behavior relative to respective power domains; and using a computer to add power control circuitry to the circuit design that implements the power domains and power modes and isolation behavior specified in the power specification information.
摘要翻译：一种用于实现用于IC的功率相关信息的单个文件格式的方法，包括：在非暂时性计算机可读存储设备中的至少一个设计文件中提供电路设计; 在与所述至少一个设计文件分离的并且指定所述电路设计中的多个电力域的所述计算机可读存储设备中的文件中提供电力相关设计信息，每个电力域包括来自所述电路内的一个或多个设计对象实例并且指定多个功率模式，每个功率模式对应于多个指定功率域的开/关状态的不同组合，并且指定相对于相应功率域的隔离行为; 并且使用计算机将功率控制电路添加到实现功率规范信息中指定的功率域和功率模式以及隔离行为的电路设计。

2. 发明授权

US07739629B2 Method and mechanism for implementing electronic designs having power information specifications background 有权
标题翻译：实现具有电力信息规格背景的电子设计的方法和机制
公开(公告)号：US07739629B2
公开(公告)日：2010-06-15
申请号：US11590657
申请日：2006-10-30
申请人： Qi Wang , Ankur Gupta , Pinhong Chen , Christina Chu , Manish Pandey , Huan-Chih Tsai , Sandeep Bhatia , Yonghao Chen , Steven Sharp , Vivek Chickermane , Patrick Gallagher
发明人： Qi Wang , Ankur Gupta , Pinhong Chen , Christina Chu , Manish Pandey , Huan-Chih Tsai , Sandeep Bhatia , Yonghao Chen , Steven Sharp , Vivek Chickermane , Patrick Gallagher
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022 , G06F17/5081 , G06F2217/78
摘要： A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.
摘要翻译：一种将功率控制电路添加到RTL和网表级别中的每一个处的电路设计的方法，包括：划分所述电路设计内的多个电源域; 指定多个功率模式，每个功率模式对应于多个划分的功率域的开/关状态的不同组合; 并定义相对于各自的功率域的隔离行为。

3. 发明申请

US20070245285A1 Method and mechanism for implementing electronic designs having power information specifications background 有权
标题翻译：实现具有电力信息规格背景的电子设计的方法和机制
公开(公告)号：US20070245285A1
公开(公告)日：2007-10-18
申请号：US11590657
申请日：2006-10-30
申请人： Qi Wang , Ankur Gupta , Pinhong Chen , Christina Chu , Manish Pandey , Huan-Chih Tsai , Sandeep Bhatia , Yonghao Chen , Steven Sharp , Vivek Chickermane , Patrick Gallagher
发明人： Qi Wang , Ankur Gupta , Pinhong Chen , Christina Chu , Manish Pandey , Huan-Chih Tsai , Sandeep Bhatia , Yonghao Chen , Steven Sharp , Vivek Chickermane , Patrick Gallagher
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022 , G06F17/5081 , G06F2217/78
摘要： A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.
摘要翻译：一种将功率控制电路添加到RTL和网表级别中的每一个处的电路设计的方法，包括：划分所述电路设计内的多个电源域; 指定多个功率模式，每个功率模式对应于多个划分的功率域的开/关状态的不同组合; 并定义相对于各自的功率域的隔离行为。

4. 再颁专利

USRE44479E1 Method and mechanism for implementing electronic designs having power information specifications background 有权
标题翻译：实现具有电力信息规格背景的电子设计的方法和机制
公开(公告)号：USRE44479E1
公开(公告)日：2013-09-03
申请号：US13494363
申请日：2012-06-12
申请人： Qi Wang , Ankur Gupta , Pinhong Chen , Christina Chu , Manish Pandey , Huan-Chih Tsai , Sandeep Bhatia , Yonghoa Chen , Steven Sharp , Vivek Chickermane , Patrick Gallagher , Mitchell W. Hines
发明人： Qi Wang , Ankur Gupta , Pinhong Chen , Christina Chu , Manish Pandey , Huan-Chih Tsai , Sandeep Bhatia , Yonghoa Chen , Steven Sharp , Vivek Chickermane , Patrick Gallagher , Mitchell W. Hines
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022 , G06F17/5081 , G06F2217/78
摘要： A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.
摘要翻译：一种将功率控制电路添加到RTL和网表级别中的每一个处的电路设计的方法，包括：划分所述电路设计内的多个电源域; 指定多个功率模式，每个功率模式对应于多个划分的功率域的开/关状态的不同组合; 并定义相对于各自的功率域的隔离行为。

5. 发明授权

US08001433B1 Scan testing architectures for power-shutoff aware systems 有权
标题翻译：扫描测试架构，用于断电感知系统
公开(公告)号：US08001433B1
公开(公告)日：2011-08-16
申请号：US12345950
申请日：2008-12-30
申请人： Sandeep Bhatia , Patrick Gallagher , Brian Foutz , Vivek Chickermane
发明人： Sandeep Bhatia , Patrick Gallagher , Brian Foutz , Vivek Chickermane
IPC分类号： G01R31/28 , G06F17/50
CPC分类号： G01R31/318575 , G01R31/318563
摘要： In a circuit adapted for scan testing, a first set of connections configures the circuit elements into power domains with separate power-level controls, and a second set of connections configures the circuit elements to form scan segments for loading values into circuit elements from input ends of the scan segments and unloading values from circuit elements at output ends of the scan segments. A decompressor circuit receives a decompressor input and is operatively connected to the scan-segment input ends, and a compressor circuit is operatively connected to the scan segment output ends and generates a compressor output. Isolation circuits at scan-segment exits set values for scan segments at scan-segment exits when a corresponding independent power domain is in a power-off state.
摘要翻译：在适于扫描测试的电路中，第一组连接将电路元件配置成具有单独的功率电平控制的电源域，并且第二组连接将电路元件配置为形成用于从输入端将值加载到电路元件中的扫描段的扫描段和从扫描段输出端的电路元件卸载值。解压缩器电路接收解压缩器输入并且可操作地连接到扫描段输入端，并且压缩机电路可操作地连接到扫描段输出端并产生压缩器输出。扫描段出口处的隔离电路在相应的独立电源域处于关机状态时，为扫描段出口处的扫描段设置值。

6. 发明授权

US07779381B2 Test generation for low power circuits 有权
标题翻译：低功耗电路测试一代
公开(公告)号：US07779381B2
公开(公告)日：2010-08-17
申请号：US11519381
申请日：2006-09-11
申请人： Vivek Chickermane , James Sage , Patrick Gallagher , Xiaochuan Yuan
发明人： Vivek Chickermane , James Sage , Patrick Gallagher , Xiaochuan Yuan
IPC分类号： G06F17/50
CPC分类号： G01R31/31721 , G01R31/31813 , G06F17/5045
摘要： In the field of integrated circuit design and testing, especially directed towards integrated circuits intended to operate at low power, a method and system are provided for circuit design and simulation and testing for mapping portions of a circuit, such as a power domain or portion of a power domain, to a test mode. Thereby only those portions of the circuit which need to be powered up in a particular test mode are powered up both in the design (simulation) phase and in the actual testing. This conserves power usage during actual testing as against powering up all portions of the circuit, which is not desirable during the testing of the circuit after manufacture. This ensures that the power conditions required to excite and observe any circuit faults during testing exist for the power conditions that are applied during, for instance, manufacturing testing. By automatically partitioning the faults to remove those that cannot be excited or observed during manufacturing and testing, the testability of the device in terms of its partitions or parts will accurately reflect the power state of the logic portions of the circuit.
摘要翻译：在集成电路设计和测试领域，特别针对旨在以低功率运行的集成电路，提供了一种方法和系统，用于电路设计和仿真和测试，用于映射电路的部分，例如电源域或部分电源域，进入测试模式。因此，在设计（仿真）阶段和实际测试中只需要在特定测试模式下需要上电的电路的那些部分。这节省了实际测试期间的功率使用，以防止电路的所有部分上电，这在制造后的电路测试期间是不期望的。这确保了在测试过程中激发和观察任何电路故障所需的电源条件存在于例如制造测试期间应用的功率条件。通过自动划分故障以去除在制造和测试期间不能激发或观察到的故障，器件在其分区或部件方面的可测试性将准确反映电路逻辑部分的功率状态。

7. 发明申请

US20090326854A1 TESTING STATE RETENTION LOGIC IN LOW POWER SYSTEMS 有权
标题翻译：低功耗系统中的测试状态保持逻辑
公开(公告)号：US20090326854A1
公开(公告)日：2009-12-31
申请号：US12147428
申请日：2008-06-26
申请人： Krishna CHAKRAVADHANULA , Patrick Gallagher , Vivek Chickermane , Steven L. Gregor , Puneet Arora
发明人： Krishna CHAKRAVADHANULA , Patrick Gallagher , Vivek Chickermane , Steven L. Gregor , Puneet Arora
IPC分类号： G01R31/317
CPC分类号： G01R31/318575
摘要： A method of testing an Integrated Circuit (IC) includes: loading a sequence of data into a chain of circuit elements that hold data values, where outputs of at least some circuit elements are connected to inputs of adjacent circuit elements so values move sequentially through the chain between a chain input for loading values and a chain output for unloading values, and a first circuit element includes a retention element for saving values during power variations related to the IC. The method further includes: saving a value from the data sequence in the retention element; and accessing the retention element for verifying an accuracy of the saved value from the data sequence.
摘要翻译：一种测试集成电路（IC）的方法包括：将一系列数据加载到保持数据值的电路元件链中，其中至少一些电路元件的输出连接到相邻电路元件的输入，因此值顺序地通过用于装载值的链输入和用于卸载值的链输出之间的链，以及第一电路元件，包括用于在与IC相关的功率变化期间保存值的保持元件。该方法还包括：从保留元素中的数据序列中保存值; 以及访问所述保留元件，以从所述数据序列验证所保存的值的准确性。

8. 发明授权

US08271226B2 Testing state retention logic in low power systems 有权
标题翻译：在低功率系统中测试状态保持逻辑
公开(公告)号：US08271226B2
公开(公告)日：2012-09-18
申请号：US12147428
申请日：2008-06-26
申请人： Krishna Chakravadhanula , Patrick Gallagher , Vivek Chickermane , Steven L. Gregor , Puneet Arora
发明人： Krishna Chakravadhanula , Patrick Gallagher , Vivek Chickermane , Steven L. Gregor , Puneet Arora
IPC分类号： G06F3/00 , G06F3/01 , G06F3/06 , G06F13/10
CPC分类号： G01R31/318575
摘要： A method of testing an Integrated Circuit (IC) includes: loading a sequence of data into a chain of circuit elements that hold data values, where outputs of at least some circuit elements are connected to inputs of adjacent circuit elements so values move sequentially through the chain between a chain input for loading values and a chain output for unloading values, and a first circuit element includes a retention element for saving values during power variations related to the IC. The method further includes: saving a value from the data sequence in the retention element; and accessing the retention element for verifying an accuracy of the saved value from the data sequence.
摘要翻译：一种测试集成电路（IC）的方法包括：将一系列数据加载到保持数据值的电路元件链中，其中至少一些电路元件的输出连接到相邻电路元件的输入，因此值顺序地通过用于装载值的链输入和用于卸载值的链输出之间的链，以及第一电路元件，包括用于在与IC相关的功率变化期间保存值的保持元件。该方法还包括：从保留元素中的数据序列中保存值; 以及访问所述保留元件，以从所述数据序列验证所保存的值的准确性。

9. 发明授权

US07926012B1 Design-For-testability planner 有权
标题翻译：设计可测性规划师
公开(公告)号：US07926012B1
公开(公告)日：2011-04-12
申请号：US11951571
申请日：2007-12-06
申请人： Nitin Parimi , Patrick Gallagher , Brian Foutz , Vivek Chickermane
发明人： Nitin Parimi , Patrick Gallagher , Brian Foutz , Vivek Chickermane
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/505 , G06F2217/14
摘要： A method is provided to improve the usability of Design-For-Testability Synthesis (DFTS) tools and to increase the design process productivity. The method comprises receiving a list of testability and design impact analysis functions, to be performed on the circuit, also referred to as a device under test (DUT). The impact analysis leads to the creation of logical transformations, which can be selected by a user with one or more available transformation methods from a list including, but not limited to, boundary scan test logic insertion, scan test logic insertion, memory BIST (built-in-self-test) logic insertion, and logic BIST logic insertion, and scan test data compression insertion logic insertion.
摘要翻译：提供了一种提高设计可测性综合（DFTS）工具的可用性并提高设计流程生产率的方法。该方法包括接收在电路上执行的可测试性和设计影响分析功能的列表，也被称为被测设备（DUT）。影响分析导致逻辑变换的创建，其可以由用户从列表中选择一个或多个可用的转换方法，包括但不限于边界扫描测试逻辑插入，扫描测试逻辑插入，存储器BIST（内置 -in-self-test）逻辑插入和逻辑BIST逻辑插入，以及扫描测试数据压缩插入逻辑插入。

10. 发明授权

US07979764B2 Distributed test compression for integrated circuits 有权
标题翻译：集成电路的分布式测试压缩
公开(公告)号：US07979764B2
公开(公告)日：2011-07-12
申请号：US11933853
申请日：2007-11-01
申请人： Brian Foutz , Patrick Gallagher , Vivek Chickermane , Carl Barnhart
发明人： Brian Foutz , Patrick Gallagher , Vivek Chickermane , Carl Barnhart
IPC分类号： G01R31/28
CPC分类号： G06F11/267 , G01R31/318547
摘要： A method for testing integrated circuits is provided. The method provides for incorporating compression and decompression logic into each sub-component of an integrated circuit, developing test modes that target different sub-components of the integrated circuit, selecting one of the test modes, applying a test pattern to one or more sub-components of the integrated circuit targeted by the one test mode, comparing a response from application of the test pattern to a known good response, and diagnosing the response to determine which part of the one or more sub-components targeted by the one test mode failed when the response does not match the known good response.
摘要翻译：提供了一种用于测试集成电路的方法。该方法提供将压缩和解压缩逻辑并入到集成电路的每个子组件中，开发针对集成电路的不同子组件的测试模式，选择测试模式之一，将测试模式应用于一个或多个子模块，由一个测试模式所针对的集成电路的组件，将来自应用测试模式的响应与已知的良好响应进行比较，以及诊断响应以确定由一个测试模式所针对的一个或多个子组件的哪个部分失败当响应与已知的良好响应不匹配时。

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