专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08296703B1 Fault modeling for state retention logic 有权
标题翻译：状态保留逻辑的故障建模
公开(公告)号：US08296703B1
公开(公告)日：2012-10-23
申请号：US12339958
申请日：2008-12-19
申请人： Krishna Chakravadhanula , Steven L. Gregor , Brion L. Keller , Vivek Chickermane
发明人： Krishna Chakravadhanula , Steven L. Gregor , Brion L. Keller , Vivek Chickermane
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G11C29/56008 , G06F2217/78
摘要： A method for modeling state-retention logic includes: specifying a circuit that includes an arrangement of circuit elements, wherein a portion of the circuit is organized into a power domain with a power-domain control for effecting power variations within the power domain, and the power domain includes a state-retention cell that includes a retention element with a retention-element control for saving state-retention-cell values in the retention element during power variations in the power domain; determining one or more pattern faults for detecting defects in state-retention operation of the circuit by associating circuit element values with values for the power-domain control or the retention-element control; and saving one or more values for the one or more pattern faults.
摘要翻译：一种用于建模状态保持逻辑的方法包括：指定包括电路元件布置的电路，其中电路的一部分被组织成具有功率域控制的功率域，以实现功率域内的功率变化，并且功率域包括状态保持单元，其包括具有保持元件控制的保持元件，用于在功率域的功率变化期间在保持元件中保持状态保持单元值; 通过将电路元件值与功率域控制或保持元件控制的值相关联来确定用于检测电路的状态保持操作中的缺陷的一个或多个模式故障; 并为一个或多个模式故障保存一个或多个值。

2. 发明授权

US08271226B2 Testing state retention logic in low power systems 有权
标题翻译：在低功率系统中测试状态保持逻辑
公开(公告)号：US08271226B2
公开(公告)日：2012-09-18
申请号：US12147428
申请日：2008-06-26
申请人： Krishna Chakravadhanula , Patrick Gallagher , Vivek Chickermane , Steven L. Gregor , Puneet Arora
发明人： Krishna Chakravadhanula , Patrick Gallagher , Vivek Chickermane , Steven L. Gregor , Puneet Arora
IPC分类号： G06F3/00 , G06F3/01 , G06F3/06 , G06F13/10
CPC分类号： G01R31/318575
摘要： A method of testing an Integrated Circuit (IC) includes: loading a sequence of data into a chain of circuit elements that hold data values, where outputs of at least some circuit elements are connected to inputs of adjacent circuit elements so values move sequentially through the chain between a chain input for loading values and a chain output for unloading values, and a first circuit element includes a retention element for saving values during power variations related to the IC. The method further includes: saving a value from the data sequence in the retention element; and accessing the retention element for verifying an accuracy of the saved value from the data sequence.
摘要翻译：一种测试集成电路（IC）的方法包括：将一系列数据加载到保持数据值的电路元件链中，其中至少一些电路元件的输出连接到相邻电路元件的输入，因此值顺序地通过用于装载值的链输入和用于卸载值的链输出之间的链，以及第一电路元件，包括用于在与IC相关的功率变化期间保存值的保持元件。该方法还包括：从保留元素中的数据序列中保存值; 以及访问所述保留元件，以从所述数据序列验证所保存的值的准确性。

3. 发明授权

US07032144B2 Method and apparatus for testing multi-port memories 有权
公开(公告)号：US07032144B2
公开(公告)日：2006-04-18
申请号：US10425003
申请日：2003-04-28
申请人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
发明人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
IPC分类号： G11C29/00
CPC分类号： G11C29/52 , G11C8/16 , G11C2207/104
摘要： A method and system for testing multiported memories, especially when one or more of the ports are not directly accessible without intervening logic. The method and system segregates the multiported memory into at least two portions which are then used for testing the one or more ports which are not directly accessible.

4. 发明授权

US06907554B2 Built-in self test system and method for two-dimensional memory redundancy allocation 失效
标题翻译：内置自检系统和二维内存冗余分配方法
公开(公告)号：US06907554B2
公开(公告)日：2005-06-14
申请号：US10249817
申请日：2003-05-09
申请人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Gary S. Koch
发明人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Gary S. Koch
IPC分类号： G11C29/44 , G11C29/00
CPC分类号： G11C29/4401 , G11C29/44 , G11C2029/0401
摘要： A built-in self test system (124) and method for two-dimensional memory redundancy allocation. The built-in self test system is adapted to allocate two redundant columns (116) and one redundant row (120) to an embedded memory (104) as needed to repair single cell failures (SCFs) within the rows (108) and columns of the memory. The self-test system includes a left-priority encoder (136), a right-priority encoder (140), and a greater-than-two detector (144). The left-priority encoder encodes the location of the first SCF most proximate the most-significant bit of the corresponding word. The right-priority encoder encodes the location of the first SCF most proximate the least-significant bit of the corresponding word. The greater-than-two detector determines whether a word contains more than two SCFs. If the greater-than-two detector detects that a word contains more than two SCFs, the built-in self test system identifies the corresponding row as being a must-fix row, since the number of SCFs exceeds the number of redundant columns.
摘要翻译：内置自检系统（124）和二维内存冗余分配方法。所述内置自检系统适于根据需要将两个冗余列（116）和一个冗余行（120）分配给嵌入式存储器（104），以修复行（108）和列（108）中的单个单元故障（SCF）记忆。自检系统包括左优先编码器（136），右优先编码器（140）和大于二检测器（144）。左优先级编码器对最接近相应字最高有效位的第一SCF的位置进行编码。右优先编码器编码最接近对应字的最低有效位的第一SCF的位置。大于2的检测器确定一个单词是否包含两个以上的SCF。如果大于2的检测器检测到一个字含有两个以上的SCF，则内置的自检系统将相应的行识别为必须修复的行，因为SCF的数量超过冗余列的数量。

5. 发明授权

US06651201B1 Programmable memory built-in self-test combining microcode and finite state machine self-test 失效
标题翻译：可编程存储器内置自检组合微码和有限状态机自检
公开(公告)号：US06651201B1
公开(公告)日：2003-11-18
申请号：US09626715
申请日：2000-07-26
申请人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
发明人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
IPC分类号： G01R3128
CPC分类号： G01R31/3187 , G01R31/2891 , G11C29/16
摘要： A finite state machine (FSM) is used to generate, in real time, potentially long sequences of signals which control generation of signals for application to a memory structure during a self-test procedure which is provided in hardware on the same chip with the memory structure. The FSM-based instruction generator requires much less area than is required for storage of a corresponding number of microcode instructions and allows the built-in self-test (BIST) controller to have a modular architecture permitting re-use of hardware designs for the BIST arrangement with consequent reduction of elimination of design costs of the BIST arrangement to accommodate new memory designs. The sequential nature of the operation of a finite state machine as it progresses through a desired sequence of states is particularly well-suited to controlling capture of signals where access to high. speed data transfer circuits cannot otherwise be accommodated.
摘要翻译：有限状态机（FSM）用于实时地产生潜在的长序列信号，该序列控制信号的产生，以便在与存储器相同的芯片上的硬件中提供的自检过程期间应用于存储器结构结构体。基于FSM的指令生成器需要比存储相应数量的微代码指令所需的面积少得多的内存自检（BIST）控制器具有模块化架构，允许重新使用硬件设计用于BIST 从而减少了BIST安排的设计成本的消除以适应新的存储器设计。有限状态机在其进行期望的状态序列的操作的顺序性质特别适合于控制对高访问信号的捕获。速度数据传输电路不能适应。

6. 发明授权

US06557127B1 Method and apparatus for testing multi-port memories 失效
标题翻译：用于测试多端口存储器的方法和装置
公开(公告)号：US06557127B1
公开(公告)日：2003-04-29
申请号：US09514870
申请日：2000-02-28
申请人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
发明人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
IPC分类号： G11C2900
CPC分类号： G11C29/52 , G11C8/16 , G11C2207/104
摘要： A method and system for testing multiported memories, especially when one or more of the ports are not directly accessible without intervening logic. The method and system segregates the multiported memory into at least two portions which are then used for testing the one or more ports which are not directly accessible.
摘要翻译：一种用于测试多端口存储器的方法和系统，特别是当一个或多个端口不能直接访问而没有中间逻辑时。该方法和系统将多端口存储器隔离成至少两个部分，然后将其用于测试不能直接访问的一个或多个端口。

7. 发明授权

US5276848A Shared two level cache including apparatus for maintaining storage consistency 失效
标题翻译：共享两级缓存，包括维护存储一致性的设备
公开(公告)号：US5276848A
公开(公告)日：1994-01-04
申请号：US750430
申请日：1991-08-20
申请人： Patrick W. Gallagher , Steven L. Gregor , Stephen M. Reeve
发明人： Patrick W. Gallagher , Steven L. Gregor , Stephen M. Reeve
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0811 , G06F12/0897
摘要： A multilevel cache buffer for a multiprocessor system in which each processor has a level one cache storage unit which interfaces with a level two cache unit and main storage unit shared by all processors. The multiprocessors share the level two cache according to a priority algorithm. When data in the level two cache is updated, corresponding data in level one caches is invalidated until it is updated.
摘要翻译：用于多处理器系统的多级缓存缓冲器，其中每个处理器具有与所有处理器共享的二级高速缓存单元和主存储单元接口的一级缓存存储单元。多处理器根据优先级算法共享二级缓存。当二级缓存中的数据被更新时，一级缓存中的对应数据被无效，直到被更新。

8. 发明授权

US07168005B2 Programable multi-port memory BIST with compact microcode 失效
标题翻译：可编程多端口存储器BIST具有紧凑的微码
公开(公告)号：US07168005B2
公开(公告)日：2007-01-23
申请号：US10354535
申请日：2003-01-30
申请人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
发明人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
IPC分类号： G06F11/00
CPC分类号： G06F11/2242 , G11C8/16 , G11C29/16
摘要： A microcode programmable built-in-self-test (BIST) circuit and method for testing a multiported memory via multiple ports, either simultaneously or sequentially, as directed by a microcode instruction word. The microcode instruction word contains a plurality of executable subinstructions and one bit of information that controls whether the test operations prescribed in the plurality of subinstructions shall be executed in parallel or in series. The executable subinstructions are dispatched by a primary controller to subcontrollers which perform test operations at each port according to the subinstructions. The microcode programable BIST architecture flexibly facilitates the testing of multiple devices, multiported devices, including multiported memory structures and complex dependent multiported memory structures. The BIST supports in-situ testing of the functionality of the memory at wafer, module, and burn-in, as well as system-level testing.
摘要翻译：微代码可编程内置自检（BIST）电路和方法，用于通过多个端口同时或顺序地测试多端口存储器，如微代码指令字所指示的。微代码指令字包含多个可执行子指令和一位信息，用于控制多个子指令中规定的测试操作是并行还是串行执行。可执行子指令由主控制器分派到根据子提示在每个端口执行测试操作的子控制器。微码可编程BIST架构灵活地促进了多个设备，多端口设备的测试，包括多端口存储器结构和复杂的多端口存储器结构。 BIST支持在晶片，模块和老化模式下对存储器的功能进行现场测试，以及系统级测试。

9. 发明授权

US5450563A Storage protection keys in two level cache system 失效
标题翻译：二级缓存系统中的存储保护密钥
公开(公告)号：US5450563A
公开(公告)日：1995-09-12
申请号：US968767
申请日：1992-10-30
申请人： Steven L. Gregor
发明人： Steven L. Gregor
IPC分类号： G06F12/08 , G06F12/14 , G06F12/00
CPC分类号： G06F12/0875 , G06F12/1475 , G06F12/0897
摘要： The cache system comprises a level one (L1) data cache, a level one (L1) key cache for storing a plurality of access keys for respective pages or blocks of data referenced by the central processor. A level three (L3) storage stores the data requested by the central processor and an access key array including the plurality of access keys. A level two (L2) data cache is coupled between the L3 storage and the L1 data cache and stores a copy of data fetched from the L3 storage for the L1 data cache pursuant to a read request and data written by the central processor. The level two (L2) key cache is coupled between the L3 storage access key array and the L1 key cache and stores the plurality of access keys for respective pages or blocks of data in the L2 data cache. The general strategy of the cache system is to copy the access key corresponding to each central processor request into the L1 key cache the first time that any page of data is inpaged pursuant to a read or write request, so that the access key is readily available to the central processor for the current and subsequent requests. If the central processor request is to store data to the L2 data cache, the corresponding access key but not the data is copied into the L1 level, and the data is updated only in the L2 data cache, assuming that the data did not reside in the L1 data cache due to a previous read request.
摘要翻译：高速缓存系统包括一级（L1）数据高速缓存，一级（L1）密钥高速缓存，用于存储由中央处理器引用的相应页面或数据块的多个访问密钥。三级（L3）存储器存储由中央处理器请求的数据和包括多个访问密钥的访问密钥阵列。第二级（L2）数据高速缓存耦合在L3存储器和L1数据高速缓冲存储器之间，并且根据读取请求和由中央处理器写入的数据存储从用于L1数据高速缓存的L3存储器取出的数据的副本。第二级（L2）密钥缓存耦合在L3存储访问密钥阵列和L1密钥高速缓存之间，并将多个访问密钥存储在L2数据高速缓存中的各个页面或数据块。缓存系统的一般策略是在第一次根据读或写请求对任何数据页进行页面复制时，将与每个中央处理器请求相对应的访问密钥复制到L1密钥高速缓存中，使得访问密钥容易获得到当前和后续请求的中央处理器。如果中央处理器请求是将数据存储到L2数据高速缓存中，则相应的访问密钥而不是数据被复制到L1级，并且仅在L2数据高速缓存中更新数据，假设数据不在由于先前的读取请求导致的L1数据高速缓存。

10. 发明授权

US5313613A Execution of storage-immediate and storage-storage instructions within cache buffer storage 失效
标题翻译：在缓存缓存存储器中执行存储即时存储和存储指令
公开(公告)号：US5313613A
公开(公告)日：1994-05-17
申请号：US92374
申请日：1993-07-15
申请人： Steven L. Gregor
发明人： Steven L. Gregor
IPC分类号： G06F9/305 , G06F9/315 , G06F9/38 , G06F12/08 , G06F12/00 , G06F9/00
CPC分类号： G06F9/30029 , G06F12/0802 , G06F9/30032 , G06F9/30167 , G06F9/3824
摘要： A cache storage system having hardware for in-cache execution of storage-storage and storage-immediate instructions thereby obviating the need for data to be moved from the cache to a separate execution unit and back to cache.
摘要翻译：高速缓存存储系统具有用于缓存中执行存储和存储即时指令的硬件，从而避免了将数据从高速缓存移动到单独的执行单元并返回到高速缓存的需要。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式