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1. 发明申请

US20150358005A1 OFFSET CALIBRATION FOR LOW POWER AND HIGH PERFORMANCE RECEIVER 有权
标题翻译：低功率和高性能接收器的偏移校准
公开(公告)号：US20150358005A1
公开(公告)日：2015-12-10
申请号：US14298718
申请日：2014-06-06
申请人： QUALCOMM Incorporated
发明人： Minhan Chen , Kenneth Luis Arcudia
IPC分类号： H03K5/003 , H04L25/03 , H04B1/16
CPC分类号： H04L25/061 , H03K5/003 , H04B1/16 , H04L25/0272 , H04L25/0296 , H04L25/03057
摘要： Systems and methods for providing offset calibration for low power and high performance receivers are described herein. In one embodiment, a method for offset calibration comprises inputting a first voltage to a first input of a sample latch, and inputting a second voltage and an offset-cancelation voltage to a second input of the sample latch. The method also comprises adjusting the offset-cancelation voltage, observing an output of the sample latch as the offset-cancelation voltage is adjusted, and recording a value of the offset-cancelation voltage at which a metastable state is observed at the output of the sample latch. The method may be performed for each one of a plurality of different voltage levels for the first voltage to determine an offset-cancelation voltage for each one of the voltage levels.
摘要翻译：本文描述了用于为低功率和高性能接收机提供偏移校准的系统和方法。在一个实施例中，一种用于偏移校准的方法包括：将第一电压输入到采样锁存器的第一输入端，以及向采样锁存器的第二输入端输入第二电压和偏移消除电压。该方法还包括调整偏移消除电压，当调整偏移消除电压时观察样本锁存器的输出，并记录在样本的输出处观察到亚稳状态的偏移消除电压的值锁定。该方法可以针对第一电压的多个不同电压电平中的每一个执行，以确定每个电压电平的偏移消除电压。

2. 发明申请

US20190173440A1 OFFSET NULLING FOR HIGH-SPEED SENSE AMPLIFIER 审中-公开
公开(公告)号：US20190173440A1
公开(公告)日：2019-06-06
申请号：US15829774
申请日：2017-12-01
申请人： QUALCOMM Incorporated
发明人： Todd Morgan Rasmus , Minhan Chen
IPC分类号： H03F3/45
摘要： A resistor in a pair of resistors is selectively coupled to a current source through a selection switch during the reset phase of a voltage-mode sense amplifier so that one evaluation node for the voltage-mode sense amplifier is discharged from a power supply voltage by an ohmic voltage drop across the selectively-coupled resistor to null an offset for the voltage-mode sense amplifier.

3. 发明申请

US20160294583A1 OFFSET CALIBRATION FOR LOW POWER AND HIGH PERFORMANCE RECEIVER 有权
标题翻译：低功率和高性能接收器的偏移校准
公开(公告)号：US20160294583A1
公开(公告)日：2016-10-06
申请号：US15175990
申请日：2016-06-07
申请人： QUALCOMM Incorporated
发明人： Minhan Chen , Kenneth Luis Arcudia
IPC分类号： H04L25/06 , H03K5/003
CPC分类号： H04L25/061 , H03K5/003 , H04B1/16 , H04L25/0272 , H04L25/0296 , H04L25/03057
摘要： Systems and methods for providing offset calibration for low power and high performance receivers are described herein. In one embodiment, a receiver comprises a sample latch having a first input coupled to a receive data path, and a second input. The receive also comprises a first digital-to-analog converter (DAC), a second DAC, and a calibration controller. In a calibration mode, the calibration controller is configured to input a calibration voltage to the first input of the sample latch using the first DAC, to input a threshold voltage and an offset-cancelation voltage to the second input of the sample latch using the second DAC, to adjust the offset-cancelation voltage, to observe an output of the sample latch as the offset-cancelation voltage is adjusted, and to store a value of the offset-cancelation voltage at which a metastable state is observed at the output of the sample latch in a memory.
摘要翻译：本文描述了用于为低功率和高性能接收机提供偏移校准的系统和方法。在一个实施例中，接收机包括具有耦合到接收数据路径的第一输入和第二输入的采样锁存器。接收器还包括第一数模转换器（DAC），第二DAC和校准控制器。在校准模式中，校准控制器被配置为使用第一DAC将校准电压输入到采样锁存器的第一输入端，以使用第二DAC向采样锁存器的第二输入端输入阈值电压和偏移消除电压 DAC，以调整偏移消除电压，以在调整偏移消除电压时观察样本锁存器的输出，并存储在该输出处观察到亚稳态的偏移消除电压的值样品锁存在存储器中。

4. 发明授权

US10965442B2 Low-power, low-latency time-to-digital-converter-based serial link 有权
公开(公告)号：US10965442B2
公开(公告)日：2021-03-30
申请号：US16150123
申请日：2018-10-02
申请人： QUALCOMM Incorporated
发明人： Eskinder Hailu , Bupesh Pandita , Jon Boyette , Hadi Goudarzi , Yong Suk Jun , Zhi Zhu , Minhan Chen
IPC分类号： H04L7/033 , G04F10/00 , H04L7/00 , H03K3/037 , H03K5/159
摘要： A receiver is provided that includes a time-to-digital converter for converting a phase difference between a clock signal and a received data signal into a phase-difference digital code. The receiver also includes a logic circuit that controls a programmable delay line to delay the clock signal into a delayed clock signal by a delay that is responsive to a difference between the phase-difference code and a unit interval for the clock signal. The delayed clock signal clocks a flip-flop to register the received data signal.

5. 发明授权

US09722823B2 Offset calibration for low power and high performance receiver 有权
公开(公告)号：US09722823B2
公开(公告)日：2017-08-01
申请号：US15175990
申请日：2016-06-07
申请人： QUALCOMM Incorporated
发明人： Minhan Chen , Kenneth Luis Arcudia
IPC分类号： H04L25/06 , H03K5/003 , H04B1/16 , H04L25/02 , H04L25/03
CPC分类号： H04L25/061 , H03K5/003 , H04B1/16 , H04L25/0272 , H04L25/0296 , H04L25/03057
摘要： Systems and methods for providing offset calibration for low power and high performance receivers are described herein. In one embodiment, a receiver comprises a sample latch having a first input coupled to a receive data path, and a second input. The receive also comprises a first digital-to-analog converter (DAC), a second DAC, and a calibration controller. In a calibration mode, the calibration controller is configured to input a calibration voltage to the first input of the sample latch using the first DAC, to input a threshold voltage and an offset-cancelation voltage to the second input of the sample latch using the second DAC, to adjust the offset-cancelation voltage, to observe an output of the sample latch as the offset-cancelation voltage is adjusted, and to store a value of the offset-cancelation voltage at which a metastable state is observed at the output of the sample latch in a memory.

6. 发明授权

US09614502B2 Accurate sample latch offset compensation scheme 有权
公开(公告)号：US09614502B2
公开(公告)日：2017-04-04
申请号：US14818091
申请日：2015-08-04
申请人： QUALCOMM Incorporated
发明人： Minhan Chen , Kenneth Luis Arcudia
IPC分类号： H03K3/356
CPC分类号： H03K3/356104 , H03F3/45183 , H03F3/45475 , H03F3/72 , H03F2200/234 , H03F2200/27 , H03F2200/297 , H03F2200/366 , H03F2200/375 , H03F2200/45 , H03F2200/525 , H03F2200/75 , H03F2200/78 , H03F2200/84 , H03F2203/7203
摘要： A receiver according to one aspect comprises a latch configured to sample a data signal according to a sampling clock signal, and a plurality of offset-compensation segments, wherein each of the segments is coupled to an internal node of the latch. Each of the segments comprises a compensation transistor, and a step-adjustment transistor coupled in series with the compensation transistor. The receiver further comprises an offset controller configured to selectively turn on one or more of the compensations transistors to reduce an offset voltage of the latch, and a bias circuit configured to apply a bias voltage to a gate of each of one or more of the step-adjustment transistors.

7. 发明申请

US20170040983A1 ACCURATE SAMPLE LATCH OFFSET COMPENSATION SCHEME 有权
标题翻译：精确采样锁定补偿方案
公开(公告)号：US20170040983A1
公开(公告)日：2017-02-09
申请号：US14818091
申请日：2015-08-04
申请人： QUALCOMM Incorporated
发明人： Minhan Chen , Kenneth Luis Arcudia
IPC分类号： H03K3/356
CPC分类号： H03K3/356104 , H03F3/45183 , H03F3/45475 , H03F3/72 , H03F2200/234 , H03F2200/27 , H03F2200/297 , H03F2200/366 , H03F2200/375 , H03F2200/45 , H03F2200/525 , H03F2200/75 , H03F2200/78 , H03F2200/84 , H03F2203/7203
摘要： A receiver according to one aspect comprises a latch configured to sample a data signal according to a sampling clock signal, and a plurality of offset-compensation segments, wherein each of the segments is coupled to an internal node of the latch. Each of the segments comprises a compensation transistor, and a step-adjustment transistor coupled in series with the compensation transistor. The receiver further comprises an offset controller configured to selectively turn on one or more of the compensations transistors to reduce an offset voltage of the latch, and a bias circuit configured to apply a bias voltage to a gate of each of one or more of the step-adjustment transistors.
摘要翻译：根据一个方面的接收机包括配置成根据采样时钟信号对数据信号进行采样的锁存器以及多个偏移补偿段，其中每个段耦合到锁存器的内部节点。每个段包括补偿晶体管和与补偿晶体管串联耦合的步进调节晶体管。接收器还包括偏移控制器，其被配置为选择性地接通补偿晶体管中的一个或多个以减小锁存器的偏移电压;以及偏置电路，被配置为将偏置电压施加到步骤中的一个或多个步骤调整晶体管。

8. 发明申请

US20160216317A1 BUILT-IN TEST STRUCTURE FOR A RECEIVER 审中-公开
标题翻译：接收器的内置测试结构
公开(公告)号：US20160216317A1
公开(公告)日：2016-07-28
申请号：US14603025
申请日：2015-01-22
申请人： QUALCOMM, Incorporated
发明人： Minhan Chen , Kenneth Luis Arcudia , Bupesh Pandita
IPC分类号： G01R31/28 , H04B17/20
CPC分类号： H04B17/29
摘要： In one embodiment, a method for operating a receiver having a first receiver input and a second receiver input is described herein. The method comprises receiving a data signal via the first and second receiver inputs in a mission mode, AC-coupling the received data signal to an amplifier, and amplifying the AC-coupled data signal using the amplifier. The method also comprises receiving one or more test signals via one or both of the first and second receiver inputs in a test mode, DC-coupling the received one or more test signals to a test receiver, and determining whether there are one or more defects based on the one or more test signals received by the test receiver.
摘要翻译：在一个实施例中，这里描述了一种用于操作具有第一接收机输入和第二接收机输入的接收机的方法。该方法包括以任务模式经由第一和第二接收器输入接收数据信号，将接收的数据信号AC耦合到放大器，以及使用放大器放大AC耦合的数据信号。该方法还包括在测试模式中经由第一和第二接收机输入中的一个或两者接收一个或多个测试信号，将接收的一个或多个测试信号直接耦合到测试接收机，以及确定是否存在一个或多个缺陷基于由测试接收机接收的一个或多个测试信号。

9. 发明授权

US10326417B1 Offset nulling for high-speed sense amplifier 有权
公开(公告)号：US10326417B1
公开(公告)日：2019-06-18
申请号：US15829774
申请日：2017-12-01
申请人： QUALCOMM Incorporated
发明人： Todd Morgan Rasmus , Minhan Chen
IPC分类号： H03F3/45
摘要： A resistor in a pair of resistors is selectively coupled to a current source through a selection switch during the reset phase of a voltage-mode sense amplifier so that one evaluation node for the voltage-mode sense amplifier is discharged from a power supply voltage by an ohmic voltage drop across the selectively-coupled resistor to null an offset for the voltage-mode sense amplifier.

10. 发明授权

US09385695B2 Offset calibration for low power and high performance receiver 有权
标题翻译：低功耗和高性能接收机的偏移校准
公开(公告)号：US09385695B2
公开(公告)日：2016-07-05
申请号：US14298718
申请日：2014-06-06
申请人： QUALCOMM Incorporated
发明人： Minhan Chen , Kenneth Luis Arcudia
IPC分类号： H03H7/30 , H03K5/003 , H04B1/16 , H04L25/02 , H04L25/06 , H04L25/03
CPC分类号： H04L25/061 , H03K5/003 , H04B1/16 , H04L25/0272 , H04L25/0296 , H04L25/03057
摘要： Systems and methods for providing offset calibration for low power and high performance receivers are described herein. In one embodiment, a method for offset calibration comprises inputting a first voltage to a first input of a sample latch, and inputting a second voltage and an offset-cancellation voltage to a second input of the sample latch. The method also comprises adjusting the offset-cancellation voltage, observing an output of the sample latch as the offset-cancellation voltage is adjusted, and recording a value of the offset-cancellation voltage at which a metastable state is observed at the output of the sample latch. The method may be performed for each one of a plurality of different voltage levels for the first voltage to determine an offset-cancellation voltage for each one of the voltage levels.
摘要翻译：本文描述了用于为低功率和高性能接收机提供偏移校准的系统和方法。在一个实施例中，用于偏移校准的方法包括将第一电压输入到采样锁存器的第一输入端，以及将第二电压和偏移消除电压输入到采样锁存器的第二输入端。该方法还包括调整偏移消除电压，在调整偏移消除电压时观察样本锁存器的输出，并记录在样本的输出处观察到亚稳态的偏移消除电压的值锁定。该方法可以针对第一电压的多个不同电压电平中的每一个执行，以确定每个电压电平的偏移消除电压。

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