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1. 发明授权

US09577646B1 Fractional phase locked loop (PLL) architecture 有权
标题翻译：分数锁相环（PLL）架构
公开(公告)号：US09577646B1
公开(公告)日：2017-02-21
申请号：US14820894
申请日：2015-08-07
申请人： QUALCOMM Incorporated
发明人： Bupesh Pandita , Hanan Cohen , Eskinder Hailu , Kenneth Luis Arcudia
IPC分类号： H03K21/10
CPC分类号： H03K21/10 , H03L7/18 , H03L7/197 , H03L7/1974 , H03L7/1976
摘要： In one embodiment, method for frequency division comprises propagating a modulus signal up a chain of cascaded divider stages from a last one of the divider stages to a first one of the divider stages, and, for each of the divider stages, generating a respective local load signal when the modulus signal propagates out of the divider stage. The method also comprises, for each of the divider stages, inputting one or more respective control bits to the divider stage based on the respective local load signal, the one or more respective control bits setting a divider value of the divider stage.
摘要翻译：在一个实施例中，用于分频的方法包括将模数信号向上传播到一级级联分频器级从最后一级分频级到第一分频级，并且对于每个分频级，产生相应的本地当模数信号传播到分频器级之后的负载信号。该方法还包括对于每个分频器级，基于相应的本地负载信号将一个或多个相应的控制位输入到分频器级，所述一个或多个相应的控制位设置分频器级的分频器值。

2. 发明申请

US20160020740A1 WIDEBAND LOW-POWER AMPLIFIER 有权
标题翻译：宽带低功率放大器
公开(公告)号：US20160020740A1
公开(公告)日：2016-01-21
申请号：US14335421
申请日：2014-07-18
申请人： QUALCOMM Incorporated
发明人： Kenneth Luis Arcudia , Zhiqin Chen
IPC分类号： H03F3/45
CPC分类号： H03F1/3211 , H03F1/42 , H03F3/45197 , H03F3/45654 , H03F2203/45332 , H03F2203/45488 , H03F2203/45494 , H03F2203/45644 , H03F2203/45691 , H03F2203/45726 , H03G5/28
摘要： An amplifier is provided that includes a differential pair of transistors configured to steer a tail current responsive to a differential input voltage. The amplifier also includes a transconductor that tranconducts high-frequency changes in the differential output voltage into a differential bias current conducted through the differential pair of transistors.
摘要翻译：提供了一种放大器，其包括配置成响应于差分输入电压来引导尾部电流的差分晶体管晶体管。放大器还包括跨导器，其将差分输出电压中的高频变化转换成通过差分对晶体管传导的差分偏置电流。

3. 发明申请

US20160019183A1 SYSTEMS AND METHODS FOR CHIP TO CHIP COMMUNICATION 有权
标题翻译：用于芯片通信的芯片的系统和方法
公开(公告)号：US20160019183A1
公开(公告)日：2016-01-21
申请号：US14801310
申请日：2015-07-16
申请人： QUALCOMM Incorporated
发明人： Jason Alan Thurston , Kenneth Luis Arcudia
IPC分类号： G06F13/42 , G06F13/364 , G06F1/08
CPC分类号： G06F13/4291 , G06F1/08 , G06F13/364 , Y02D10/14 , Y02D10/151
摘要： Systems and methods for chip to chip communication are disclosed. In an exemplary aspect, a chip to chip link comprises a master device having a data transmitter, a clock, a clock transmitter, a phase locked loop (PLL) associated with the clock, and a receiver. The chip to chip link also comprises a slave device that has a data transmitter, a clock receiver, and a data receiver. Noticeably absent from the slave device is a clock or a PLL. By removing the clock from the slave device, the slave device does not have the power consuming element of a slave PLL. Further, because the slave device does not have a clock which would normally have to acquire a new frequency and settle, the master clock may change frequency relatively quickly and vary the frequency across many frequencies, not just one or two predefined frequencies.
摘要翻译：公开了用于芯片到芯片通信的系统和方法。在示例性方面，芯片到芯片链路包括具有数据发送器，时钟，时钟发送器，与时钟相关联的锁相环（PLL）的主器件和接收器。芯片到芯片链路还包括具有数据发送器，时钟接收器和数据接收器的从设备。从属设备显然不存在时钟或PLL。通过从从设备移除时钟，从器件不具有从PLL的功耗元件。此外，因为从设备没有通常必须获取新频率并且稳定的时钟，所以主时钟可以相对快速地改变频率，并且在许多频率上改变频率，而不仅仅是一个或两个预定义的频率。

4. 发明申请

US20170041005A1 NEW FRACTIONAL PHASE LOCKED LOOP (PLL) ARCHITECTURE 有权
标题翻译：新的相位锁相环（PLL）架构
公开(公告)号：US20170041005A1
公开(公告)日：2017-02-09
申请号：US14820894
申请日：2015-08-07
申请人： QUALCOMM Incorporated
发明人： Bupesh Pandita , Hanan Cohen , Eskinder Hailu , Kenneth Luis Arcudia
IPC分类号： H03K21/10
CPC分类号： H03K21/10 , H03L7/18 , H03L7/197 , H03L7/1974 , H03L7/1976
摘要： In one embodiment, method for frequency division comprises propagating a modulus signal up a chain of cascaded divider stages from a last one of the divider stages to a first one of the divider stages, and, for each of the divider stages, generating a respective local load signal when the modulus signal propagates out of the divider stage. The method also comprises, for each of the divider stages, inputting one or more respective control bits to the divider stage based on the respective local load signal, the one or more respective control bits setting a divider value of the divider stage.
摘要翻译：在一个实施例中，用于分频的方法包括将模数信号向上传播到一级级联分频器级从最后一级分频级到第一分频级，并且对于每个分频级，产生相应的本地当模数信号传播到分频器级之后的负载信号。该方法还包括对于每个分频器级，基于相应的本地负载信号将一个或多个相应的控制位输入到分频器级，所述一个或多个相应的控制位设置分频器级的分频器值。

5. 发明授权

US09485084B2 Linearity of phase interpolators by combining current coding and size coding 有权
标题翻译：通过组合当前编码和大小编码来实现相位内插器的线性度
公开(公告)号：US09485084B2
公开(公告)日：2016-11-01
申请号：US14300127
申请日：2014-06-09
申请人： Qualcomm Incorporated
发明人： Li Sun , Zhi Zhu , Xiaohua Kong , Kenneth Luis Arcudia , Zhiqin Chen
IPC分类号： H04L7/033 , H03L7/099 , H03K5/135 , H03K5/00
CPC分类号： H04L7/0331 , H03K5/135 , H03K2005/00065 , H03L7/099
摘要： A phase interpolator, including: a first portion including a first plurality of branches and a plurality of tail current sources, each branch including a differential pair of transistors, source terminals of the differential pair of transistors connect to form a source node, wherein each tail current source couples to one of the source nodes, and wherein the differential pair of transistors and the corresponding tail current source are configured in a current coding scheme; a second portion including a second plurality of branches and a fixed current source coupled to the second plurality of branches, each branch of the second plurality of branches including a second plurality of differential pairs of transistors and a plurality of switches configured in a size coding scheme; wherein the first portion and the second portion are coupled to each other and to a pair of load resistors.
摘要翻译：一种相位插值器，包括：包括第一多个分支和多个尾电流源的第一部分，每个分支包括差分对晶体管，所述差分对晶体管的源极端子连接以形成源节点，其中每个尾部电流源耦合到源节点之一，并且其中所述差分对晶体管和相应的尾电流源以当前编码方案配置; 第二部分包括第二多个分支和耦合到第二多个分支的固定电流源，第二多个分支的每个分支包括第二多个差分对晶体管和多个开关，其以尺寸编码方案 ; 其中所述第一部分和所述第二部分彼此耦合并耦合到一对负载电阻器。

6. 发明申请

US20160269034A1 APPARATUSES, METHODS, AND SYSTEMS FOR GLITCH-FREE CLOCK SWITCHING 有权
标题翻译：免提时钟切换的设备，方法和系统
公开(公告)号：US20160269034A1
公开(公告)日：2016-09-15
申请号：US14657225
申请日：2015-03-13
申请人： QUALCOMM Incorporated
发明人： Chad Everett Winemiller , Behnam Amelifard , Kenneth Luis Arcudia , Jon Raymond Boyette , Chia Heng Chang , Russell Coleman Deans , Kevin Wayne Spears
IPC分类号： H03L7/08 , G06F1/12
CPC分类号： G06F1/12 , G06F1/04 , G06F1/3237 , G06F1/3293 , Y02D10/122 , Y02D10/128
摘要： Aspects disclosed in the detailed description include apparatuses, methods, and systems for glitch-free clock switching. In this regard, in one aspect, an electronic circuit is switched from a lower-frequency reference clock to a higher-frequency reference clock. An oscillation detection logic is configured to determine the stability of the higher-frequency reference clock prior to switching the electronic circuit to the higher-frequency reference clock. The oscillation detection logic derives a sampled clock signal from the higher-frequency reference clock, wherein the sampled clock signal has a slower frequency than the lower-frequency reference clock. The oscillation detection logic then compares the sampled clock signal against the lower-frequency reference clock to determine the stability of the higher-frequency reference clock. By deterministically detecting stability of a reference clock prior to switching to the reference clock, it is possible to avoid premature switching to an unstable reference clock, thus providing glitch-free clock switching in the electronic circuit.
摘要翻译：在详细描述中公开的方面包括用于无毛刺时钟切换的装置，方法和系统。在这方面，在一个方面，电子电路从低频参考时钟切换到较高频率参考时钟。振荡检测逻辑被配置为在将电子电路切换到较高频率参考时钟之前确定较高频率参考时钟的稳定性。振荡检测逻辑从较高频率参考时钟导出采样时钟信号，其中采样时钟信号的频率比低频参考时钟慢。振荡检测逻辑然后将采样的时钟信号与较低频率参考时钟进行比较，以确定较高频率参考时钟的稳定性。通过在切换到参考时钟之前确定性地检测参考时钟的稳定性，可以避免过早切换到不稳定的参考时钟，从而在电子电路中提供无毛刺的时钟切换。

7. 发明申请

US20150358005A1 OFFSET CALIBRATION FOR LOW POWER AND HIGH PERFORMANCE RECEIVER 有权
标题翻译：低功率和高性能接收器的偏移校准
公开(公告)号：US20150358005A1
公开(公告)日：2015-12-10
申请号：US14298718
申请日：2014-06-06
申请人： QUALCOMM Incorporated
发明人： Minhan Chen , Kenneth Luis Arcudia
IPC分类号： H03K5/003 , H04L25/03 , H04B1/16
CPC分类号： H04L25/061 , H03K5/003 , H04B1/16 , H04L25/0272 , H04L25/0296 , H04L25/03057
摘要： Systems and methods for providing offset calibration for low power and high performance receivers are described herein. In one embodiment, a method for offset calibration comprises inputting a first voltage to a first input of a sample latch, and inputting a second voltage and an offset-cancelation voltage to a second input of the sample latch. The method also comprises adjusting the offset-cancelation voltage, observing an output of the sample latch as the offset-cancelation voltage is adjusted, and recording a value of the offset-cancelation voltage at which a metastable state is observed at the output of the sample latch. The method may be performed for each one of a plurality of different voltage levels for the first voltage to determine an offset-cancelation voltage for each one of the voltage levels.
摘要翻译：本文描述了用于为低功率和高性能接收机提供偏移校准的系统和方法。在一个实施例中，一种用于偏移校准的方法包括：将第一电压输入到采样锁存器的第一输入端，以及向采样锁存器的第二输入端输入第二电压和偏移消除电压。该方法还包括调整偏移消除电压，当调整偏移消除电压时观察样本锁存器的输出，并记录在样本的输出处观察到亚稳状态的偏移消除电压的值锁定。该方法可以针对第一电压的多个不同电压电平中的每一个执行，以确定每个电压电平的偏移消除电压。

8. 发明授权

US09485085B2 Phase locked loop (PLL) architecture 有权
标题翻译：锁相环（PLL）架构
公开(公告)号：US09485085B2
公开(公告)日：2016-11-01
申请号：US14644029
申请日：2015-03-10
申请人： QUALCOMM, Incorporated
发明人： Kenneth Luis Arcudia , Jeffrey Andrew Shafer , Bupesh Pandita
IPC分类号： H04L7/033 , H04L7/04 , H04L7/00 , H03B5/12
CPC分类号： H04L7/0332 , H03B5/1212 , H03B5/1228 , H03L7/091 , H03L7/093 , H04L7/0025 , H04L7/041
摘要： In one embodiment, a phase locked loop (PLL) comprises a voltage-controlled oscillator (VCO), a frequency divider configured to frequency divide an output signal of the VCO to produce a feedback signal, and a phase detection circuit configured to detect a phase difference between a reference signal and the feedback signal, and to generate an output signal based on the detected phase difference. The PLL also comprises a proportional circuit configured to generate a control voltage based on the output signal of the phase detection circuit, wherein the control voltage tunes a first capacitance of the VCO to provide phase correction. The PLL further comprises an integration circuit configured to convert the control voltage into a digital signal, to integrate the digital signal, and to tune a second capacitance of the VCO based on the integrated digital signal to provide frequency tracking.
摘要翻译：在一个实施例中，锁相环（PLL）包括压控振荡器（VCO），分频器，被配置为频率分频VCO的输出信号以产生反馈信号;以及相位检测电路，被配置为检测相位参考信号和反馈信号之间的差异，并且基于检测到的相位差产生输出信号。 PLL还包括比例电路，其被配置为基于相位检测电路的输出信号产生控制电压，其中控制电压调谐VCO的第一电容以提供相位校正。 PLL还包括集成电路，其被配置为将控制电压转换为数字信号，以集成数字信号，并且基于积分数字信号来调谐VCO的第二电容以提供频率跟踪。

9. 发明申请

US20160294583A1 OFFSET CALIBRATION FOR LOW POWER AND HIGH PERFORMANCE RECEIVER 有权
标题翻译：低功率和高性能接收器的偏移校准
公开(公告)号：US20160294583A1
公开(公告)日：2016-10-06
申请号：US15175990
申请日：2016-06-07
申请人： QUALCOMM Incorporated
发明人： Minhan Chen , Kenneth Luis Arcudia
IPC分类号： H04L25/06 , H03K5/003
CPC分类号： H04L25/061 , H03K5/003 , H04B1/16 , H04L25/0272 , H04L25/0296 , H04L25/03057
摘要： Systems and methods for providing offset calibration for low power and high performance receivers are described herein. In one embodiment, a receiver comprises a sample latch having a first input coupled to a receive data path, and a second input. The receive also comprises a first digital-to-analog converter (DAC), a second DAC, and a calibration controller. In a calibration mode, the calibration controller is configured to input a calibration voltage to the first input of the sample latch using the first DAC, to input a threshold voltage and an offset-cancelation voltage to the second input of the sample latch using the second DAC, to adjust the offset-cancelation voltage, to observe an output of the sample latch as the offset-cancelation voltage is adjusted, and to store a value of the offset-cancelation voltage at which a metastable state is observed at the output of the sample latch in a memory.
摘要翻译：本文描述了用于为低功率和高性能接收机提供偏移校准的系统和方法。在一个实施例中，接收机包括具有耦合到接收数据路径的第一输入和第二输入的采样锁存器。接收器还包括第一数模转换器（DAC），第二DAC和校准控制器。在校准模式中，校准控制器被配置为使用第一DAC将校准电压输入到采样锁存器的第一输入端，以使用第二DAC向采样锁存器的第二输入端输入阈值电压和偏移消除电压 DAC，以调整偏移消除电压，以在调整偏移消除电压时观察样本锁存器的输出，并存储在该输出处观察到亚稳态的偏移消除电压的值样品锁存在存储器中。

10. 发明申请

US20160269172A1 NOVEL PHASE LOCKED LOOP (PLL) ARCHITECTURE 有权
标题翻译：新型锁相环（PLL）架构
公开(公告)号：US20160269172A1
公开(公告)日：2016-09-15
申请号：US14644029
申请日：2015-03-10
申请人： QUALCOMM, Incorporated
发明人： Kenneth Luis Arcudia , Jeffrey Andrew Shafer , Bupesh Pandita
IPC分类号： H04L7/033 , H04L7/00 , H03B5/12 , H04L7/04
CPC分类号： H04L7/0332 , H03B5/1212 , H03B5/1228 , H03L7/091 , H03L7/093 , H04L7/0025 , H04L7/041
摘要： In one embodiment, a phase locked loop (PLL) comprises a voltage-controlled oscillator (VCO), a frequency divider configured to frequency divide an output signal of the VCO to produce a feedback signal, and a phase detection circuit configured to detect a phase difference between a reference signal and the feedback signal, and to generate an output signal based on the detected phase difference. The PLL also comprises a proportional circuit configured to generate a control voltage based on the output signal of the phase detection circuit, wherein the control voltage tunes a first capacitance of the VCO to provide phase correction. The PLL further comprises an integration circuit configured to convert the control voltage into a digital signal, to integrate the digital signal, and to tune a second capacitance of the VCO based on the integrated digital signal to provide frequency tracking.
摘要翻译：在一个实施例中，锁相环（PLL）包括压控振荡器（VCO），分频器，被配置为频率分频VCO的输出信号以产生反馈信号;以及相位检测电路，被配置为检测相位参考信号和反馈信号之间的差异，并且基于检测到的相位差产生输出信号。 PLL还包括比例电路，其被配置为基于相位检测电路的输出信号产生控制电压，其中控制电压调谐VCO的第一电容以提供相位校正。 PLL还包括集成电路，其被配置为将控制电压转换为数字信号，以集成数字信号，并且基于积分数字信号来调谐VCO的第二电容以提供频率跟踪。

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