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1. 发明授权

US09443572B2 Programmable power for a memory interface 有权
标题翻译：用于存储器接口的可编程电源
公开(公告)号：US09443572B2
公开(公告)日：2016-09-13
申请号：US14298730
申请日：2014-06-06
申请人： QUALCOMM Incorporated
发明人： Jan Christian Diffenderfer , Yuehchun Claire Cheng
IPC分类号： G11C7/00 , G11C11/4076 , H03L7/08 , G11C7/10 , H03L7/081
CPC分类号： G11C11/4076 , G11C7/1066 , G11C7/1093 , H03L7/08 , H03L7/0805 , H03L7/0812
摘要： Systems and methods for delay control are described herein. In one embodiment, a delay system comprises a first delay circuit configured to provide a voltage bias to a second delay circuit, wherein the voltage bias controls a delay of the second delay circuit, and to update the voltage bias at an update rate. The delay system also comprises an update controller configured to adjust the update rate of the first delay circuit. For example, the update controller may adjust the update rate based on timing requirements of a memory interface incorporating the delay system. The update rate may be reduced when the timing requirements are more relaxed to reduce power, and may be increased when the timing requirements are tighter.
摘要翻译：本文描述了用于延迟控制的系统和方法。在一个实施例中，延迟系统包括被配置为向第二延迟电路提供电压偏置的第一延迟电路，其中电压偏压控制第二延迟电路的延迟，并以更新速率更新电压偏置。延迟系统还包括被配置为调整第一延迟电路的更新速率的更新控制器。例如，更新控制器可以基于包含延迟系统的存储器接口的定时要求来调整更新速率。当定时要求更加放松以降低功率时，可以减少更新速率，并且当定时要求更紧时可能会增加更新速率。

2. 发明申请

US20150358007A1 DELAY STRUCTURE FOR A MEMORY INTERFACE 有权
标题翻译：用于记忆界面的延迟结构
公开(公告)号：US20150358007A1
公开(公告)日：2015-12-10
申请号：US14298742
申请日：2014-06-06
申请人： QUALCOMM Incorporated
发明人： Jan Christian Diffenderfer , Yuehchun Claire Cheng
IPC分类号： H03K5/13
CPC分类号： H03K5/13 , G11C7/1072 , H03K5/131 , H03K5/135 , H03K2005/00026 , H03K2005/00247 , H03K2005/00286
摘要： Systems and methods for delaying a signal are described herein. In one embodiment, a method for delaying a signal comprises receiving a first signal edge, and, in response to receiving the first signal edge, counting a number of oscillations of an oscillator. The method also comprises outputting a second signal edge if the number of oscillations reaches a predetermined number. The second signal edge represents a delayed version of the first signal edge.
摘要翻译：本文描述了用于延迟信号的系统和方法。在一个实施例中，一种用于延迟信号的方法包括接收第一信号边缘，并且响应于接收到第一信号边沿，对振荡器的振荡次数进行计数。该方法还包括如果振荡次数达到预定数量则输出第二信号沿。第二信号边缘表示第一信号边沿的延迟版本。

3. 发明申请

US20160329884A1 PROGRAMMABLE DELAY CIRCUIT FOR LOW POWER APPLICATIONS 有权
标题翻译：用于低功率应用的可编程延迟电路
公开(公告)号：US20160329884A1
公开(公告)日：2016-11-10
申请号：US14705733
申请日：2015-05-06
申请人： QUALCOMM, Incorporated
发明人： Shraddha Sridhar , Jan Christian Diffenderfer , Guneet Singh , Michael Thomas Fertsch
IPC分类号： H03K5/06 , H03K5/13
CPC分类号： H03K5/06 , H03K3/0315 , H03K5/131 , H03K2005/00058
摘要： Programmable delay circuits are described herein according to embodiments of the present disclosure. In one embodiment, a delay circuit comprises a plurality of delay stages coupled in series. Each of the delay stages comprises a delay gate on a forward path of the delay circuit, wherein the delay gate is configured to pass or block a signal on the forward path depending on a logic state of a respective select signal. Each of the delay stages also comprises a multiplexer on a return path of the delay circuit, wherein the multiplexer is configured to pass a signal on the return path or route the signal on the forward path to the return path depending on the logic state of the respective select signal. Output logic states of the delay gates and the multiplexers may remain static during a change in the delay setting of the delay circuit to reduce glitch.
摘要翻译：这里根据本公开的实施例描述了可编程延迟电路。在一个实施例中，延迟电路包括串联耦合的多个延迟级。每个延迟级包括在延迟电路的正向路径上的延迟门，其中延迟门配置为根据相应选择信号的逻辑状态在正向路径上传递或阻塞信号。每个延迟级还包括在延迟电路的返回路径上的复用器，其中多路复用器被配置为在返回路径上传递信号或将前向路径上的信号路由到返回路径，这取决于逻辑状态各选择信号。在延迟电路的延迟设置改变期间，延迟门和多路复用器的输出逻辑状态可以保持静态以减少毛刺。

4. 发明授权

US09397646B2 Delay circuit 有权
标题翻译：延时电路
公开(公告)号：US09397646B2
公开(公告)日：2016-07-19
申请号：US14489055
申请日：2014-09-17
申请人： QUALCOMM Incorporated
发明人： Guneet Singh , Yuehchun Claire Cheng , Jan Christian Diffenderfer , Vaishnav Srinivas , Robert Won Chol Kim
IPC分类号： H03K5/13 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C29/02 , H03K5/00
CPC分类号： H03K5/13 , G11C7/1066 , G11C7/1093 , G11C7/222 , G11C11/4076 , G11C29/023 , G11C29/028 , H03K2005/00019
摘要： Systems and methods for delay control are described herein. In one embodiment, a delay circuit comprises a first delay path and a second delay path. The delay circuit also comprises a plurality of switches, wherein each switch is coupled between different points on the first and second delay paths, and each switch is configured to turn on or off in response to a respective one of a plurality of select signals. The delay circuit further comprises a multiplexer having a first input coupled to an output of the first delay path, a second input coupled to an output of the second delay path, and an output coupled to an output of the delay circuit, wherein the multiplexer is configured to selectively couple one of the outputs of the first and second delay paths to the output of the delay circuit in response to a second select signal.
摘要翻译：本文描述了用于延迟控制的系统和方法。在一个实施例中，延迟电路包括第一延迟路径和第二延迟路径。延迟电路还包括多个开关，其中每个开关耦合在第一和第二延迟路径上的不同点之间，并且每个开关被配置为响应于多个选择信号中的相应一个而导通或关断。延迟电路还包括多路复用器，其具有耦合到第一延迟路径的输出的第一输入，耦合到第二延迟路径的输出的第二输入和耦合到延迟电路的输出的输出，其中多路复用器被配置为响应于第二选择信号选择性地将第一和第二延迟路径的输出之一耦合到延迟电路的输出。

5. 发明申请

US20150357017A1 PROGRAMMABLE POWER FOR A MEMORY INTERFACE 有权
标题翻译：用于存储接口的可编程电源
公开(公告)号：US20150357017A1
公开(公告)日：2015-12-10
申请号：US14298730
申请日：2014-06-06
申请人： QUALCOMM Incorporated
发明人： Jan Christian Diffenderfer , Yuehchun Claire Cheng
IPC分类号： G11C11/4076 , H03L7/08
CPC分类号： G11C11/4076 , G11C7/1066 , G11C7/1093 , H03L7/08 , H03L7/0805 , H03L7/0812
摘要： Systems and methods for delay control are described herein. In one embodiment, a delay system comprises a first delay circuit configured to provide a voltage bias to a second delay circuit, wherein the voltage bias controls a delay of the second delay circuit, and to update the voltage bias at an update rate. The delay system also comprises an update controller configured to adjust the update rate of the first delay circuit. For example, the update controller may adjust the update rate based on timing requirements of a memory interface incorporating the delay system. The update rate may be reduced when the timing requirements are more relaxed to reduce power, and may be increased when the timing requirements are tighter.
摘要翻译：本文描述了用于延迟控制的系统和方法。在一个实施例中，延迟系统包括被配置为向第二延迟电路提供电压偏置的第一延迟电路，其中电压偏压控制第二延迟电路的延迟，并以更新速率更新电压偏置。延迟系统还包括被配置为调整第一延迟电路的更新速率的更新控制器。例如，更新控制器可以基于包含延迟系统的存储器接口的定时要求来调整更新速率。当定时要求更加放松以降低功率时，可以减少更新速率，并且当定时要求更紧时可能会增加更新速率。

6. 发明申请

US20150318978A1 CLOCK AND DATA RECOVERY WITH HIGH JITTER TOLERANCE AND FAST PHASE LOCKING 有权
标题翻译：时钟和数据恢复与高耐久性和快速锁相
公开(公告)号：US20150318978A1
公开(公告)日：2015-11-05
申请号：US14268850
申请日：2014-05-02
申请人： QUALCOMM Incorporated
发明人： Yu Song , Jan Christian Diffenderfer , Nan Chen , David Ian West , Paul Lawrence Viani
IPC分类号： H04L7/00 , H03L7/091
CPC分类号： H04L7/0016 , H03L7/0807 , H03L7/091 , H04L7/0083 , H04L7/0338
摘要： Systems and methods for recovering clock and data from a data input signal are disclosed that sample a plurality of clock phase signals with the data input signal to determine a timing relationship between the data input signal and the clock phase signals and use the determined to timing relationship to select one of the clock phase signals to use for sampling the data input signal to produce recovered data. The CDR can include a glitch suppression module to suppress glitches on the clock output signal that could be caused by large instantaneous jitter on the data input signal. A clock and data recovery circuit (CDR) using these methods can quickly lock to a new data input signal and can reliably receive data when there is large instantaneous timing jitter on the data input signal.
摘要翻译：公开了用于从数据输入信号恢复时钟和数据的系统和方法，用数据输入信号对多个时钟相位信号进行采样，以确定数据输入信号和时钟相位信号之间的定时关系，并使用确定的定时关系选择一个时钟相位信号用于采样数据输入信号以产生恢复的数据。 CDR可以包括毛刺抑制模块，以抑制可能由数据输入信号上的大的瞬时抖动引起的时钟输出信号的毛刺。使用这些方法的时钟和数据恢复电路（CDR）可以快速锁定到新的数据输入信号，并且可以在数据输入信号上存在大的瞬时定时抖动时可靠地接收数据。

7. 发明授权

US09520864B2 Delay structure for a memory interface 有权
标题翻译：存储器接口的延迟结构
公开(公告)号：US09520864B2
公开(公告)日：2016-12-13
申请号：US14298742
申请日：2014-06-06
申请人： QUALCOMM Incorporated
发明人： Jan Christian Diffenderfer , Yuehchun Claire Cheng
IPC分类号： H03K5/13 , G11C7/10 , H03K5/135 , H03K5/00
CPC分类号： H03K5/13 , G11C7/1072 , H03K5/131 , H03K5/135 , H03K2005/00026 , H03K2005/00247 , H03K2005/00286
摘要： Systems and methods for delaying a signal are described herein. In one embodiment, a method for delaying a signal comprises receiving a first signal edge, and, in response to receiving the first signal edge, counting a number of oscillations of an oscillator. The method also comprises outputting a second signal edge if the number of oscillations reaches a predetermined number. The second signal edge represents a delayed version of the first signal edge.
摘要翻译：本文描述了用于延迟信号的系统和方法。在一个实施例中，一种用于延迟信号的方法包括接收第一信号边缘，并且响应于接收到第一信号边沿，对振荡器的振荡次数进行计数。该方法还包括如果振荡次数达到预定数量则输出第二信号沿。第二信号边缘表示第一信号边沿的延迟版本。

8. 发明授权

US09490785B1 Programmable delay circuit for low power applications 有权
标题翻译：用于低功率应用的可编程延迟电路
公开(公告)号：US09490785B1
公开(公告)日：2016-11-08
申请号：US14705733
申请日：2015-05-06
申请人： QUALCOMM, Incorporated
发明人： Shraddha Sridhar , Jan Christian Diffenderfer , Guneet Singh , Michael Thomas Fertsch
IPC分类号： H03H11/26 , H03K5/06 , H03K5/13 , H03K5/00
CPC分类号： H03K5/06 , H03K3/0315 , H03K5/131 , H03K2005/00058
摘要： Programmable delay circuits are described herein according to embodiments of the present disclosure. In one embodiment, a delay circuit comprises a plurality of delay stages coupled in series. Each of the delay stages comprises a delay gate on a forward path of the delay circuit, wherein the delay gate is configured to pass or block a signal on the forward path depending on a logic state of a respective select signal. Each of the delay stages also comprises a multiplexer on a return path of the delay circuit, wherein the multiplexer is configured to pass a signal on the return path or route the signal on the forward path to the return path depending on the logic state of the respective select signal. Output logic states of the delay gates and the multiplexers may remain static during a change in the delay setting of the delay circuit to reduce glitch.
摘要翻译：这里根据本公开的实施例描述了可编程延迟电路。在一个实施例中，延迟电路包括串联耦合的多个延迟级。每个延迟级包括在延迟电路的正向路径上的延迟门，其中延迟门配置为根据相应选择信号的逻辑状态在正向路径上传递或阻塞信号。每个延迟级还包括在延迟电路的返回路径上的复用器，其中多路复用器被配置为在返回路径上传递信号或将前向路径上的信号路由到返回路径，这取决于逻辑状态各选择信号。在延迟电路的延迟设置改变期间，延迟门和多路复用器的输出逻辑状态可以保持静态以减少毛刺。

9. 发明申请

US20160079971A1 DELAY CIRCUIT 有权
标题翻译：延时电路
公开(公告)号：US20160079971A1
公开(公告)日：2016-03-17
申请号：US14489055
申请日：2014-09-17
申请人： QUALCOMM Incorporated
发明人： Guneet Singh , Yuehchun Claire Cheng , Jan Christian Diffenderfer , Vaishnav Srinivas , Robert Won Chol Kim
IPC分类号： H03K5/13
CPC分类号： H03K5/13 , G11C7/1066 , G11C7/1093 , G11C7/222 , G11C11/4076 , G11C29/023 , G11C29/028 , H03K2005/00019
摘要： Systems and methods for delay control are described herein. In one embodiment, a delay circuit comprises a first delay path and a second delay path. The delay circuit also comprises a plurality of switches, wherein each switch is coupled between different points on the first and second delay paths, and each switch is configured to turn on or off in response to a respective one of a plurality of select signals. The delay circuit further comprises a multiplexer having a first input coupled to an output of the first delay path, a second input coupled to an output of the second delay path, and an output coupled to an output of the delay circuit, wherein the multiplexer is configured to selectively couple one of the outputs of the first and second delay paths to the output of the delay circuit in response to a second select signal.
摘要翻译：本文描述了用于延迟控制的系统和方法。在一个实施例中，延迟电路包括第一延迟路径和第二延迟路径。延迟电路还包括多个开关，其中每个开关耦合在第一和第二延迟路径上的不同点之间，并且每个开关被配置为响应于多个选择信号中的相应一个而导通或关断。延迟电路还包括多路复用器，其具有耦合到第一延迟路径的输出的第一输入，耦合到第二延迟路径的输出的第二输入和耦合到延迟电路的输出的输出，其中多路复用器是被配置为响应于第二选择信号选择性地将第一和第二延迟路径的输出之一耦合到延迟电路的输出。

10. 发明授权

US09281934B2 Clock and data recovery with high jitter tolerance and fast phase locking 有权
标题翻译：具有高抖动容限和快速锁相的时钟和数据恢复
公开(公告)号：US09281934B2
公开(公告)日：2016-03-08
申请号：US14268850
申请日：2014-05-02
申请人： QUALCOMM Incorporated
发明人： Yu Song , Jan Christian Diffenderfer , Nan Chen , David Ian West , Paul Lawrence Viani
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40 , H03L7/091 , H03L7/08 , H04L7/033
CPC分类号： H04L7/0016 , H03L7/0807 , H03L7/091 , H04L7/0083 , H04L7/0338
摘要： Systems and methods for recovering clock and data from a data input signal are disclosed that sample a plurality of clock phase signals with the data input signal to determine a timing relationship between the data input signal and the clock phase signals and use the determined to timing relationship to select one of the clock phase signals to use for sampling the data input signal to produce recovered data. The CDR can include a glitch suppression module to suppress glitches on the clock output signal that could be caused by large instantaneous jitter on the data input signal. A clock and data recovery circuit (CDR) using these methods can quickly lock to a new data input signal and can reliably receive data when there is large instantaneous timing jitter on the data input signal.
摘要翻译：公开了用于从数据输入信号恢复时钟和数据的系统和方法，用数据输入信号对多个时钟相位信号进行采样，以确定数据输入信号和时钟相位信号之间的定时关系，并使用确定的定时关系选择一个时钟相位信号用于采样数据输入信号以产生恢复的数据。 CDR可以包括毛刺抑制模块，以抑制可能由数据输入信号上的大的瞬时抖动引起的时钟输出信号的毛刺。使用这些方法的时钟和数据恢复电路（CDR）可以快速锁定到新的数据输入信号，并且可以在数据输入信号上存在大的瞬时定时抖动时可靠地接收数据。

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