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1. 发明申请

US20140266357A1 Measure-Based Delay Circuit 有权
标题翻译：基于测量的延迟电路
公开(公告)号：US20140266357A1
公开(公告)日：2014-09-18
申请号：US13831201
申请日：2013-03-14
申请人： QUALCOMM INCORPORATED
发明人： Vaishnav Srinivas , Jan Diffenderfer , Philip Michael Clovis , David Ian West
IPC分类号： H03K5/159
CPC分类号： H03K5/159
摘要： A master measure circuit is disclosed that may select from various nodes on a delay path carrying a signal. The master measure circuit measures the delay for propagation of the signal from one selected node to another selected node and controls an adjustable delay circuit in the delay path accordingly.
摘要翻译：公开了可以在承载信号的延迟路径上的各个节点进行选择的主测量电路。主测量电路测量信号从一个选定节点传播到另一个选定节点的延迟，并相应地控制延迟路径中的可调节延迟电路。

2. 发明授权

US09633698B2 Dynamic control of signaling power based on an error rate 有权
公开(公告)号：US09633698B2
公开(公告)日：2017-04-25
申请号：US14280313
申请日：2014-05-16
申请人： QUALCOMM Incorporated
发明人： Dexter Tamio Chun , Vaishnav Srinivas , David Ian West , Deepti Vijayalakshmi Sriramagiri , Jungwon Suh , Jason Thurston
IPC分类号： G06F11/00 , G11C5/14 , G06F11/07 , G06F11/10 , G01R31/317
CPC分类号： G11C5/147 , G01R31/31709 , G01R31/3171 , G06F11/076 , G06F11/1004
摘要： Writing to and reading from dynamic random access memory (DRAM) by a system on chip (SoC) over a multiphase multilane memory bus has power consumption optimized based on bit error rate (BER) and one or more thresholds. The bit error rate (BER) may be measured and used to control parameters to achieve optimal balance between power consumption and accuracy. The bit error rate (BER) measurement, purposely adding jitter, and checking against the thresholds is performed during normal mission-mode operation with live traffic. Error detection may cover every memory data transaction that has a block of binary data.

3. 发明申请

US20150318978A1 CLOCK AND DATA RECOVERY WITH HIGH JITTER TOLERANCE AND FAST PHASE LOCKING 有权
标题翻译：时钟和数据恢复与高耐久性和快速锁相
公开(公告)号：US20150318978A1
公开(公告)日：2015-11-05
申请号：US14268850
申请日：2014-05-02
申请人： QUALCOMM Incorporated
发明人： Yu Song , Jan Christian Diffenderfer , Nan Chen , David Ian West , Paul Lawrence Viani
IPC分类号： H04L7/00 , H03L7/091
CPC分类号： H04L7/0016 , H03L7/0807 , H03L7/091 , H04L7/0083 , H04L7/0338
摘要： Systems and methods for recovering clock and data from a data input signal are disclosed that sample a plurality of clock phase signals with the data input signal to determine a timing relationship between the data input signal and the clock phase signals and use the determined to timing relationship to select one of the clock phase signals to use for sampling the data input signal to produce recovered data. The CDR can include a glitch suppression module to suppress glitches on the clock output signal that could be caused by large instantaneous jitter on the data input signal. A clock and data recovery circuit (CDR) using these methods can quickly lock to a new data input signal and can reliably receive data when there is large instantaneous timing jitter on the data input signal.
摘要翻译：公开了用于从数据输入信号恢复时钟和数据的系统和方法，用数据输入信号对多个时钟相位信号进行采样，以确定数据输入信号和时钟相位信号之间的定时关系，并使用确定的定时关系选择一个时钟相位信号用于采样数据输入信号以产生恢复的数据。 CDR可以包括毛刺抑制模块，以抑制可能由数据输入信号上的大的瞬时抖动引起的时钟输出信号的毛刺。使用这些方法的时钟和数据恢复电路（CDR）可以快速锁定到新的数据输入信号，并且可以在数据输入信号上存在大的瞬时定时抖动时可靠地接收数据。

4. 发明申请

US20150206854A1 PACKAGE ON PACKAGE (PoP) INTEGRATED DEVICE COMPRISING A REDISTRIBUTION LAYER 有权
标题翻译：包装（PoP）包含重新分配层的集成设备的包装
公开(公告)号：US20150206854A1
公开(公告)日：2015-07-23
申请号：US14268974
申请日：2014-05-02
申请人： QUALCOMM Incorporated
发明人： Ryan David Lane , Charles David Paynter , David Ian West
IPC分类号： H01L25/065 , H01L23/528
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/528 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/32 , H01L24/73 , H01L24/92 , H01L25/0652 , H01L25/0655 , H01L25/105 , H01L2224/04105 , H01L2224/12105 , H01L2224/13025 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/32225 , H01L2224/73259 , H01L2224/73267 , H01L2224/92224 , H01L2224/92244 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06565 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/12042 , H01L2924/1434 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/014 , H01L2924/00
摘要： Some features pertain to an integrated device that includes a first package, a set of interconnects, and a second package. The first package includes a first substrate comprising a first surface and a second surface. The first package includes a redistribution portion comprising a redistribution layer. The first package includes a first die coupled to the first surface of the first substrate. The set of interconnects is coupled to the redistribution portion of the first package. The second package is coupled to the first package through the set of interconnects. The second package includes a second substrate comprising a first surface and a second surface; and a second die coupled to the first surface of the second substrate, where the second die is electrically coupled to the first die through the second substrate of the second package, the set of interconnects, and the redistribution portion of the first package.
摘要翻译：一些特征涉及包括第一封装，一组互连和第二封装的集成器件。第一包装包括包括第一表面和第二表面的第一基底。第一包装包括重分配部分，其包括再分配层。第一封装包括耦合到第一衬底的第一表面的第一裸片。该组互连耦合到第一封装的再分配部分。第二包通过一组互连耦合到第一包装。第二包装包括包括第一表面和第二表面的第二基底; 以及第二管芯，其耦合到所述第二衬底的所述第一表面，其中所述第二管芯通过所述第二封装的所述第二衬底，所述一组互连和所述第一封装的再分配部分电耦合到所述第一管芯。

5. 发明申请

US20140061642A1 METHOD AND APPARATUS FOR ROUTING DIE SIGNALS USING EXTERNAL INTERCONNECTS 有权
标题翻译：使用外部互连路由DIE信号的方法和装置
公开(公告)号：US20140061642A1
公开(公告)日：2014-03-06
申请号：US13802759
申请日：2013-03-14
申请人： QUALCOMM INCORPORATED
发明人： Vaishnav Srinivas , Bernie Jord Yang , Michael Brunolli , David Ian West , Charles David Paynter
IPC分类号： H01L23/00
CPC分类号： H01L24/17 , H01L21/563 , H01L22/32 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/81 , H01L24/83 , H01L2224/02377 , H01L2224/0401 , H01L2224/05558 , H01L2224/0556 , H01L2224/05569 , H01L2224/11462 , H01L2224/13028 , H01L2224/131 , H01L2224/13109 , H01L2224/13116 , H01L2224/13147 , H01L2224/14165 , H01L2224/16225 , H01L2224/16245 , H01L2224/27462 , H01L2224/29028 , H01L2224/29078 , H01L2224/29147 , H01L2224/3012 , H01L2224/3213 , H01L2224/73204 , H01L2224/81193 , H01L2224/81815 , H01L2224/831 , H01L2924/00014 , H01L2924/01322 , H01L2924/07802 , H01L2924/381 , H01L2924/0105 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
摘要： Various aspects of an approach for routing die signals in an interior portion of a die using external interconnects are described herein. The approach provides for contacts coupled to circuits in the interior portion of the die, where the contacts are exposed to an exterior portion of the die. The external interconnects are configured to couple these contacts so that signals from the circuits in the interior portion of the die may be routed externally to the die. In various aspects of the disclosed approach, the external interconnects are protected by a packaging for the die.
摘要翻译：这里描述了使用外部互连在芯片的内部部分中布线管芯信号的方法的各个方面。该方法提供了耦合到管芯内部的电路的触点，其中触点暴露于管芯的外部部分。外部互连被配置为耦合这些触点，使得来自芯片内部部分的电路的信号可以被外部引导到管芯。在所公开的方法的各个方面，外部互连由模具的包装保护。

6. 发明授权

US10224081B2 Dynamic random access memory (DRAM) backchannel communication systems and methods 有权
公开(公告)号：US10224081B2
公开(公告)日：2019-03-05
申请号：US15849463
申请日：2017-12-20
申请人： QUALCOMM Incorporated
发明人： David Ian West , Michael Joseph Brunolli , Dexter Tamio Chun , Vaishnav Srinivas
IPC分类号： G11C7/10 , G06F12/00 , G11C11/4076 , G06F11/10 , G11C11/406
摘要： Dynamic random access memory (DRAM) backchannel communication systems and methods are disclosed. In one aspect, a backchannel communication system allows a DRAM to communicate error correction information and refresh alert information to a System on a Chip (SoC), applications processor (AP), or other memory controller.

7. 发明授权

US10061645B2 Memory array and link error correction in a low power memory sub-system 有权
公开(公告)号：US10061645B2
公开(公告)日：2018-08-28
申请号：US14859063
申请日：2015-09-18
申请人： QUALCOMM Incorporated
发明人： Jungwon Suh , David Ian West
IPC分类号： G06F11/10 , G11C29/52
CPC分类号： G06F11/1068 , G06F11/1048 , G11C29/52
摘要： A method of memory array and link error correction in a low power memory sub-system includes embedding error correction code (ECC) parity bits within unused data mask bits during a normal write operation and during a read operation. The method also includes embedding the ECC parity bits in a mask write data byte corresponding to an asserted data mask bit during a mask write operation.

8. 发明授权

US09947377B2 Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses 有权
公开(公告)号：US09947377B2
公开(公告)日：2018-04-17
申请号：US15622772
申请日：2017-06-14
申请人： QUALCOMM Incorporated
发明人： Vaishnav Srinivas , Michael Joseph Brunolli , Dexter Tamio Chun , David Ian West
IPC分类号： G06F12/02 , G11C7/10 , G11C29/02
CPC分类号： G11C7/1072 , G11C29/022 , G11C29/028
摘要： Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses are disclosed. In one aspect, a first port within a DRAM system is coupled to a second port via a loopback connection. A signal is sent to the first port from a System-on-Chip (SoC), and passed to the second port through the loopback connection. The signal is then returned to the SoC, where it may be examined by a closed-loop engine of the SoC. A result corresponding to a hardware parameter may be recorded, and the process may be repeated until an optimal result for the hardware parameter is achieved at the closed-loop engine. By using a port-to-port loopback configuration, the DRAM system parameters regarding timing, power, and other parameters associated with the DRAM system may be trained more quickly and with lower boot memory usage.

9. 发明授权

US09153560B2 Package on package (PoP) integrated device comprising a redistribution layer 有权
标题翻译：包装（PoP）集成设备包括再分配层
公开(公告)号：US09153560B2
公开(公告)日：2015-10-06
申请号：US14268974
申请日：2014-05-02
申请人： QUALCOMM Incorporated
发明人： Ryan David Lane , Charles David Paynter , David Ian West
IPC分类号： H01L23/34 , H01L25/065 , H01L23/528
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/528 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/32 , H01L24/73 , H01L24/92 , H01L25/0652 , H01L25/0655 , H01L25/105 , H01L2224/04105 , H01L2224/12105 , H01L2224/13025 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/32225 , H01L2224/73259 , H01L2224/73267 , H01L2224/92224 , H01L2224/92244 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06565 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/12042 , H01L2924/1434 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/014 , H01L2924/00
摘要： Some features pertain to an integrated device that includes a first package, a set of interconnects, and a second package. The first package includes a first substrate comprising a first surface and a second surface. The first package includes a redistribution portion comprising a redistribution layer. The first package includes a first die coupled to the first surface of the first substrate. The set of interconnects is coupled to the redistribution portion of the first package. The second package is coupled to the first package through the set of interconnects. The second package includes a second substrate comprising a first surface and a second surface; and a second die coupled to the first surface of the second substrate, where the second die is electrically coupled to the first die through the second substrate of the second package, the set of interconnects, and the redistribution portion of the first package.
摘要翻译：一些特征涉及包括第一封装，一组互连和第二封装的集成器件。第一包装包括包括第一表面和第二表面的第一基底。第一包装包括重分配部分，其包括再分配层。第一封装包括耦合到第一衬底的第一表面的第一裸片。该组互连耦合到第一封装的再分配部分。第二包通过一组互连耦合到第一包装。第二包装包括包括第一表面和第二表面的第二基底; 以及第二管芯，其耦合到所述第二衬底的所述第一表面，其中所述第二管芯通过所述第二封装的所述第二衬底，所述一组互连和所述第一封装的再分配部分电耦合到所述第一管芯。

10. 发明申请

US20150213849A1 PROVIDING MEMORY TRAINING OF DYNAMIC RANDOM ACCESS MEMORY (DRAM) SYSTEMS USING PORT-TO-PORT LOOPBACKS, AND RELATED METHODS, SYSTEMS, AND APPARATUSES 有权
标题翻译：使用端口到端口循环提供动态随机存取存储器（DRAM）系统的存储器训练以及相关方法，系统和装置
公开(公告)号：US20150213849A1
公开(公告)日：2015-07-30
申请号：US14589145
申请日：2015-01-05
申请人： QUALCOMM Incorporated
发明人： Vaishnav Srinivas , Michael Joseph Brunolli , Dexter Tamio Chun , David Ian West
IPC分类号： G11C7/10
CPC分类号： G11C7/1072 , G11C29/022 , G11C29/028
摘要： Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses are disclosed. In one aspect, a first port within a DRAM system is coupled to a second port via a loopback connection. A training signal is sent to the first port from a System-on-Chip (SoC), and passed to the second port through the loopback connection. The training signal is then returned to the SoC, where it may be examined by a closed-loop training engine of the SoC. A training result corresponding to a hardware parameter may be recorded, and the process may be repeated until an optimal result for the hardware parameter is achieved at the closed-loop training engine. By using a port-to-port loopback configuration, the DRAM system parameters regarding timing, power, and other parameters associated with the DRAM system may be trained more quickly and with lower boot memory usage.
摘要翻译：提供使用端口到端口环回的动态随机存取存储器（DRAM）系统的存储器训练以及相关方法，系统和装置。在一个方面，DRAM系统中的第一端口经由环回连接耦合到第二端口。训练信号从片上系统（SoC）发送到第一个端口，并通过环回连接传递到第二个端口。然后训练信号返回到SoC，在那里可以通过SoC的闭环训练引擎检查训练信号。可以记录与硬件参数对应的训练结果，并且可以重复该过程，直到在闭环训练引擎上实现硬件参数的最佳结果。通过使用端口到端口环回配置，关于与DRAM系统相关联的定时，功率和其他参数的DRAM系统参数可以被更快地训练并且具有较低的启动存储器使用。

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