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1. 发明申请

US20150294970A1 CAPACITOR, RESISTOR AND RESISTOR-CAPACITOR COMPONENTS 审中-公开
标题翻译：电容器，电阻器和电阻器电容器组件
公开(公告)号：US20150294970A1
公开(公告)日：2015-10-15
申请号：US14252588
申请日：2014-04-14
申请人： QUALCOMM Incorporated
发明人： Renatas Jakushokas , Robert Won Chol Kim , Vaishnav Srinivas
IPC分类号： H01L27/10 , H01L23/64 , H01L49/02
CPC分类号： H01L28/20 , H01L23/5223 , H01L23/5228 , H01L27/016 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： Capacitor, resistor and resistor-capacitor components are described herein. In one embodiment, a die comprises first and second metal interconnect layers in a back end of line (BEOL) of the die, and an insulator between the first and second metal interconnect layers. The die also comprises a metal-insulator-metal (MIM) capacitor embedded in the insulator, the MIM capacitor comprising a first metal plate, a second metal plate, and a dielectric layer between the first and second metal plates. The die further comprises a metal resistor embedded in the insulator, wherein the metal resistor and the first metal plate of the MIM capacitor are formed from a same metal layer. In one example, the dielectric layer may have a higher dielectric constant than the insulator. In another example, the second metal plate of the MIM capacitor may overlap the metal resistor.
摘要翻译：本文描述了电容器，电阻器和电阻器 - 电容器部件。在一个实施例中，管芯包括管芯的后端（BEOL）中的第一和第二金属互连层以及第一和第二金属互连层之间的绝缘体。模具还包括嵌入在绝缘体中的金属 - 绝缘体 - 金属（MIM）电容器，MIM电容器包括第一金属板，第二金属板和介于第一和第二金属板之间的电介质层。模具还包括嵌入绝缘体中的金属电阻器，其中金属电阻器和MIM电容器的第一金属板由相同的金属层形成。在一个示例中，电介质层可以具有比绝缘体更高的介电常数。在另一示例中，MIM电容器的第二金属板可以与金属电阻器重叠。

2. 发明申请

US20140367757A1 METAL-INSULATOR-METAL CAPACITOR STRUCTURES 有权
标题翻译：金属绝缘体 - 金属电容器结构
公开(公告)号：US20140367757A1
公开(公告)日：2014-12-18
申请号：US13917549
申请日：2013-06-13
申请人： QUALCOMM Incorporated
发明人： Renatas Jakushokas , Vaishnav Srinivas , Robert Won Chol Kim
IPC分类号： H01L49/02
CPC分类号： H01L28/60 , H01G4/002 , H01G4/005 , H01G4/33 , H01G4/385 , H01L23/5223 , H01L27/0805 , H01L28/40 , H01L28/87 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： Capacitor structures capable of providing both low-voltage capacitors and high-voltage capacitors are described herein. In one embodiment, a capacitor structure comprises a low-voltage capacitor and a high-voltage capacitor. The low-voltage capacitor comprises a first electrode formed from a first metal layer, a second electrode formed from a second metal layer, a third electrode formed from a third metal layer, a first dielectric layer between the first and second electrodes, and a second dielectric layer between the second and third electrodes. The high-voltage capacitor comprises a fourth electrode formed from the first metal layer, a fifth electrode formed from the third metal layer, and a third dielectric layer between the fourth and fifth electrodes, wherein the third dielectric layer is thicker than either the first dielectric layer or the second dielectric layer.
摘要翻译：本文描述了能够提供低电压电容器和高压电容器的电容器结构。在一个实施例中，电容器结构包括低压电容器和高压电容器。低电压电容器包括由第一金属层形成的第一电极，由第二金属层形成的第二电极，由第三金属层形成的第三电极，第一和第二电极之间的第一介电层，以及第二电极电介质层在第二和第三电极之间。高压电容器包括由第一金属层形成的第四电极，由第三金属层形成的第五电极和在第四和第五电极之间的第三电介质层，其中第三电介质层比第一电介质层厚层或第二电介质层。

3. 发明授权

US09397646B2 Delay circuit 有权
标题翻译：延时电路
公开(公告)号：US09397646B2
公开(公告)日：2016-07-19
申请号：US14489055
申请日：2014-09-17
申请人： QUALCOMM Incorporated
发明人： Guneet Singh , Yuehchun Claire Cheng , Jan Christian Diffenderfer , Vaishnav Srinivas , Robert Won Chol Kim
IPC分类号： H03K5/13 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C29/02 , H03K5/00
CPC分类号： H03K5/13 , G11C7/1066 , G11C7/1093 , G11C7/222 , G11C11/4076 , G11C29/023 , G11C29/028 , H03K2005/00019
摘要： Systems and methods for delay control are described herein. In one embodiment, a delay circuit comprises a first delay path and a second delay path. The delay circuit also comprises a plurality of switches, wherein each switch is coupled between different points on the first and second delay paths, and each switch is configured to turn on or off in response to a respective one of a plurality of select signals. The delay circuit further comprises a multiplexer having a first input coupled to an output of the first delay path, a second input coupled to an output of the second delay path, and an output coupled to an output of the delay circuit, wherein the multiplexer is configured to selectively couple one of the outputs of the first and second delay paths to the output of the delay circuit in response to a second select signal.
摘要翻译：本文描述了用于延迟控制的系统和方法。在一个实施例中，延迟电路包括第一延迟路径和第二延迟路径。延迟电路还包括多个开关，其中每个开关耦合在第一和第二延迟路径上的不同点之间，并且每个开关被配置为响应于多个选择信号中的相应一个而导通或关断。延迟电路还包括多路复用器，其具有耦合到第一延迟路径的输出的第一输入，耦合到第二延迟路径的输出的第二输入和耦合到延迟电路的输出的输出，其中多路复用器被配置为响应于第二选择信号选择性地将第一和第二延迟路径的输出之一耦合到延迟电路的输出。

4. 发明授权

US09312326B2 Metal-insulator-metal capacitor structures 有权
标题翻译：金属 - 绝缘体 - 金属电容器结构
公开(公告)号：US09312326B2
公开(公告)日：2016-04-12
申请号：US14688807
申请日：2015-04-16
申请人： QUALCOMM, Incorporated
发明人： Renatas Jakushokas , Vaishnav Srinivas , Robert Won Chol Kim
IPC分类号： H01L49/02 , H01L23/522 , H01L27/08 , H01G4/33 , H01G4/38 , H01G4/002 , H01G4/005
CPC分类号： H01L28/60 , H01G4/002 , H01G4/005 , H01G4/33 , H01G4/385 , H01L23/5223 , H01L27/0805 , H01L28/40 , H01L28/87 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： Capacitor structures capable of providing both low-voltage capacitors and high-voltage capacitors are described herein. In one embodiment, a capacitor structure comprises a first electrode formed from a first metal layer, a second electrode formed from a second metal layer, and a third electrode formed from a third metal layer, wherein second and third electrodes are spaced farther apart than the first and second electrodes. The capacitor structure also comprises a first dielectric layer between the first and second electrodes, and a second dielectric layer between the second and third metal layers, wherein the second dielectric layer has a larger thickness than the first dielectric layer. The first electrode is coupled to a first power-supply rail, the third electrode is coupled to a second power-supply rail, and the second power-supply rail has a higher power-supply voltage than the first power-supply rail.
摘要翻译：本文描述了能够提供低电压电容器和高压电容器的电容器结构。在一个实施例中，电容器结构包括由第一金属层形成的第一电极，由第二金属层形成的第二电极和由第三金属层形成的第三电极，其中第二和第三电极间隔比第第一和第二电极。电容器结构还包括在第一和第二电极之间的第一电介质层和在第二和第三金属层之间的第二电介质层，其中第二电介质层具有比第一电介质层更大的厚度。第一电极耦合到第一电源轨道，第三电极耦合到第二电源轨道，并且第二电源轨道具有比第一电源轨道更高的电源电压。

5. 发明申请

US20150221716A1 METAL-INSULATOR-METAL CAPACITOR STRUCTURES 有权
标题翻译：金属绝缘体 - 金属电容器结构
公开(公告)号：US20150221716A1
公开(公告)日：2015-08-06
申请号：US14688807
申请日：2015-04-16
申请人： QUALCOMM, Incorporated
发明人： Renatas Jakushokas , Vaishnav Srinivas , Robert Won Chol Kim
IPC分类号： H01L49/02
CPC分类号： H01L28/60 , H01G4/002 , H01G4/005 , H01G4/33 , H01G4/385 , H01L23/5223 , H01L27/0805 , H01L28/40 , H01L28/87 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： Capacitor structures capable of providing both low-voltage capacitors and high-voltage capacitors are described herein. In one embodiment, a capacitor structure comprises a first electrode formed from a first metal layer, a second electrode formed from a second metal layer, and a third electrode formed from a third metal layer, wherein second and third electrodes are spaced farther apart than the first and second electrodes. The capacitor structure also comprises a first dielectric layer between the first and second electrodes, and a second dielectric layer between the second and third metal layers, wherein the second dielectric layer has a larger thickness than the first dielectric layer. The first electrode is coupled to a first power-supply rail, the third electrode is coupled to a second power-supply rail, and the second power-supply rail has a higher power-supply voltage than the first power-supply rail.
摘要翻译：本文描述了能够提供低电压电容器和高压电容器的电容器结构。在一个实施例中，电容器结构包括由第一金属层形成的第一电极，由第二金属层形成的第二电极和由第三金属层形成的第三电极，其中第二和第三电极间隔比第第一和第二电极。电容器结构还包括在第一和第二电极之间的第一电介质层和在第二和第三金属层之间的第二电介质层，其中第二电介质层具有比第一电介质层更大的厚度。第一电极耦合到第一电源轨，第三电极耦合到第二电源轨，并且第二电源轨具有比第一电源轨更高的电源电压。

6. 发明授权

US09041148B2 Metal-insulator-metal capacitor structures 有权
标题翻译：金属 - 绝缘体 - 金属电容器结构
公开(公告)号：US09041148B2
公开(公告)日：2015-05-26
申请号：US13917549
申请日：2013-06-13
申请人： QUALCOMM Incorporated
发明人： Renatas Jakushokas , Vaishnav Srinivas , Robert Won Chol Kim
IPC分类号： H01L29/00 , H01L49/02 , H01L23/522 , H01L27/08 , H01G4/33 , H01G4/38 , H01G4/002
CPC分类号： H01L28/60 , H01G4/002 , H01G4/005 , H01G4/33 , H01G4/385 , H01L23/5223 , H01L27/0805 , H01L28/40 , H01L28/87 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： Capacitor structures capable of providing both low-voltage capacitors and high-voltage capacitors are described herein. In one embodiment, a capacitor structure comprises a low-voltage capacitor and a high-voltage capacitor. The low-voltage capacitor comprises a first electrode formed from a first metal layer, a second electrode formed from a second metal layer, a third electrode formed from a third metal layer, a first dielectric layer between the first and second electrodes, and a second dielectric layer between the second and third electrodes. The high-voltage capacitor comprises a fourth electrode formed from the first metal layer, a fifth electrode formed from the third metal layer, and a third dielectric layer between the fourth and fifth electrodes, wherein the third dielectric layer is thicker than either the first dielectric layer or the second dielectric layer.
摘要翻译：本文描述了能够提供低电压电容器和高压电容器的电容器结构。在一个实施例中，电容器结构包括低压电容器和高压电容器。低电压电容器包括由第一金属层形成的第一电极，由第二金属层形成的第二电极，由第三金属层形成的第三电极，第一和第二电极之间的第一介电层，以及第二电极电介质层在第二和第三电极之间。高压电容器包括由第一金属层形成的第四电极，由第三金属层形成的第五电极和在第四和第五电极之间的第三电介质层，其中第三电介质层比第一电介质层厚层或第二电介质层。

7. 发明申请

US20160079971A1 DELAY CIRCUIT 有权
标题翻译：延时电路
公开(公告)号：US20160079971A1
公开(公告)日：2016-03-17
申请号：US14489055
申请日：2014-09-17
申请人： QUALCOMM Incorporated
发明人： Guneet Singh , Yuehchun Claire Cheng , Jan Christian Diffenderfer , Vaishnav Srinivas , Robert Won Chol Kim
IPC分类号： H03K5/13
CPC分类号： H03K5/13 , G11C7/1066 , G11C7/1093 , G11C7/222 , G11C11/4076 , G11C29/023 , G11C29/028 , H03K2005/00019
摘要： Systems and methods for delay control are described herein. In one embodiment, a delay circuit comprises a first delay path and a second delay path. The delay circuit also comprises a plurality of switches, wherein each switch is coupled between different points on the first and second delay paths, and each switch is configured to turn on or off in response to a respective one of a plurality of select signals. The delay circuit further comprises a multiplexer having a first input coupled to an output of the first delay path, a second input coupled to an output of the second delay path, and an output coupled to an output of the delay circuit, wherein the multiplexer is configured to selectively couple one of the outputs of the first and second delay paths to the output of the delay circuit in response to a second select signal.
摘要翻译：本文描述了用于延迟控制的系统和方法。在一个实施例中，延迟电路包括第一延迟路径和第二延迟路径。延迟电路还包括多个开关，其中每个开关耦合在第一和第二延迟路径上的不同点之间，并且每个开关被配置为响应于多个选择信号中的相应一个而导通或关断。延迟电路还包括多路复用器，其具有耦合到第一延迟路径的输出的第一输入，耦合到第二延迟路径的输出的第二输入和耦合到延迟电路的输出的输出，其中多路复用器是被配置为响应于第二选择信号选择性地将第一和第二延迟路径的输出之一耦合到延迟电路的输出。

8. 发明授权

US09032358B2 Integrated circuit floorplan for compact clock distribution 有权
标题翻译：集成电路平面图，实现紧凑的时钟分配
公开(公告)号：US09032358B2
公开(公告)日：2015-05-12
申请号：US13787647
申请日：2013-03-06
申请人： QUALCOMM Incorporated
发明人： Vaishnav Srinivas , Robert Won Chol Kim , Philip Michael Clovis , David Ian West
IPC分类号： G06F17/50 , H01L27/02
CPC分类号： H01L27/0207 , G06F17/5072 , G06F2217/40
摘要： An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.
摘要翻译：集成电路包括核心逻辑和围绕核心逻辑的外围设置的多个接口块。多个输入或输出（I / O）电路被分配给多个接口块中的一个。 I / O电路包括耦合到集成电路以外的器件的外部I / O电路和耦合到集成电路的内部I / O电路。每个接口块包括设置在接口块的第一侧上的第一多个I / O电路和设置在接口块的第二侧上的第二多个I / O电路。每个接口块还包括用于在第一多个I / O电路和第二多个I / O电路之间的接口块的接口逻辑，以及逻辑集线器，其包括驱动启动逻辑和捕获逻辑的最小长度的时钟分配形成接口块的I / O电路。

9. 发明申请

US20140253228A1 INTEGRATED CIRCUIT FLOORPLAN FOR COMPACT CLOCK DISTRIBUTION 有权
标题翻译：用于紧凑时钟分配的集成电路FLOORPLAN
公开(公告)号：US20140253228A1
公开(公告)日：2014-09-11
申请号：US13787647
申请日：2013-03-06
申请人： QUALCOMM INCORPORATED
发明人： Vaishnav Srinivas , Robert Won Chol Kim , Philip Michael Clovis , David Ian West
IPC分类号： H01L27/02
CPC分类号： H01L27/0207 , G06F17/5072 , G06F2217/40
摘要： An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.
摘要翻译：集成电路包括核心逻辑和围绕核心逻辑的外围设置的多个接口块。多个输入或输出（I / O）电路被分配给多个接口块中的一个。 I / O电路包括耦合到集成电路以外的器件的外部I / O电路和耦合到集成电路的内部I / O电路。每个接口块包括设置在接口块的第一侧上的第一多个I / O电路和设置在接口块的第二侧上的第二多个I / O电路。每个接口块还包括用于在第一多个I / O电路和第二多个I / O电路之间的接口块的接口逻辑，以及逻辑集线器，其包括驱动启动逻辑和捕获逻辑的最小长度的时钟分配形成接口块的I / O电路。

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