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1. 发明授权

US09787296B1 Delay circuit 有权
公开(公告)号：US09787296B1
公开(公告)日：2017-10-10
申请号：US15234954
申请日：2016-08-11
申请人： SK hynix Inc.
发明人： Sung-Eun Lee , Kyung-Hoon Kim , Myeong-Jae Park , Woo-Yeol Shin , Han-Kyu Chi , Yong-Ju Kim
IPC分类号： H03K5/159 , H03K21/38 , H03K5/00
CPC分类号： H03K5/159 , H03K5/131 , H03K21/38 , H03K2005/00078 , H03K2005/00247 , H03K2005/00273
摘要： A delay circuit includes: a plurality of delay units that are serially coupled with each other in a form of loop and sequentially delay an input signal of the delay circuit; an input control unit that selects a delay unit to receive the input signal of the delay circuit among the plurality of the delay units; and an output control unit that controls an output signal of a predetermined delay unit among the plurality of the delay units to be outputted as an output signal of the delay circuit, when the output signal of the predetermined delay unit is enabled N times, where N is an integer equal to or greater than 0.

2. 发明申请

US20170272063A1 DELAY CIRCUIT 有权
公开(公告)号：US20170272063A1
公开(公告)日：2017-09-21
申请号：US15234954
申请日：2016-08-11
申请人： SK hynix Inc.
发明人： Sung-Eun LEE , Kyung-Hoon KIM , Myeong-Jae PARK , Woo-Yeol SHIN , Han-Kyu CHI , Yong-Ju KIM
IPC分类号： H03K5/159 , H03K21/38
CPC分类号： H03K5/159 , H03K5/131 , H03K21/38 , H03K2005/00078 , H03K2005/00247 , H03K2005/00273
摘要： A delay circuit includes: a plurality of delay units that are serially coupled with each other in a form of loop and sequentially delay an input signal of the delay circuit; an input control unit that selects a delay unit to receive the input signal of the delay circuit among the plurality of the delay units; and an output control unit that controls an output signal of a predetermined delay unit among the plurality of the delay units to be outputted as an output signal of the delay circuit, when the output signal of the predetermined delay unit is enabled N times, where N is an integer equal to or greater than 0.

3. 发明授权

US09740407B2 Clock mode determination in a memory system 有权
公开(公告)号：US09740407B2
公开(公告)日：2017-08-22
申请号：US15378650
申请日：2016-12-14
申请人： Conversant Intellectual Property Management Inc.
发明人： Peter B. Gillingham , Graham Allan
IPC分类号： G11C8/00 , G06F3/06 , G11C16/32 , G11C14/00 , G11C16/10 , G11C16/28
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0688 , G06F13/1694 , G11C7/1045 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C14/0018 , G11C16/0483 , G11C16/10 , G11C16/28 , G11C16/32 , H03K2005/00247 , Y02D10/14
摘要： A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

4. 发明授权

US09552889B2 Clock mode determination in a memory system 有权
标题翻译：存储器系统中的时钟模式确定
公开(公告)号：US09552889B2
公开(公告)日：2017-01-24
申请号：US15183162
申请日：2016-06-15
申请人： CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
发明人： Peter B. Gillingham , Graham Allan
IPC分类号： G11C8/00 , G11C16/32 , G11C16/04 , G11C16/10
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0688 , G06F13/1694 , G11C7/1045 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C14/0018 , G11C16/0483 , G11C16/10 , G11C16/28 , G11C16/32 , H03K2005/00247 , Y02D10/14
摘要： A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.
摘要翻译：描述了用于存储器件的时钟模式配置电路。存储器系统包括彼此串行连接的任何数量的存储器件，其中每个存储器件接收时钟信号。可以将时钟信号并行地提供给所有存储器件，或者通过公共时钟输入从存储器件到存储器器件串行提供。每个存储器件中的时钟模式配置电路被设置为用于接收并行时钟信号的并行模式，以及用于从现有存储器件接收源同步时钟信号的串行模式。根据设置的工作模式，数据输入电路将被配置为相应的数据信号格式，相应的时钟输入电路将被启用或禁用。通过感测提供给每个存储器件的参考电压的电压电平来设置并联模式和串行模式。

5. 发明申请

US20160293265A1 CLOCK MODE DETERMINATION IN A MEMORY SYSTEM 审中-公开
公开(公告)号：US20160293265A1
公开(公告)日：2016-10-06
申请号：US15183162
申请日：2016-06-15
申请人： CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
发明人： Peter B. GILLINGHAM , Graham ALLAN
IPC分类号： G11C16/32 , G11C16/10 , G11C16/04
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0688 , G06F13/1694 , G11C7/1045 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C14/0018 , G11C16/0483 , G11C16/10 , G11C16/28 , G11C16/32 , H03K2005/00247 , Y02D10/14
摘要： A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

6. 发明授权

US09141088B1 Time-to-digital converter and operation method thereof 有权
标题翻译：时 - 数转换器及其操作方法
公开(公告)号：US09141088B1
公开(公告)日：2015-09-22
申请号：US14488302
申请日：2014-09-17
申请人： Winbond Electronics Corp.
发明人： Chen-Yi Lee
IPC分类号： G04F10/00 , H03L7/08
CPC分类号： G04F10/005 , H03K2005/00247 , H03L7/08
摘要： A time-to-digital converter adopted to transform an enabled time of a time signal into an output data and an operation method thereof are provided. The operation method includes the following steps: providing a counter clock signal by a digital phase locked loop according to a reference clock signal; providing a counter result by a counter unit according to the counter clock signal and the time signal; comparing the enabled time of the time signal with a minimum time to provide a comparison result by a comparator unit; and outputting the counter result as the output data according to the comparison result when the enabled time of the time signal is longer than the minimum time.
摘要翻译：提供了一种用于将时间信号的使能时间转换为输出数据的时间 - 数字转换器及其操作方法。该操作方法包括以下步骤：根据参考时钟信号通过数字锁相环提供计数器时钟信号; 根据计数器时钟信号和时间信号由计数器单元提供计数器结果; 将所述时间信号的使能时间与最小时间进行比较，以通过比较器单元提供比较结果; 并且当所述时间信号的使能时间长于所述最小时间时，根据所述比较结果输出所述计数器结果作为所述输出数据。

7. 发明申请

US20150255167A1 CLOCK MODE DETERMINATION IN A MEMORY SYSTEM 有权
公开(公告)号：US20150255167A1
公开(公告)日：2015-09-10
申请号：US14720317
申请日：2015-05-22
申请人： CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
发明人： Peter B. GILLINGHAM , Graham ALLAN
IPC分类号： G11C16/32 , G11C16/28
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0688 , G06F13/1694 , G11C7/1045 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C14/0018 , G11C16/0483 , G11C16/10 , G11C16/28 , G11C16/32 , H03K2005/00247 , Y02D10/14
摘要： A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

8. 发明授权

US09042199B2 Clock mode determination in a memory system 有权
标题翻译：存储器系统中的时钟模式确定
公开(公告)号：US09042199B2
公开(公告)日：2015-05-26
申请号：US14491440
申请日：2014-09-19
申请人： CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
发明人： Peter B. Gillingham , Graham Allan
IPC分类号： G11C8/00 , G11C16/10
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0688 , G06F13/1694 , G11C7/1045 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C14/0018 , G11C16/0483 , G11C16/10 , G11C16/28 , G11C16/32 , H03K2005/00247 , Y02D10/14
摘要： A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.
摘要翻译：描述了用于存储器件的时钟模式配置电路。存储器系统包括彼此串行连接的任何数量的存储器件，其中每个存储器件接收时钟信号。可以将时钟信号并行地提供给所有存储器件，或者通过公共时钟输入从存储器件到存储器器件串行提供。每个存储器件中的时钟模式配置电路被设置为用于接收并行时钟信号的并行模式，以及用于从现有存储器件接收源同步时钟信号的串行模式。根据设置的工作模式，数据输入电路将被配置为相应的数据信号格式，相应的时钟输入电路将被启用或禁用。通过感测提供给每个存储器件的参考电压的电压电平来设置并联模式和串行模式。

9. 发明申请

US20140009197A1 SELF-ADJUSTING DUTY CYCLE TUNER 有权
标题翻译：自调整占空比调谐器
公开(公告)号：US20140009197A1
公开(公告)日：2014-01-09
申请号：US13544588
申请日：2012-07-09
申请人： Takeo Yasuda
发明人： Takeo Yasuda
IPC分类号： H03K3/017
CPC分类号： H03K3/017 , H03K2005/00247
摘要： A duty cycle tuner measures high and low periods of a signal, calculates an actual duty cycle, generates duty control signals based on the actual duty cycle and a desired duty cycle, and adjusts the duty cycle responsive to the duty control signals. The high and low periods are measured using high-speed counters to provide a high count for the high period and a low count for the low period. The actual duty cycle value is then computed from the high and low counts, and compared to the desired duty cycle value to generate increment and decrement signals which may be positive or zero, to increase, decrease or maintain the actual duty cycle. In this manner, even if the high and low counts are subject to variations due to process, temperature or power supply voltage, their ratio is independent of such variations, so the tuner is immune to those effects.
摘要翻译：占空比调谐器测量信号的高周期和低周期，计算实际占空比，基于实际占空比和期望的占空比产生占空比控制信号，并响应占空比控制信号调整占空比。使用高速计数器测量高周期和低周期，以提供高周期的高计数和低周期的低计数。然后从高和低计数计算实际占空比值，并与期望的占空比值进行比较，以生成可以为正或零的增量和减量信号，以增加，减少或维持实际占空比。以这种方式，即使高低计数由于处理，温度或电源电压而发生变化，它们的比例也与这种变化无关，所以调谐器不受这些影响。

10. 发明授权

US08432767B2 Clock mode determination in a memory system 有权
公开(公告)号：US08432767B2
公开(公告)日：2013-04-30
申请号：US13006005
申请日：2011-01-13
申请人： Peter B. Gillingham , Graham Allan
发明人： Peter B. Gillingham , Graham Allan
IPC分类号： G11C8/00
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0688 , G06F13/1694 , G11C7/1045 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C14/0018 , G11C16/0483 , G11C16/10 , G11C16/28 , G11C16/32 , H03K2005/00247 , Y02D10/14
摘要： A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

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