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1. 发明授权

US07895556B2 Method for optimizing an unrouted design to reduce the probability of timing problems due to coupling and long wire routes 有权
标题翻译：用于优化未路由设计以减少由于耦合和长线路引起的定时问题的概率的方法
公开(公告)号：US07895556B2
公开(公告)日：2011-02-22
申请号：US11942990
申请日：2007-11-20
申请人： Pooja M. Kotecha , David J. Hathaway , Louise H. Trevillyan
发明人： Pooja M. Kotecha , David J. Hathaway , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method and a system is described to predict effects of coupling on timing by estimating the delta delay and delta slack that can occur due to coupling on any net, for optimization to minimize the sensitivity of slack to potential coupling violations. The invention protects against other unexpected increases in effective load capacitance, such as those due to unexpectedly long wire routes. It also estimates the delay impact of a single ‘fault’ or ‘event’, such as a coupling event or unexpectedly long wires routes, including the impact of slew propagation.
摘要翻译：描述了一种方法和系统，以通过估计由于任何网络上的耦合而可能发生的增量延迟和增量松弛来预测耦合对定时的影响，以便优化以使松弛对潜在耦合违规的灵敏度最小化。本发明可防止有效负载电容的其他意外增加，例如由于意外长的电线路由引起的负载电容。它还估计单个“故障”或“事件”的延迟影响，例如耦合事件或意外长电线路由，包括转换传播的影响。

2. 发明申请

US20090132982A1 METHOD FOR OPTIMIZING AN UNROUTED DESIGN TO REDUCE THE PROBABILITY OF TIMING PROBLEMS DUE TO COUPLING AND LONG WIRE ROUTES 有权
标题翻译：优化设计的方法，以减少因耦合和长途径导致的时序问题的可行性
公开(公告)号：US20090132982A1
公开(公告)日：2009-05-21
申请号：US11942990
申请日：2007-11-20
申请人： Pooja M. Kotecha , David J. Hathaway , Louise H. Trevillyan
发明人： Pooja M. Kotecha , David J. Hathaway , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method and a system is described to predict effects of coupling on timing by estimating the delta delay and delta slack that can occur due to coupling on any net, for optimization to minimize the sensitivity of slack to potential coupling violations. The invention protects against other unexpected increases in effective load capacitance, such as those due to unexpectedly long wire routes. It also estimates the delay impact of a single ‘fault’ or ‘event’, such as a coupling event or unexpectedly long wires routes, including the impact of slew propagation.
摘要翻译：描述了一种方法和系统，以通过估计由于任何网络上的耦合而可能发生的增量延迟和增量松弛来预测耦合对定时的影响，以便优化以使松弛对潜在耦合违规的灵敏度最小化。本发明可防止有效负载电容的其他意外增加，例如由于意外长的电线路由引起的负载电容。它还估计单个“故障”或“事件”的延迟影响，例如耦合事件或意外长电线路由，包括转换传播的影响。

3. 发明申请

US20100180242A1 Method and system for efficient validation of clock skews during hierarchical static timing analysis 有权
标题翻译：在分层静态时序分析期间有效验证时钟偏差的方法和系统
公开(公告)号：US20100180242A1
公开(公告)日：2010-07-15
申请号：US12351944
申请日：2009-01-12
申请人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Pooja M. Kotecha
发明人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Pooja M. Kotecha
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and a system for validating clock skews during a hierarchical static timing analysis of a chip or multi-chip package. Each pair of clock inputs of a hierarchical module bounds the allowable clock skew, creating new relative constraints on clock input arrival times propagated to those clock inputs. One embodiment is based on asserted arrival times and a maximum of computed slack values at said clock inputs, while a second embodiment is based on asserted arrival times and a minimum of downstream test slack values. The method further converts module clock assertions into a set of relative timing constraints to allow a hierarchical timing sign-off even in circumstances where absolute timing arrivals are not totally known at the time of module analysis.
摘要翻译：一种用于在芯片或多芯片封装的分层静态时序分析期间验证时钟偏移的方法和系统。分层模块的每对时钟输入限制了可允许的时钟偏移，从而在传播到这些时钟输入的时钟输入到达时间上产生新的相对约束。一个实施例基于确定的到达时间和在所述时钟输入处的计算的松弛值的最大值，而第二实施例基于确定的到达时间和最小的下游测试松弛值。该方法还将模块时钟断言转换成一组相对时序约束，以便即使在模块分析时绝对定时到达不是完全知道的情况下也允许分层定时签发。

4. 发明授权

US07987440B2 Method and system for efficient validation of clock skews during hierarchical static timing analysis 有权
标题翻译：在分层静态时序分析期间有效验证时钟偏差的方法和系统
公开(公告)号：US07987440B2
公开(公告)日：2011-07-26
申请号：US12351944
申请日：2009-01-12
申请人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Pooja M. Kotecha
发明人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Pooja M. Kotecha
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and a system for validating clock skews during a hierarchical static timing analysis of a chip or multi-chip package. Each pair of clock inputs of a hierarchical module bounds the allowable clock skew, creating new relative constraints on clock input arrival times propagated to those clock inputs. One embodiment is based on asserted arrival times and a maximum of computed slack values at said clock inputs, while a second embodiment is based on asserted arrival times and a minimum of downstream test slack values. The method further converts module clock assertions into a set of relative timing constraints to allow a hierarchical timing sign-off even in circumstances where absolute timing arrivals are not totally known at the time of module analysis.
摘要翻译：一种用于在芯片或多芯片封装的分层静态时序分析期间验证时钟偏移的方法和系统。分层模块的每对时钟输入限制了可允许的时钟偏移，从而在传播到这些时钟输入的时钟输入到达时间上产生新的相对约束。一个实施例基于确定的到达时间和在所述时钟输入处的计算的松弛值的最大值，而第二实施例基于确定的到达时间和最小的下游测试松弛值。该方法还将模块时钟断言转换成一组相对时序约束，以便即使在模块分析时绝对定时到达不是完全知道的情况下也允许分层定时签发。

5. 发明授权

US07225421B2 Clock tree distribution generation by determining allowed placement regions for clocked elements 有权
标题翻译：通过确定时钟元素的允许放置区域来生成时钟树分布
公开(公告)号：US07225421B2
公开(公告)日：2007-05-29
申请号：US10905970
申请日：2005-01-28
申请人： William R. Migatz , Paul M. Campbell , David J. Hathaway , David S. Kung , Ruchir Puri , Louise H. Trevillyan
发明人： William R. Migatz , Paul M. Campbell , David J. Hathaway , David S. Kung , Ruchir Puri , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F1/10
摘要： A method, system and program product are described for generating a clock distribution network on an integrated circuit by determining an allowable placement region for each of a set of clock tree leaf elements in the integrated circuit. This allowable placement region is generated by determining and intersecting a set of sub-regions under different constraints, each of which identifies an area in which the clock tree leaf element is placed to satisfy the respective constraint. Constraints for which sub-regions are determined include timing constraints in the form of slacks and congestion constraints. After allowable placement regions have been determined, the clock tree leaf elements are clustered, and each clock tree leaf element is placed at a location within its allowable placement region which minimizes some cost function for that clustering.
摘要翻译：描述了一种方法，系统和程序产品，用于通过为集成电路中的一组时钟树叶元素中的每一个确定允许的布局区域来在集成电路上生成时钟分配网络。通过确定和相交不同约束下的一组子区域来生成该允许的放置区域，每个子区域标识其中放置时钟树叶元素的区域以满足相应的约束。确定子区域的约束包括松弛和拥挤约束形式的时间约束。在确定了允许的放置区域之后，时钟树叶元素被聚集，并且每个时钟树叶元素被放置在其允许的放置区域内的位置，这使得该聚类的一些成本函数最小化。

6. 发明授权

US08607176B2 Delay model construction in the presence of multiple input switching events 失效
标题翻译：存在多个输入切换事件的延迟模型构建
公开(公告)号：US08607176B2
公开(公告)日：2013-12-10
申请号：US13088688
申请日：2011-04-18
申请人： Jeffrey P. Soreff , Bhavana Agrawal , David J. Hathaway
发明人： Jeffrey P. Soreff , Bhavana Agrawal , David J. Hathaway
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031
摘要： A method for constructing delay rules which include the effects of MIS simulations for static timing analysis with reduced cost. The present method includes constructing skew windows for applying MIS penalties purely from SIS data, and scales the MIS penalties during rule use based upon how closely the skews in the use case approach the edge of the skew window. The method applies both to timing rule construction for a library of circuits and to timing rule construction for macros where only part of the circuits in the macro may be sensitive to skew between macro inputs.
摘要翻译：一种用于构建延迟规则的方法，其中包括MIS模拟对静态时序分析的影响，降低成本。本方法包括构建歪斜窗口，用于纯粹来自SIS数据的MIS惩罚，并根据使用案例中的倾斜度接近偏斜窗口的边缘来缩小规则使用期间的MIS惩罚。该方法既适用于电路库的定时规则构造，也适用于宏的定时规则构造，其中宏中仅部分电路可能对宏输入之间的偏移敏感。

7. 发明授权

US08381150B2 Method for performing a parallel static timing analysis using thread-specific sub-graphs 有权
标题翻译：使用线程特定子图执行并行静态时序分析的方法
公开(公告)号：US08381150B2
公开(公告)日：2013-02-19
申请号：US13151295
申请日：2011-06-02
申请人： Vladimir Zolotov , David J. Hathaway , Kerim Kalafala , Mark A. Lavin , Peihua Qi
发明人： Vladimir Zolotov , David J. Hathaway , Kerim Kalafala , Mark A. Lavin , Peihua Qi
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F8/20 , G06F2217/84
摘要： A method for efficient multithreaded analysis of a timing graph is described. The method is applicable to multithreaded common path pessimism removal, critical path traversing for timing report generation, and other types of analysis requiring traversal of sub-graphs of timing graph. In order to achieve high efficiency and scalability for parallel multithreaded execution, the number of access locks is minimized. One parent computation thread and multiple child threads are employed. The parent computational thread identifies the tasks for analysis and distributes them among child threads. Each child thread identifies a sub-graph to be analyzed, creates a thread-specific replica of the identified sub-graph, and performs the analysis required. After completing the analysis, the child thread transfers the results back to the main timing graph and waits for next task. As all data structures of each child thread are accessed only by the child thread owing them, no access locks are required for construction and processing of thread specific graph replica of the timing sub-graph. The construction of each thread specific graph replica is performed by the child thread without locking the main timing graph data structures. Access locks are used only for transferring results of the analysis back to the main timing graph where the results computed by all child threads are combined together.
摘要翻译：描述了一种用于定时图的有效多线程分析的方法。该方法适用于多线程公共路径悲观消除，定时报告生成的关键路径遍历以及需要遍历时序图子图的其他类型分析。为了实现并行多线程执行的高效率和可扩展性，访问锁的数量最小化。使用一个父计算线程和多个子线程。父计算线程识别用于分析的任务，并在子线程之间分配它们。每个子线程标识要分析的子图，创建所识别的子图的线程特定副本，并执行所需的分析。完成分析后，子线程将结果传回主时序图，等待下一个任务。由于每个子线程的所有数据结构仅由它们的子线程访问，所以不需要访问锁来构建和处理定时子图的线程特定图形副本。每个线程特定图形副本的构造由子线程执行，而不锁定主时序图数据结构。访问锁仅用于将分析结果传回主时序图，其中所有子线程计算的结果组合在一起。

8. 发明授权

US08239794B2 System and method for estimating leakage current of an electronic circuit 有权
标题翻译：用于估计电子电路的漏电流的系统和方法
公开(公告)号：US08239794B2
公开(公告)日：2012-08-07
申请号：US12568985
申请日：2009-09-29
申请人： Bhavna Agrawal , David J. Hathaway , Pravin P. Kamdar , Karl K. Moody, III , Peng Peng , David W. Winston
发明人： Bhavna Agrawal , David J. Hathaway , Pravin P. Kamdar , Karl K. Moody, III , Peng Peng , David W. Winston
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/5022
摘要： Disclosed are embodiments of a system and of an associated method for estimating the leakage current of an electronic circuit. The embodiments analyze a layout of an electronic circuit in order to identify all driven and non-driven nets within the electronic circuit, to identify all of the driven net-bounded partitions within the electronic circuit (based on the driven and non-driven nets), and to identify, for each driven net-bounded partition, all possible states of the electronic circuit that can leak. Then, using this information, the embodiments estimate the leakage current of the electronic circuit. This is accomplished by first determining, for each state of each driven net-bounded partition, a leakage current of the driven net-bounded partition and a probability that the state will occur in the driven net-bounded partition during operation of the electronic circuit. Then, for each state of each driven net-bounded partition, the leakage current of the driven net-bounded partition and the state probability are multiplied together. The results are then aggregated.
摘要翻译：公开了用于估计电子电路的漏电流的系统和相关方法的实施例。实施例分析电子电路的布局，以便识别电子电路内的所有被驱动和非驱动的网络，以识别电子电路内的所有被驱动的网络边界的分区（基于被驱动和非驱动的网络）并且为每个被驱动的有界分区识别可能泄漏的电子电路的所有可能的状态。然后，使用该信息，实施例估计电子电路的漏电流。这是通过首先确定每个受驱动网络边界分区的每个状态的驱动网络边界分区的泄漏电流以及在电子电路运行期间该状态将在该被驱动的有界分区中发生的概率来实现的。然后，对于每个被驱动的有界分区的每个状态，驱动的有界分区的泄漏电流和状态概率相乘。然后汇总结果。

9. 发明授权

US08056038B2 Method for efficiently checkpointing and restarting static timing analysis of an integrated circuit chip 有权
标题翻译：用于有效地检查和重新启动集成电路芯片的静态时序分析的方法
公开(公告)号：US08056038B2
公开(公告)日：2011-11-08
申请号：US12354360
申请日：2009-01-15
申请人： Kerim Kalafala , Hemlata Gupta , David J. Hathaway , Jeffrey G. Hemmett
发明人： Kerim Kalafala , Hemlata Gupta , David J. Hathaway , Jeffrey G. Hemmett
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for loading checkpoint timing in an environment where the boundary arrival times, slews, required arrival times, or loads differ from the checkpoint run. A timing checkpoint file generated for one or more hierarchical modules, during which each input is assigned a unique phase tag. The association of unique phase tags allows subsequent restart analyses to efficiently adjust the checkpoint timing in relation to the restart timing environment. In the restart run, one or more such checkpoint files is read, during which an initial propagation of arrival, required arrivals and slew times are performed, followed by a local re-update based on adjusted arrival times and the required arrival times. Finally, if multiple hierarchical modules are updated, a global recalculation of timing values is performed based on a slack change threshold in order to determine whether any new timing failures have been introduced.
摘要翻译：在边界到达时间，转数，所需到达时间或负载与检查点运行不同的环境中加载检查点定时的方法。为一个或多个分层模块生成的定时检查点文件，在此期间为每个输入分配唯一的相位标签。独特相位标签的关联允许随后的重新启动分析以有效地调整与重启定时环境相关的检查点定时。在重新启动运行中，读取一个或多个这样的检查点文件，在此期间，执行到达的初始传播，所需到达和转换时间，然后基于调整的到达时间和所需的到达时间进行本地重新更新。最后，如果更新了多个分级模块，则基于松弛变化阈值执行定时值的全局重新计算，以便确定是否引入了任何新的定时故障。

10. 发明授权

US08056035B2 Method and system for analyzing cross-talk coupling noise events in block-based statistical static timing 有权
标题翻译：在基于块的统计静态时序中分析串扰耦合噪声事件的方法和系统
公开(公告)号：US08056035B2
公开(公告)日：2011-11-08
申请号：US12132636
申请日：2008-06-04
申请人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Gregory M. Schaeffer , Chandramouli Visweswariah
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Gregory M. Schaeffer , Chandramouli Visweswariah
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： A method of performing statistical timing analysis of a logic design, including effects of signal coupling, includes performing a deterministic analysis to determine deterministic coupling information for at least one aggressor/victim net pair of the logic design. Additionally, the method includes performing a statistical timing analysis in which the deterministic coupling information for the at least one aggressor/victim net pair is combined with statistical values of the statistical timing analysis to determine a statistical effective capacitance of a victim of the aggressor/victim net pair. Furthermore, the method includes using the statistical effective capacitance to determine timing data used in the statistical timing analysis.
摘要翻译：执行包括信号耦合效应的逻辑设计的统计定时分析的方法包括执行确定性分析以确定逻辑设计的至少一个攻击者/受害者网对的确定性耦合信息。另外，该方法包括执行统计时序分析，其中至少一个攻击者/受害者网络对的确定性耦合信息与统计时间分析的统计值相结合，以确定攻击者/受害者的受害者的统计有效电容净对。此外，该方法包括使用统计有效电容来确定在统计时序分析中使用的定时数据。

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