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1. 发明授权

US07987440B2 Method and system for efficient validation of clock skews during hierarchical static timing analysis 有权
标题翻译：在分层静态时序分析期间有效验证时钟偏差的方法和系统
公开(公告)号：US07987440B2
公开(公告)日：2011-07-26
申请号：US12351944
申请日：2009-01-12
申请人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Pooja M. Kotecha
发明人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Pooja M. Kotecha
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and a system for validating clock skews during a hierarchical static timing analysis of a chip or multi-chip package. Each pair of clock inputs of a hierarchical module bounds the allowable clock skew, creating new relative constraints on clock input arrival times propagated to those clock inputs. One embodiment is based on asserted arrival times and a maximum of computed slack values at said clock inputs, while a second embodiment is based on asserted arrival times and a minimum of downstream test slack values. The method further converts module clock assertions into a set of relative timing constraints to allow a hierarchical timing sign-off even in circumstances where absolute timing arrivals are not totally known at the time of module analysis.
摘要翻译：一种用于在芯片或多芯片封装的分层静态时序分析期间验证时钟偏移的方法和系统。分层模块的每对时钟输入限制了可允许的时钟偏移，从而在传播到这些时钟输入的时钟输入到达时间上产生新的相对约束。一个实施例基于确定的到达时间和在所述时钟输入处的计算的松弛值的最大值，而第二实施例基于确定的到达时间和最小的下游测试松弛值。该方法还将模块时钟断言转换成一组相对时序约束，以便即使在模块分析时绝对定时到达不是完全知道的情况下也允许分层定时签发。

2. 发明申请

US20100180242A1 Method and system for efficient validation of clock skews during hierarchical static timing analysis 有权
标题翻译：在分层静态时序分析期间有效验证时钟偏差的方法和系统
公开(公告)号：US20100180242A1
公开(公告)日：2010-07-15
申请号：US12351944
申请日：2009-01-12
申请人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Pooja M. Kotecha
发明人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Pooja M. Kotecha
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and a system for validating clock skews during a hierarchical static timing analysis of a chip or multi-chip package. Each pair of clock inputs of a hierarchical module bounds the allowable clock skew, creating new relative constraints on clock input arrival times propagated to those clock inputs. One embodiment is based on asserted arrival times and a maximum of computed slack values at said clock inputs, while a second embodiment is based on asserted arrival times and a minimum of downstream test slack values. The method further converts module clock assertions into a set of relative timing constraints to allow a hierarchical timing sign-off even in circumstances where absolute timing arrivals are not totally known at the time of module analysis.
摘要翻译：一种用于在芯片或多芯片封装的分层静态时序分析期间验证时钟偏移的方法和系统。分层模块的每对时钟输入限制了可允许的时钟偏移，从而在传播到这些时钟输入的时钟输入到达时间上产生新的相对约束。一个实施例基于确定的到达时间和在所述时钟输入处的计算的松弛值的最大值，而第二实施例基于确定的到达时间和最小的下游测试松弛值。该方法还将模块时钟断言转换成一组相对时序约束，以便即使在模块分析时绝对定时到达不是完全知道的情况下也允许分层定时签发。

3. 发明申请

US20120124534A1 System and Method for Performing Static Timing Analysis in the Presence of Correlations Between Asserted Arrival Times 失效
标题翻译：在断定到达时间之间相关性的情况下执行静态时序分析的系统和方法
公开(公告)号：US20120124534A1
公开(公告)日：2012-05-17
申请号：US12944059
申请日：2010-11-11
申请人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Jeffrey G. Hemmett , Peihua Qi , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Jeffrey G. Hemmett , Peihua Qi , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F2217/84
摘要： A method of applying common path credit in a static timing analysis in the presence of correlations between asserted arrival times, comprising the steps of using a computer, identifying one or more pairs of asserted arrival times for which one or more correlations exist; propagating to each of the one or more pairs of asserted arrival times a timing value dependent on the one or more correlations; and performing a subsequent common path pessimism removal analysis for at least one test during which a timing value dependent on the one or more correlations between asserted arrival times is used to compute an adjusted test slack.
摘要翻译：一种在断言到达时间之间的相关性存在的静态时序分析中应用公共路径信用的方法，包括以下步骤：使用计算机识别存在一个或多个相关性的一个或多个断言到达时间对; 将所述一个或多个断言到达时间对中的每一个传播到取决于所述一个或多个相关性的定时值; 以及对至少一个测试执行随后的公共路径悲观消除分析，在该测试期间，使用取决于所述到达时间之间的一个或多个相关性的定时值来计算经调整的测试松弛。

4. 发明授权

US08689158B2 System and method for performing static timing analysis in the presence of correlations between asserted arrival times 失效
标题翻译：在断言到达时间之间存在相关性的情况下执行静态时序分析的系统和方法
公开(公告)号：US08689158B2
公开(公告)日：2014-04-01
申请号：US12944059
申请日：2010-11-11
申请人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Jeffrey G. Hemmett , Peihua Qi , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Jeffrey G. Hemmett , Peihua Qi , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F2217/84
摘要： A method of applying common path credit in a static timing analysis in the presence of correlations between asserted arrival times, comprising the steps of using a computer, identifying one or more pairs of asserted arrival times for which one or more correlations exist; propagating to each of the one or more pairs of asserted arrival times a timing value dependent on the one or more correlations; and performing a subsequent common path pessimism removal analysis for at least one test during which a timing value dependent on the one or more correlations between asserted arrival times is used to compute an adjusted test slack.
摘要翻译：一种在断言到达时间之间的相关性存在的静态时序分析中应用公共路径信用的方法，包括以下步骤：使用计算机识别存在一个或多个相关性的一个或多个断言到达时间对; 将所述一个或多个断言到达时间对中的每一个传播到取决于所述一个或多个相关性的定时值; 以及对至少一个测试执行随后的公共路径悲观消除分析，在该测试期间，使用取决于所述到达时间之间的一个或多个相关性的定时值来计算经调整的测试松弛。

5. 发明授权

US07895556B2 Method for optimizing an unrouted design to reduce the probability of timing problems due to coupling and long wire routes 有权
标题翻译：用于优化未路由设计以减少由于耦合和长线路引起的定时问题的概率的方法
公开(公告)号：US07895556B2
公开(公告)日：2011-02-22
申请号：US11942990
申请日：2007-11-20
申请人： Pooja M. Kotecha , David J. Hathaway , Louise H. Trevillyan
发明人： Pooja M. Kotecha , David J. Hathaway , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method and a system is described to predict effects of coupling on timing by estimating the delta delay and delta slack that can occur due to coupling on any net, for optimization to minimize the sensitivity of slack to potential coupling violations. The invention protects against other unexpected increases in effective load capacitance, such as those due to unexpectedly long wire routes. It also estimates the delay impact of a single ‘fault’ or ‘event’, such as a coupling event or unexpectedly long wires routes, including the impact of slew propagation.
摘要翻译：描述了一种方法和系统，以通过估计由于任何网络上的耦合而可能发生的增量延迟和增量松弛来预测耦合对定时的影响，以便优化以使松弛对潜在耦合违规的灵敏度最小化。本发明可防止有效负载电容的其他意外增加，例如由于意外长的电线路由引起的负载电容。它还估计单个“故障”或“事件”的延迟影响，例如耦合事件或意外长电线路由，包括转换传播的影响。

6. 发明申请

US20090132982A1 METHOD FOR OPTIMIZING AN UNROUTED DESIGN TO REDUCE THE PROBABILITY OF TIMING PROBLEMS DUE TO COUPLING AND LONG WIRE ROUTES 有权
标题翻译：优化设计的方法，以减少因耦合和长途径导致的时序问题的可行性
公开(公告)号：US20090132982A1
公开(公告)日：2009-05-21
申请号：US11942990
申请日：2007-11-20
申请人： Pooja M. Kotecha , David J. Hathaway , Louise H. Trevillyan
发明人： Pooja M. Kotecha , David J. Hathaway , Louise H. Trevillyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method and a system is described to predict effects of coupling on timing by estimating the delta delay and delta slack that can occur due to coupling on any net, for optimization to minimize the sensitivity of slack to potential coupling violations. The invention protects against other unexpected increases in effective load capacitance, such as those due to unexpectedly long wire routes. It also estimates the delay impact of a single ‘fault’ or ‘event’, such as a coupling event or unexpectedly long wires routes, including the impact of slew propagation.
摘要翻译：描述了一种方法和系统，以通过估计由于任何网络上的耦合而可能发生的增量延迟和增量松弛来预测耦合对定时的影响，以便优化以使松弛对潜在耦合违规的灵敏度最小化。本发明可防止有效负载电容的其他意外增加，例如由于意外长的电线路由引起的负载电容。它还估计单个“故障”或“事件”的延迟影响，例如耦合事件或意外长电线路由，包括转换传播的影响。

7. 发明申请

US20110035714A1 SYSTEM AND METHOD FOR COMMON HISTORY PESSIMISM RELIEF DURING STATIC TIMING ANALYSIS 有权
标题翻译：系统和方法在静态时序分析期间的共同历史缓解
公开(公告)号：US20110035714A1
公开(公告)日：2011-02-10
申请号：US12538229
申请日：2009-08-10
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A system and method for adjustment of modeled timing data variation as a function of past state and/or switching history during static timing analysis. One illustrative embodiment may include inputting and asserting at least one of initial signal history bound and explicit device history bound constraints for at least one signal of a circuit design and evaluating for a segment processed during a forward propagation of block based static timing analysis whether any input signal to a current segment has a bounded history, at least one of propagated and asserted. The method may further include evaluating for the segment whether history bounds are downstream from a gating restriction, and processing a next segment until there are no further segments.
摘要翻译：一种用于在静态时序分析期间调整作为过去状态和/或切换历史的函数的建模定时数据变化的系统和方法。一个说明性实施例可以包括输入和断言用于电路设计的至少一个信号的初始信号历史约束和显式设备历史约束约束中的至少一个，并且针对在基于块的静态时序分析的正向传播期间处理的段来评估是否有任何输入对当前段的信号具有有界历史，至少一个传播和断言。该方法可以进一步包括评估该段是否历史边界是在门控限制的下游，以及处理下一个段，直到没有进一步的段。

8. 发明授权

US07669156B2 Method of identifying paths with delays dominated by a particular factor 失效
标题翻译：识别具有由特定因素主导的延迟的路径的方法
公开(公告)号：US07669156B2
公开(公告)日：2010-02-23
申请号：US12014138
申请日：2008-01-15
申请人： David J. Hathaway , Kerim Kalafala
发明人： David J. Hathaway , Kerim Kalafala
IPC分类号： G06F17/50
CPC分类号： H04L41/14 , H04L43/0852 , H04L43/16
摘要： A method of performing node-based static timing analysis on a digital network and a program storage device for implementing the method, wherein the method comprises partitioning timing delays in the digital network into portions attributable to a factor of interest and portions attributable to other factors; multiplying the timing delays by different weights based on the factor of interest to produce weighted timing delays; and using the multiplied timing delays to determine a relative impact of the factor of interest on the various paths in the digital network. The method further comprises setting arrival times of timing signals at digital network path start points to zero and identifying digital network paths whose timing delays are dominated by a particular factor of interest. The different weights comprise any of a positive weight, a negative weight, and a zero weight.
摘要翻译：一种在数字网络上执行基于节点的静态时序分析的方法和用于实现该方法的程序存储设备，其中该方法包括将数字网络中的定时延迟分成可归因于其他因素的关注因素和部分; 基于感兴趣的因素将定时延迟乘以不同的权重以产生加权定时延迟; 并且使用相乘的定时延迟来确定感兴趣因素对数字网络中各种路径的相对影响。该方法还包括将数字网络路径起点处的定时信号的到达时间设置为零，并且识别其定时延迟由特定感兴趣的因素支配的数字网络路径。不同的重量包括正重量，负重量和零重量中的任何一种。

9. 发明授权

US07117466B2 System and method for correlated process pessimism removal for static timing analysis 失效
标题翻译：静态时序分析相关过程悲观消除的系统和方法
公开(公告)号：US07117466B2
公开(公告)日：2006-10-03
申请号：US10665273
申请日：2003-09-18
申请人： Kerim Kalafala , Peihua Qi , David J. Hathaway , Alexander J. Suess , Chandramouli Visweswariah
发明人： Kerim Kalafala , Peihua Qi , David J. Hathaway , Alexander J. Suess , Chandramouli Visweswariah
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method of removing pessimism in static timing analysis is described. Delays are expressed as a function of discrete parameter settings allowing for both local and global variation to be taken in to account. Based on a specified target slack, each failing timing test is examined to determine a consistent set of parameter settings which produces the worst possible slack. The analysis is performed on a path basis. By considering only parameters which are in common to a particular data/clock path-pair, the number of process combinations that need to be explored is reduced when compared to analyzing all combinations of the global parameter settings. Further, if parameters are separable and linear, worst-case variable assignments for a particular clock/data path pair can be computed in linear time by independently assigning each parameter value. In addition, if available, the incremental delay change with respect to each physically realizable process variable may be used to project the worst-case variable assignment on a per-path basis without the need for performing explicit corner enumeration.
摘要翻译：描述了静态时序分析中消除悲观情绪的方法。延迟表示为离散参数设置的函数，允许将本地和全局变量都用于账户。根据指定的目标松弛，检查每个失败的定时测试，以确定一组一致的参数设置，从而产生最差的松弛。分析以路径为基础进行。通过仅考虑与特定数据/时钟路径对共同的参数，与分析全局参数设置的所有组合相比，需要探索的进程组合的数量减少。此外，如果参数是可分离的和线性的，则通过独立地分配每个参数值，可以在线性时间内计算特定时钟/数据路径对的最差情况变量分配。另外，如果可用，可以使用相对于每个物理上可实现的过程变量的增量延迟变化来在每个路径基础上投射最坏情况的变量赋值，而不需要执行明确的角点枚举。

10. 发明授权

US08108816B2 Device history based delay variation adjustment during static timing analysis 有权
标题翻译：静态时序分析期间基于设备历史的延迟变化调整
公开(公告)号：US08108816B2
公开(公告)日：2012-01-31
申请号：US12484293
申请日：2009-06-15
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/504 , G06F2217/84
摘要： A system and method for the adjustment of history based delay variation during static timing analysis of an integrated circuit design. The method may include obtaining information through sources of variability of history based components of delay variability, and a relationship between the sources of variability and one or more bounded device histories. Then, inputting history bounds for at least one signal of the integrated circuit design, and computing and propagating history bounds through at least one first segment of the integrated circuit design to at least one signal of the integrated circuit design. Further, the method may include evaluating from at least one of the propagated history bounds, device history bounds for at least one second segment of the integrated circuit design, and based on the evaluated device history bounds, adjusting at least one of a value of the history based delay variability and propagation of timing.
摘要翻译：一种用于在集成电路设计的静态时序分析期间调整基于历史的延迟变化的系统和方法。该方法可以包括通过延迟变异性的基于历史的组件的变异源获得信息，以及变异源与一个或多个有界设备历史之间的关系。然后，为集成电路设计的至少一个信号输入历史界限，并且通过集成电路设计的至少一个第一段将集成电路设计的至少一个信号计算和传播历史界限。此外，该方法可以包括从至少一个传播的历史界限评估集成电路设计的至少一个第二段的设备历史界限，以及基于所评估的设备历史界限，调整至少一个基于历史的延迟变异性和时间传播。

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