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1. 发明申请

US20090192776A1 CHARGE-BASED CIRCUIT ANALYSIS 有权
标题翻译：基于费率的电路分析
公开(公告)号：US20090192776A1
公开(公告)日：2009-07-30
申请号：US12163318
申请日：2008-06-27
申请人： Emrah Acar , Bhavna Agrawal , Peter Feldmann , Ying Liu , Steven G. Walker
发明人： Emrah Acar , Bhavna Agrawal , Peter Feldmann , Ying Liu , Steven G. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A solution for analyzing a circuit using initial charge information is provided. In particular, one or more nodes in a design for the circuit is initialized with an initial charge. The charge can comprise a non-equilibrium charge, thereby simulating the history effect, the impact of a charged particle, electro-static discharge (ESD), and/or the like. Operation of the circuit is then simulated over a set of input cycles based on the initial charge(s). To this extent, the non-equilibrium initial condition solution enables the state of the circuit to be controlled and solves the initial system based on these values. This capability is very useful to condition the circuit at a worst-case, best-case, and/or the like, status. Further, in one embodiment of the invention, a set of equations are provided to implement the non-equilibrium initial charge analysis, which provide a more efficient initialization of the circuit than current solutions.
摘要翻译：提供了使用初始电荷信息分析电路的解决方案。特别地，用于电路的设计中的一个或多个节点用初始电荷初始化。电荷可以包括非平衡电荷，从而模拟历史效应，带电粒子的影响，静电放电（ESD）等。然后基于初始电荷在一组输入周期上模拟电路的操作。在这种程度上，非平衡初始条件解决方案使得能够控制电路的状态并且基于这些值来解决初始系统。该功能对于在最坏情况，最佳情况和/或类似状态下调节电路非常有用。此外，在本发明的一个实施例中，提供一组方程以实现非平衡初始电荷分析，其提供电路比当前解决方案更有效的初始化。

2. 发明授权

US07519526B2 Charge-based circuit analysis 失效
标题翻译：充电电路分析
公开(公告)号：US07519526B2
公开(公告)日：2009-04-14
申请号：US11355342
申请日：2006-02-16
申请人： Emrah Acar , Bhavna Agrawal , Peter Feldmann , Ying Liu , Steven G. Walker
发明人： Emrah Acar , Bhavna Agrawal , Peter Feldmann , Ying Liu , Steven G. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A solution for analyzing a circuit using initial charge information is provided. In particular, one or more nodes in a design for the circuit is initialized with an initial charge. The charge can comprise a non-equilibrium charge, thereby simulating the history effect, the impact of a charged particle, electro-static discharge (ESD), and/or the like. Operation of the circuit is then simulated over the set of input cycles based on the initial charge(s). To this extent, the non-equilibrium initial condition solution enables the state of the circuit to be controlled and solves the initial system based on these values. This capability is very useful to condition the circuit at a worst-case, best-case, and/or the like, status. Further, in one embodiment of the invention, a set of equations are provided to implement the non-equilibrium initial charge analysis, which provide a more efficient initialization of the circuit than current solutions.
摘要翻译：提供了使用初始电荷信息分析电路的解决方案。特别地，用于电路的设计中的一个或多个节点用初始电荷初始化。电荷可以包括非平衡电荷，从而模拟历史效应，带电粒子的影响，静电放电（ESD）等。然后基于初始充电在该组输入周期上模拟电路的操作。在这种程度上，非平衡初始条件解决方案使得能够控制电路的状态并且基于这些值来解决初始系统。该功能对于在最坏情况，最佳情况和/或类似状态下调节电路非常有用。此外，在本发明的一个实施例中，提供一组方程以实现非平衡初始电荷分析，其提供电路比当前解决方案更有效的初始化。

3. 发明授权

US07487480B1 Method for estimating aggregate leakage of transistors 失效
标题翻译：估计晶体管漏电的方法
公开(公告)号：US07487480B1
公开(公告)日：2009-02-03
申请号：US12118857
申请日：2008-05-12
申请人： Bhavna Agrawal , David J. Hathaway , Peng Peng
发明人： Bhavna Agrawal , David J. Hathaway , Peng Peng
IPC分类号： G06F17/50 , G06F17/17 , G06F17/11
CPC分类号： G06F17/5036
摘要： A method of estimating a leakage for a plurality of transistors in an integrated circuit that accounts for narrow channel effects includes determining an expected total leaking transistor width for the collection; determining an expected total number of leaking transistors for the collection; determining an average width of a leaking transistor from the expected total leaking transistor width and expected total number of leaking transistors; estimating a leakage for a transistor of the average width; and determining the estimated leakage for the collection of transistors by multiplying the leakage for a transistor of the average width by the expected total number of leaking transistors for the collection.
摘要翻译：估计考虑窄通道效应的集成电路中的多个晶体管的泄漏的方法包括确定用于采集的预期的总泄漏晶体管宽度; 确定用于收集的泄漏晶体管的预期总数; 从预期的总泄漏晶体管宽度和预期的泄漏晶体管总数确定泄漏晶体管的平均宽度; 估计平均宽度的晶体管的泄漏; 并且通过将用于平均宽度的晶体管的泄漏乘以用于集合的预期泄漏晶体管总数来确定用于收集晶体管的估计泄漏。

4. 发明申请

US20070225958A1 Charge-based circuit analysis 失效
标题翻译：充电电路分析
公开(公告)号：US20070225958A1
公开(公告)日：2007-09-27
申请号：US11355342
申请日：2006-02-16
申请人： Emrah Acar , Bhavna Agrawal , Peter Feldmann , Ying Liu , Steven Walker
发明人： Emrah Acar , Bhavna Agrawal , Peter Feldmann , Ying Liu , Steven Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A solution for analyzing a circuit using initial charge information is provided. In particular, one or more nodes in a design for the circuit is initialized with an initial charge. The charge can comprise a non-equilibrium charge, thereby simulating the history effect, the impact of a charged particle, electro-static discharge (ESD), and/or the like. Operation of the circuit is then simulated over the set of input cycles based on the initial charge(s). To this extent, the non-equilibrium initial condition solution enables the state of the circuit to be controlled and solves the initial system based on these values. This capability is very useful to condition the circuit at a worst-case, best-case, and/or the like, status. Further, in one embodiment of the invention, a set of equations are provided to implement the non-equilibrium initial charge analysis, which provide a more efficient initialization of the circuit than current solutions.
摘要翻译：提供了使用初始电荷信息分析电路的解决方案。特别地，用于电路的设计中的一个或多个节点用初始电荷初始化。电荷可以包括非平衡电荷，从而模拟历史效应，带电粒子的影响，静电放电（ESD）等。然后基于初始充电在该组输入周期上模拟电路的操作。在这种程度上，非平衡初始条件解决方案使得能够控制电路的状态并且基于这些值来解决初始系统。该功能对于在最坏情况，最佳情况和/或类似状态下调节电路非常有用。此外，在本发明的一个实施例中，提供一组方程以实现非平衡初始电荷分析，其提供电路比当前解决方案更有效的初始化。

5. 发明授权

US08239794B2 System and method for estimating leakage current of an electronic circuit 有权
标题翻译：用于估计电子电路的漏电流的系统和方法
公开(公告)号：US08239794B2
公开(公告)日：2012-08-07
申请号：US12568985
申请日：2009-09-29
申请人： Bhavna Agrawal , David J. Hathaway , Pravin P. Kamdar , Karl K. Moody, III , Peng Peng , David W. Winston
发明人： Bhavna Agrawal , David J. Hathaway , Pravin P. Kamdar , Karl K. Moody, III , Peng Peng , David W. Winston
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/5022
摘要： Disclosed are embodiments of a system and of an associated method for estimating the leakage current of an electronic circuit. The embodiments analyze a layout of an electronic circuit in order to identify all driven and non-driven nets within the electronic circuit, to identify all of the driven net-bounded partitions within the electronic circuit (based on the driven and non-driven nets), and to identify, for each driven net-bounded partition, all possible states of the electronic circuit that can leak. Then, using this information, the embodiments estimate the leakage current of the electronic circuit. This is accomplished by first determining, for each state of each driven net-bounded partition, a leakage current of the driven net-bounded partition and a probability that the state will occur in the driven net-bounded partition during operation of the electronic circuit. Then, for each state of each driven net-bounded partition, the leakage current of the driven net-bounded partition and the state probability are multiplied together. The results are then aggregated.
摘要翻译：公开了用于估计电子电路的漏电流的系统和相关方法的实施例。实施例分析电子电路的布局，以便识别电子电路内的所有被驱动和非驱动的网络，以识别电子电路内的所有被驱动的网络边界的分区（基于被驱动和非驱动的网络）并且为每个被驱动的有界分区识别可能泄漏的电子电路的所有可能的状态。然后，使用该信息，实施例估计电子电路的漏电流。这是通过首先确定每个受驱动网络边界分区的每个状态的驱动网络边界分区的泄漏电流以及在电子电路运行期间该状态将在该被驱动的有界分区中发生的概率来实现的。然后，对于每个被驱动的有界分区的每个状态，驱动的有界分区的泄漏电流和状态概率相乘。然后汇总结果。

6. 发明申请

US20060277511A1 System and method for memory element characterization 有权
标题翻译：用于记忆元素表征的系统和方法
公开(公告)号：US20060277511A1
公开(公告)日：2006-12-07
申请号：US11142709
申请日：2005-06-01
申请人： Bhavna Agrawal , Peter Feldmann , Sani Nassif , Tomasz Nowicki , Grzegorz Swirszcz
发明人： Bhavna Agrawal , Peter Feldmann , Sani Nassif , Tomasz Nowicki , Grzegorz Swirszcz
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5031
摘要： A system and method for analyzing a memory element includes modeling the memory element using a simulation method and determining component response characteristics for components of the memory element. Safety regions are computed in a state space of the memory element, which indicate stable states. A transient analysis is performed to determine a path and time needed to reach one of the safety regions. Based on the path and time needed to reach one of the safety regions, a clock waveform or waveforms are determined which place a corresponding state in that safety region.
摘要翻译：用于分析存储元件的系统和方法包括使用模拟方法对存储器元件进行建模并确定存储元件的组件的组件响应特性。在存储元件的状态空间中计算安全区域，其表示稳定状态。执行瞬态分析以确定到达安全区域之一所需的路径和时间。基于到达安全区域之一所需的路径和时间，确定在该安全区域中放置相应状态的时钟波形或波形。

7. 发明申请

US20110077882A1 SYSTEM AND METHOD FOR ESTIMATING LEAKAGE CURRENT OF AN ELECTRONIC CIRCUIT 有权
标题翻译：用于估计电子电路泄漏电流的系统和方法
公开(公告)号：US20110077882A1
公开(公告)日：2011-03-31
申请号：US12568985
申请日：2009-09-29
申请人： Bhavna Agrawal , David J. Hathaway , Pravin P. Kamdar , Karl K. Moody, III , Peng Peng , David W. Winston
发明人： Bhavna Agrawal , David J. Hathaway , Pravin P. Kamdar , Karl K. Moody, III , Peng Peng , David W. Winston
IPC分类号： G06F19/00 , G01R27/00
CPC分类号： G06F17/5022
摘要： Disclosed are embodiments of a system and of an associated method for estimating the leakage current of an electronic circuit. The embodiments analyze a layout of an electronic circuit in order to identify all driven and non-driven nets within the electronic circuit, to identify all of the driven net-bounded partitions within the electronic circuit (based on the driven and non-driven nets), and to identify, for each driven net-bounded partition, all possible states of the electronic circuit that can leak. Then, using this information, the embodiments estimate the leakage current of the electronic circuit. This is accomplished by first determining, for each state of each driven net-bounded partition, a leakage current of the driven net-bounded partition and a probability that the state will occur in the driven net-bounded partition during operation of the electronic circuit. Then, for each state of each driven net-bounded partition, the leakage current of the driven net-bounded partition and the state probability are multiplied together. The results are then aggregated.
摘要翻译：公开了用于估计电子电路的漏电流的系统和相关方法的实施例。实施例分析电子电路的布局，以便识别电子电路内的所有被驱动和非驱动的网络，以识别电子电路内的所有被驱动的网络边界的分区（基于被驱动和非驱动的网络）并且为每个被驱动的有界分区识别可能泄漏的电子电路的所有可能的状态。然后，使用该信息，实施例估计电子电路的漏电流。这是通过首先确定每个受驱动网络边界分区的每个状态，驱动网络边界分区的泄漏电流以及在电子电路运行期间状态将在驱动网络划分区域内发生的概率来实现的。然后，对于每个被驱动的有界分区的每个状态，驱动的有界分区的泄漏电流和状态概率相乘。然后汇总结果。

8. 发明授权

US08560994B1 Enabling statistical testing using deterministic multi-corner timing analysis 失效
标题翻译：使用确定性多角时序分析实现统计测试
公开(公告)号：US08560994B1
公开(公告)日：2013-10-15
申请号：US13454795
申请日：2012-04-24
申请人： Bhavna Agrawal , David S. Kung , Jinjun Xiong , Vladimir Zolotov
发明人： Bhavna Agrawal , David S. Kung , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G01R31/31725 , G06F2217/10 , G06F2217/84
摘要： In one embodiment, the invention is a method and apparatus for variation enabling statistical testing using deterministic multi-corner timing analysis. One embodiment of a method for obtaining statistical timing data for an integrated circuit chip includes obtaining deterministic multi-corner timing data for the integrated circuit chip and constructing the statistical timing data from the deterministic multi-corner timing data.
摘要翻译：在一个实施例中，本发明是用于使用确定性多角时间分析进行统计测试的变化的方法和装置。用于获得用于集成电路芯片的统计定时数据的方法的一个实施例包括获得用于集成电路芯片的确定性多角定时数据并从确定性多角定时数据构建统计定时数据。

9. 发明申请

US20120266119A1 Delay Model Construction In The Presence Of Multiple Input Switching Events 失效
标题翻译：多输入切换事件存在的延迟模型构建
公开(公告)号：US20120266119A1
公开(公告)日：2012-10-18
申请号：US13088688
申请日：2011-04-18
申请人： Jeffrey P. Soreff , Bhavna Agrawal , David J. Hathaway
发明人： Jeffrey P. Soreff , Bhavna Agrawal , David J. Hathaway
IPC分类号： G06F9/455
CPC分类号： G06F17/5031
摘要： A method for constructing delay rules which include the effects of MIS simulations for static timing analysis with reduced cost. The present method includes constructing skew windows for applying MIS penalties purely from SIS data, and scales the MIS penalties during rule use based upon how closely the skews in the use case approach the edge of the skew window. The method applies both to timing rule construction for a library of circuits and to timing rule construction for macros where only part of the circuits in the macro may be sensitive to skew between macro inputs.
摘要翻译：一种用于构建延迟规则的方法，其中包括MIS模拟对静态时序分析的影响，降低成本。本方法包括构建歪斜窗口，用于纯粹来自SIS数据的MIS惩罚，并根据使用案例中的倾斜度接近偏斜窗口的边缘来缩小规则使用期间的MIS惩罚。该方法既适用于电路库的定时规则构造，也适用于宏的定时规则构造，其中宏中仅部分电路可能对宏输入之间的偏移敏感。

10. 发明申请

US20130283223A1 ENABLING STATISTICAL TESTING USING DETERMINISTIC MULTI-CORNER TIMING ANALYSIS 失效
标题翻译：使用决定性多角度时序分析实现统计测试
公开(公告)号：US20130283223A1
公开(公告)日：2013-10-24
申请号：US13454795
申请日：2012-04-24
申请人： Bhavna Agrawal , David S. Kung , Jinjun Xiong , Vladimir Zolotov
发明人： Bhavna Agrawal , David S. Kung , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G01R31/31725 , G06F2217/10 , G06F2217/84
摘要： In one embodiment, the invention is a method and apparatus for variation enabling statistical testing using deterministic multi-corner timing analysis. One embodiment of a method for obtaining statistical timing data for an integrated circuit chip includes obtaining deterministic multi-corner timing data for the integrated circuit chip and constructing the statistical timing data from the deterministic multi-corner timing data.
摘要翻译：在一个实施例中，本发明是用于使用确定性多角时间分析进行统计测试的变化的方法和装置。用于获得用于集成电路芯片的统计定时数据的方法的一个实施例包括获得用于集成电路芯片的确定性多角定时数据并从确定性多角定时数据构建统计定时数据。

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