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1. 发明授权

US6166943A Method of forming a binary code of a ROM 有权
标题翻译：形成ROM的二进制码的方法
公开(公告)号：US6166943A
公开(公告)日：2000-12-26
申请号：US421260
申请日：1999-10-20
申请人： Ping-Ying Wang , Chun-Yi Yang , Chun-Jung Lin , Jui-Chin Chang , Mam-Tsung Wang
发明人： Ping-Ying Wang , Chun-Yi Yang , Chun-Jung Lin , Jui-Chin Chang , Mam-Tsung Wang
IPC分类号： G11C17/10 , G11C17/00
CPC分类号： G11C17/10
摘要： The present invention provides a method of writing a set of binary codes into a ROM. The method is performed by forming a first photo mask and a second photo mask according to an original first code pattern, an original second code pattern, and a set of binary codes to be written into the ROM. Final first and second code patterns are formed by coupling the binary codes to be written with the original first and second code patterns by using a Boolean logical OR operation. The first and second photo masks are formed according to the final first and second code patterns. The first photolithographic process is performed using the first photo mask, and the first ion implantation process is performed; the second photolithographic process is performed using the second photo mask, and the second ion implantation process is performed. Thus the set of binary codes is written into the ROM completely and correctly.
摘要翻译：本发明提供了将一组二进制码写入到ROM中的方法。该方法通过根据原始第一代码图案，原始第二代码图案和要写入ROM的一组二进制代码形成第一光掩模和第二光掩模来执行。最终的第一和第二代码模式通过使用布尔逻辑“或”运算来耦合待写入的二进制代码与原始的第一和第二代码模式而形成。根据最终的第一和第二编码模式形成第一和第二光掩膜。使用第一光掩模执行第一光刻工艺，并且执行第一离子注入工艺; 使用第二光掩模进行第二光刻工序，进行第二离子注入工序。因此，二进制代码集完全正确地写入ROM中。

2. 发明授权

US06397377B1 Method of performing optical proximity corrections of a photo mask pattern by using a computer 有权
标题翻译：通过使用计算机执行光掩模图案的光学邻近校正的方法
公开(公告)号：US06397377B1
公开(公告)日：2002-05-28
申请号：US09414899
申请日：1999-10-08
申请人： Bing-Ying Wang , Chun-Yi Yang , Chun-Jung Lin , Jui-Chin Chang , Mam-Tsung Wang
发明人： Bing-Ying Wang , Chun-Yi Yang , Chun-Jung Lin , Jui-Chin Chang , Mam-Tsung Wang
IPC分类号： G06F1750
CPC分类号： G03F1/36
摘要： The present invention provides a method of performing optical proximity corrections of a photo mask pattern by using a computer. The photo mask pattern is formed on a photo mask which is used when performing photolithography for forming a predetermined original pattern by exposing a photo-resist layer in a predetermined area of a semiconductor wafer. The photo mask pattern is divided into a plurality of rectangular blocks. Each block can be bright or dark, and a least one side and two corners of the block are shared with another block. Each of shared corners is checked to find corners which may be affected by an optic proximity effect, and those corners are modified so as to prevent them from being affected by the optic proximity effect.
摘要翻译：本发明提供一种通过使用计算机执行光掩模图案的光学邻近校正的方法。光掩模图案形成在通过在半导体晶片的预定区域中曝光光刻胶层进行光刻以形成预定原始图案时使用的光掩模上。光掩模图案被分成多个矩形块。每个块可以是明亮的或暗的，并且该块的至少一个侧面和两个角与另一个块共享。检查每个共享拐角以找到可能受光学邻近效应影响的角部，并且修改这些拐角以防止它们受到光学邻近效应的影响。

3. 发明授权

US06468869B1 Method of fabricating mask read only memory 有权
标题翻译：制造掩模只读存储器的方法
公开(公告)号：US06468869B1
公开(公告)日：2002-10-22
申请号：US09930843
申请日：2001-08-14
申请人： Chun-Yi Yang , Chun-Jung Lin , Ful-Long Ni
发明人： Chun-Yi Yang , Chun-Jung Lin , Ful-Long Ni
IPC分类号： H01L218236
CPC分类号： H01L27/11266 , H01L27/112
摘要： A method of fabricating a mask read only memory. Gate stacked structures, each of which made up of a gate dielectric layer, a gate conductive layer and a gate cap layer, are formed on a substrate. Source/drain regions are between, but not adjacent to the gate stacked structures. Regions between the source/drain regions and the gate stacked structures are coding areas. A dielectric layer is formed to fill spaces between the gate stacked structures. A photoresist layer with openings exposing the first dielectric layer on the coding areas is formed. The exposed first dielectric layer is removed to form implantation openings of the coding areas. Ion implantation is performed on the exposed coding areas. The photoresist layer is removed, and another dielectric layer is formed to fill the implantation openings. An etching back process is performed to expose the gate conductive layer. A word line is formed on the gate conductive layer.
摘要翻译：一种制造掩模只读存储器的方法。在基板上形成由栅极介电层，栅极导电层和栅极盖层构成的栅极堆叠结构。源极/漏极区域在栅极堆叠结构之间但不邻近栅极堆叠结构。源极/漏极区域和栅极堆叠结构之间的区域是编码区域。形成电介质层以填充栅层叠结构之间的空间。形成具有使编码区域上的第一介电层露出的开口的光致抗蚀剂层。去除暴露的第一介电层以形成编码区域的注入开口。在暴露的编码区域进行离子注入。去除光致抗蚀剂层，形成另一介质层以填充注入开口。进行蚀刻反应处理以暴露栅极导电层。在栅极导电层上形成字线。

4. 发明授权

US06440803B1 Method of fabricating a mask ROM with raised bit-line on each buried bit-line 有权
标题翻译：在每个掩埋位线上制造具有凸起位线的掩模ROM的方法
公开(公告)号：US06440803B1
公开(公告)日：2002-08-27
申请号：US10047685
申请日：2002-01-14
申请人： Shui-Chin Huang , Yen-hung Yeh , Tso-Hung Fan , Chun-Yi Yang , Chun-Jung Lin
发明人： Shui-Chin Huang , Yen-hung Yeh , Tso-Hung Fan , Chun-Yi Yang , Chun-Jung Lin
IPC分类号： H01L218238
CPC分类号： H01L27/11266 , H01L27/112
摘要： A method of fabricating a mask ROM, in which conductive strips are formed with a cap layer on each of them, then a plurality of spacers are formed on the side-walls of the conductive strips, while the substrate under the spacers are used as the coding regions. The buried bit-lines are formed in the substrate between the spacers, then a two-step coding process is performed, wherein the coding regions at the first and the second side of the conductive strips are selectively doped by a first and a second tilt coding implantation with a first and a second coding mask. After the second mask layer and the cap layer are removed, a conductive layer is formed over the substrate, then the conductive layer and the conductive strips are patterned successively to form a plurality of word-lines and plural gates, respectively.
摘要翻译：一种制造掩模ROM的方法，其中在每个掩模ROM上形成具有覆盖层的导电条，然后在导电条的侧壁上形成多个间隔物，同时使用间隔物下的基板作为编码区域。掩埋位线形成在间隔物之间的衬底中，然后进行两步编码处理，其中导电条的第一和第二侧的编码区被第一和第二倾斜编码用第一和第二编码掩模进行植入。在除去第二掩模层和盖层之后，在衬底上形成导电层，然后分别对导电层和导电条进行图案化以形成多个字线和多个栅极。

5. 发明授权

US08648401B2 Domain wall assisted spin torque transfer magnetresistive random access memory structure 有权
标题翻译：域壁辅助自旋转矩传递磁阻随机存取存储器结构
公开(公告)号：US08648401B2
公开(公告)日：2014-02-11
申请号：US12884351
申请日：2010-09-17
申请人： Chih-Huang Lai , Sheng-Huang Huang , Kuo-Feng Huang , Ming-Te Liu , Chun-Jung Lin , Ya-Chen Kao , Wen-Cheng Chen
发明人： Chih-Huang Lai , Sheng-Huang Huang , Kuo-Feng Huang , Ming-Te Liu , Chun-Jung Lin , Ya-Chen Kao , Wen-Cheng Chen
IPC分类号： H01L21/02
CPC分类号： H01L43/12 , G11C11/161 , G11C11/1657 , G11C11/1675 , G11C19/0808 , H01L27/228 , H01L43/08
摘要： A semiconductor memory device includes a first ferromagnetic layer magnetically pinned and positioned within a first region of a substrate; a second ferromagnetic layer approximate the first ferromagnetic layer; and a barrier layer interposed between the first ferromagnetic layer and the first portion of the second ferromagnetic layer. The second ferromagnetic layer includes a first portion being magnetically free and positioned within the first region; a second portion magnetically pinned to a first direction and positioned within a second region of the substrate, the second region contacting the first region from a first side; and a third portion magnetically pinned to a second direction and positioned within a third region of the substrate, the third region contacting the first region from a second side.
摘要翻译：半导体存储器件包括磁性固定并位于衬底的第一区域内的第一铁磁层; 第二铁磁层近似第一铁磁层; 以及介于所述第一铁磁层与所述第二铁磁层的所述第一部分之间的阻挡层。第二铁磁层包括无磁性的第一部分，并且位于第一区域内; 第二部分，磁性地固定在第一方向上并且位于所述基板的第二区域内，所述第二区域从第一侧接触所述第一区域; 以及第三部分，其磁性地固定到第二方向并且位于所述基板的第三区域内，所述第三区域从所述第二侧面接触所述第一区域。

6. 发明授权

US08629518B2 Sacrifice layer structure and method for magnetic tunnel junction (MTJ) etching process 有权
标题翻译：牺牲层结构和磁隧道结（MTJ）蚀刻工艺
公开(公告)号：US08629518B2
公开(公告)日：2014-01-14
申请号：US12828593
申请日：2010-07-01
申请人： Yu-Jen Wang , Ya-Chen Kao , Chun-Jung Lin
发明人： Yu-Jen Wang , Ya-Chen Kao , Chun-Jung Lin
IPC分类号： H01L29/82
CPC分类号： H01L43/12 , H01L43/08
摘要： A magnetic tunnel junction (MTJ) etching process uses a sacrifice layer. An MTJ cell structure includes an MTJ stack with a first magnetic layer, a second magnetic layer, and a tunnel barrier layer in between the first magnetic layer and the second magnetic layer, and a sacrifice layer adjacent to the second magnetic layer, where the sacrifice layer protects the second magnetic layer in the MTJ stack from oxidation during an ashing process. The sacrifice layer does not increase a resistance of the MTJ stack. The sacrifice layer can be made of Mg, Cr, V, Mn, Ti, Zr, Zn, or any alloy combination thereof, or any other suitable material. The sacrifice layer can be multi-layered and/or have a thickness ranging from 5 Å to 400 Å. The MTJ cell structure can have a top conducting layer over the sacrifice layer.
摘要翻译：磁隧道结（MTJ）蚀刻工艺使用牺牲层。 MTJ单元结构包括在第一磁性层和第二磁性层之间的具有第一磁性层，第二磁性层和隧道势垒层的MTJ堆叠以及与第二磁性层相邻的牺牲层，其中牺牲层在灰化过程中保护MTJ堆叠中的第二磁性层免受氧化。牺牲层不会增加MTJ堆叠的电阻。牺牲层可以由Mg，Cr，V，Mn，Ti，Zr，Zn或其任何合金组合或任何其它合适的材料制成。牺牲层可以是多层的和/或具有从5到400的厚度。 MTJ单元结构可以在牺牲层上方具有顶部导电层。

7. 发明授权

US08493776B1 MRAM with current-based self-referenced read operations 有权
标题翻译： MRAM具有基于当前的自引用读操作
公开(公告)号：US08493776B1
公开(公告)日：2013-07-23
申请号：US13364756
申请日：2012-02-02
申请人： Hung-Chang Yu , Kai-Chun Lin , Yu-Der Chih , Chun-Jung Lin
发明人： Hung-Chang Yu , Kai-Chun Lin , Yu-Der Chih , Chun-Jung Lin
IPC分类号： G11C11/00
CPC分类号： G11C11/1673 , G11C13/004 , G11C29/74
摘要： A magnetoresistive memory stores logic values in high and low resistance states of magnetic tunnel junction elements. Instead of comparing the resistance of elements to a fixed threshold to discern a logic state, the resistances of elements are self-compared before and after imposing a low resistance state. A measure of the resistance of an element in its unknown resistance state is stored, for example by charging a capacitor to a voltage produced when read current bias is applied. Then the element is written into its low resistance state and read current bias is applied again to develop another voltage, representing the low resistance state. A comparison circuit using current summing and an offset providing a minimum difference tolerance determines whether the resistance of the element was changed or remained the same. This determines the logic state of the element.
摘要翻译：磁阻存储器将逻辑值存储在磁性隧道结元件的高电阻和低电阻状态中。代替将元件的电阻与固定阈值进行比较以辨别逻辑状态，元件的电阻在施加低电阻状态之前和之后自我比较。例如，通过将电容器充电到施加读取电流偏压时产生的电压来存储元件在其未知电阻状态下的电阻的量度。然后将元件写入其低电阻状态，并再次施加读取电流偏压以产生表示低电阻状态的另一电压。使用电流求和和提供最小差容差的偏移的比较电路确定元件的电阻是改变还是保持相同。这决定了元素的逻辑状态。

8. 发明申请

US20130038418A1 CONTACTLESS COMMUNICATIONS USING FERROMAGNETIC MATERIAL 有权
标题翻译：使用纤维材料的无缝通信
公开(公告)号：US20130038418A1
公开(公告)日：2013-02-14
申请号：US13206584
申请日：2011-08-10
申请人： Ping-Lin Yang , Jun-De Jin , Fu-Lung Hsueh , Sa-Lly Liu , Tong-Chern Ong , Chun-Jung Lin , Ya-Chen Kao
发明人： Ping-Lin Yang , Jun-De Jin , Fu-Lung Hsueh , Sa-Lly Liu , Tong-Chern Ong , Chun-Jung Lin , Ya-Chen Kao
IPC分类号： H01F38/14 , H01F41/00
CPC分类号： H01L25/0657 , H01F5/00 , H01F27/2804 , H01F41/046 , H01F2027/2809 , H01L23/48 , H01L23/5227 , H01L2225/06531 , H01L2924/0002 , Y10T29/4902 , H01L2924/00
摘要： A communications structure comprises a first semiconductor substrate having a first coil, and a second semiconductor substrate having a second coil above the first semiconductor substrate. Inner edges of the first and second coils define a boundary of a volume that extends below the first coil and above the second coil. A ferromagnetic core is positioned at least partially within the boundary, such that a mutual inductance is provided between the first and second coils for wireless transmission of signals or power between the first and second coils.
摘要翻译：通信结构包括具有第一线圈的第一半导体衬底和在第一半导体衬底上方具有第二线圈的第二半导体衬底。第一和第二线圈的内边缘限定在第一线圈下方延伸并在第二线圈之上的体积的边界。铁磁芯至少部分地位于边界内，使得在第一和第二线圈之间提供互感以在第一和第二线圈之间无线地传输信号或电力。

9. 发明申请

US20120281464A1 Raising Programming Currents of Magnetic Tunnel Junctions Using Word Line Overdrive and High-k Metal Gate 有权
标题翻译：使用字线过驱动和高k金属栅极提高磁隧道接头的编程电流
公开(公告)号：US20120281464A1
公开(公告)日：2012-11-08
申请号：US13550262
申请日：2012-07-16
申请人： Shine Chung , Tao-Wen Chung , Chun-Jung Lin , Yu-Jen Wang , Hung-Sen Wang
发明人： Shine Chung , Tao-Wen Chung , Chun-Jung Lin , Yu-Jen Wang , Hung-Sen Wang
IPC分类号： G11C11/16
CPC分类号： G11C11/16 , G11C8/08 , G11C11/1657 , G11C11/1659
摘要： A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device; and a selector comprising a source-drain path serially coupled to the MTJ device. The method further includes applying an overdrive voltage to a gate of the selector to turn on the selector.
摘要翻译：操作磁阻随机存取存储器（MRAM）单元的方法包括提供包括磁隧道结（MTJ）装置的MRAM单元; 以及选择器，包括串联耦合到MTJ器件的源极 - 漏极路径。该方法还包括将过驱动电压施加到选择器的门以接通选择器。

10. 发明申请

US20120127788A1 MRAM Cells and Circuit for Programming the Same 有权
标题翻译： MRAM单元及其编程电路
公开(公告)号：US20120127788A1
公开(公告)日：2012-05-24
申请号：US13364955
申请日：2012-02-02
申请人： Shine Chung , Hung-Sen Wang , Tao-Wen Chung , Chun-Jung Lin , Yu-Jen Wang
发明人： Shine Chung , Hung-Sen Wang , Tao-Wen Chung , Chun-Jung Lin , Yu-Jen Wang
IPC分类号： G11C11/16
CPC分类号： G11C11/1677 , G11C11/1675
摘要： A circuit includes magneto-resistive random access memory (MRAM) cell and a control circuit. The control circuit is electrically coupled to the MRAM cell, and includes a current source configured to provide a first writing pulse to write a value into the MRAM cell, and a read circuit configured to measure a status of the MRAM cell. The control circuit is further configured to verify whether a successful writing is achieved through the first writing pulse.
摘要翻译：电路包括磁阻随机存取存储器（MRAM）单元和控制电路。控制电路电耦合到MRAM单元，并且包括被配置为提供第一写入脉冲以将值写入MRAM单元的电流源和被配置为测量MRAM单元的状态的读取电路。控制电路还被配置为验证通过第一写入脉冲是否实现了成功写入。

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