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1. 发明申请

US20050024799A1 Electronic component protected against elelctrostatic discharges 有权
标题翻译：保护电子元件免受静电放电
公开(公告)号：US20050024799A1
公开(公告)日：2005-02-03
申请号：US10867285
申请日：2004-06-14
申请人： Pierre Busson , Pierre-Olivier Jouffre , Bernard Louis-Gavet
发明人： Pierre Busson , Pierre-Olivier Jouffre , Bernard Louis-Gavet
IPC分类号： H01L23/36 , H01L23/60 , H01L23/62 , H02H9/00
CPC分类号： H01L23/60 , H01L24/48 , H01L2224/05553 , H01L2224/05599 , H01L2224/45099 , H01L2224/48237 , H01L2224/85399 , H01L2924/00014 , H01L2924/01057 , H01L2924/01079 , H01L2924/10161 , H01L2924/10253 , H01L2924/1305 , H01L2924/14 , H01L2924/181 , H01L2924/3011 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： The electronic component, comprises an integrated circuit incorporating several separate functional blocks within a semiconductor substrate, and electrostatic discharge protection means. These electrostatic discharge protection means comprise several separate metal discharge rails (GNDi) placed above the substrate (SB) and respectively associated with the plurality of functional blocks (CRi), all these metal discharge rails being mutually unconnected electrically within the integrated circuit (CI) but connected electrically via an electrical connection (FLi) external to the integrated circuit to one and the same ground plane (SLG) forming a ground reference for the electrostatic discharges, this ground plane (SLG) being located outside the integrated circuit (CI), and possibly being a heat slug.
摘要翻译：该电子部件包括在半导体衬底内并入几个单独功能块的集成电路和静电放电保护装置。这些静电放电保护装置包括放置在衬底（SB）上方并分别与多个功能块（CRi）分别相关联的多个单独的金属放电导轨（GNDi），所有这些金属放电导轨在集成电路（CI）内都是电连接的，但是通过集成电路外部的电连接（FLi）电连接到形成用于静电放电的接地基准的同一接地平面（SLG），该接地平面（SLG）位于集成电路（CI）外部，并可能是一个热塞。

2. 发明授权

US06914304B2 Electronic component protected against electrostatic discharges 有权
标题翻译：电子元件防止静电放电
公开(公告)号：US06914304B2
公开(公告)日：2005-07-05
申请号：US10867285
申请日：2004-06-14
申请人： Pierre Busson , Pierre-Olivier Jouffre , Bernard Louis-Gavet
发明人： Pierre Busson , Pierre-Olivier Jouffre , Bernard Louis-Gavet
IPC分类号： H01L23/36 , H01L23/60 , H01L23/62 , H02H9/00
CPC分类号： H01L23/60 , H01L24/48 , H01L2224/05553 , H01L2224/05599 , H01L2224/45099 , H01L2224/48237 , H01L2224/85399 , H01L2924/00014 , H01L2924/01057 , H01L2924/01079 , H01L2924/10161 , H01L2924/10253 , H01L2924/1305 , H01L2924/14 , H01L2924/181 , H01L2924/3011 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： The electronic component, comprises an integrated circuit incorporating several separate functional blocks within a semiconductor substrate, and electrostatic discharge protection means. These electrostatic discharge protection means comprise several separate metal discharge rails (GNDi) placed above the substrate (SB) and respectively associated with the plurality of functional blocks (CRi), all these metal discharge rails being mutually unconnected electrically within the integrated circuit (CI) but connected electrically via an electrical connection (FLi) external to the integrated circuit to one and the same ground plane (SLG) forming a ground reference for the electrostatic discharges, this ground plane (SLG) being located outside the integrated circuit (CI), and possibly being a heat slug.
摘要翻译：该电子部件包括在半导体衬底内并入几个单独功能块的集成电路和静电放电保护装置。这些静电放电保护装置包括放置在衬底（SB）上方并分别与多个功能块（CRi）分别相关联的多个单独的金属放电导轨（GNDi），所有这些金属放电导轨在集成电路（CI）内都是电连接的，但是通过集成电路外部的电连接（FLi）电连接到形成用于静电放电的接地基准的同一接地平面（SLG），该接地平面（SLG）位于集成电路（CI）外部，并可能是一个热塞。

3. 发明授权

US08483644B2 Electronic component allowing the decoding of a radiofrequency transmission channel conveying coded digital information, in particular for satellite digital telebroadcasting 有权
公开(公告)号：US08483644B2
公开(公告)日：2013-07-09
申请号：US10150524
申请日：2002-05-17
申请人： Pierre Busson , Bernard Louis-Gavet , Pierre-Olivier Jouffre
发明人： Pierre Busson , Bernard Louis-Gavet , Pierre-Olivier Jouffre
IPC分类号： H04B1/10
CPC分类号： H04N21/6143 , H04L27/06 , H04N7/20
摘要： The component, fully integrated onto a monolithic substrate, includes a tuner, a demodulator, and a channel decoder. The overall filtering is carried out in two parts, a baseband analog filtering and a digital Nyquist filtering removing the information of adjacent channels. It outputs a stream of MPEG data.

4. 发明授权

US07106808B2 Tuner of the type having zero intermediate frequency and corresponding control process 有权
标题翻译：调谐器具有零中频和相应的控制过程
公开(公告)号：US07106808B2
公开(公告)日：2006-09-12
申请号：US09827306
申请日：2001-04-05
申请人： Pierre Busson , Pierre-Olivier Jouffre , Frédéric Paillardet
发明人： Pierre Busson , Pierre-Olivier Jouffre , Frédéric Paillardet
IPC分类号： H03K9/00
CPC分类号： H03G3/3068 , H03G3/3089
摘要： A tuner includes an analog block, a digital block, and an analog/digital conversion stage connected therebetween. The analog block includes a first attenuator/controlled-gain amplifier stage connected upstream to a frequency transposition stage. The overall mean power of the entire signal received by the tuner is calculated during a phase of initialization. This overall calculated power is compared in the digital block with a first predetermined reference value corresponding to a maximum power desired at a predetermined location of the analog block. The gain of the first attenuator/amplifier stage is adjusted to minimize the deviation between the overall calculated power and the reference value. In a phase of normal operation, one of the channels of the signal received is selected, with the gain of the first attenuator/amplifier stage being fixed.
摘要翻译：调谐器包括模拟块，数字块和连接在它们之间的模拟/数字转换级。模拟模块包括连接到频率转置级上游的第一衰减器/受控增益放大器级。在初始化阶段计算由调谐器接收的整个信号的总平均功率。该总计算功率在数字模块中与对应于模拟模块的预定位置所需的最大功率的第一预定参考值进行比较。调整第一衰减器/放大器级的增益以最小化总计算功率与参考值之间的偏差。在正常操作的相位中，选择所接收的信号中的一个通道，其中第一衰减器/放大器级的增益是固定的。

5. 发明授权

US06249154B1 Process of controlling a switch of a switched-capacitance device, and corresponding switched-capacitance device 有权
标题翻译：控制开关电容器件的开关和相应的开关电容器件的过程
公开(公告)号：US06249154B1
公开(公告)日：2001-06-19
申请号：US09571392
申请日：2000-05-15
申请人： Pierre-Olivier Jouffre , Isabelle Telliez , Frédéric Paillardet
发明人： Pierre-Olivier Jouffre , Isabelle Telliez , Frédéric Paillardet
IPC分类号： G11C2702
CPC分类号： H03K17/063 , H03K17/165
摘要： With a switch including at least one insulated-gate field-effect transistor, an analog input signal is delivered on the source of the transistor and the transistor is controlled on its gate synchronized with a clock signal to successively turn it on and off. On the conclusion of each half-period of the clock signal during which the transistor is off, a precharging capacitor is precharged at the start of the next half-period and for a predetermined precharge duration, with a predetermined precharge voltage. Then, for the remaining duration of the half-period, the precharged capacitor is connected between the source and the gate of the transistor to turn it on under the action of a gate-source voltage which is almost independent of the level of the input signal. At the end of the half-period, the gate of the transistor and the precharging capacitor are grounded.
摘要翻译：使用包括至少一个绝缘栅场效应晶体管的开关，在晶体管的源极上传送模拟输入信号，并且在其栅极上控制晶体管与时钟信号同步以连续地打开和关闭。在晶体管截止的时钟信号的每个半周期的结论处，预充电电容器在下一个半周期的开始和预定的预充电持续时间内以预定的预充电电压进行预充电。然后，对于半周期的剩余时间，预充电电容器连接在晶体管的源极和栅极之间，以在几乎不依赖于输入信号电平的栅极 - 源极电压的作用下导通。在半周期结束时，晶体管的栅极和预充电电容器接地。

6. 发明授权

US06943598B2 Reduced-size integrated phase-locked loop 有权
标题翻译：减小尺寸的集成锁相环
公开(公告)号：US06943598B2
公开(公告)日：2005-09-13
申请号：US10776931
申请日：2004-02-11
申请人： Mostafa Ghazali , Pierre-Olivier Jouffre
发明人： Mostafa Ghazali , Pierre-Olivier Jouffre
IPC分类号： H03L7/089 , H03L7/099 , H03L7/18 , H03L7/06
CPC分类号： H03L7/18 , H03L7/0891 , H03L7/0996
摘要： A phase-locked loop comprising a comparator generating a control voltage depending on the phase-shift between a reference signal and a feedback signal, an oscillator controlled by the control voltage, generating several phase-shifted signals of same period, one of which forms the output signal of the phase-locked loop, a multiplexer capable of providing any of the phase-shifted signals to the input of a divider, the output of which forms the feedback signal, and a means controlling the multiplexer to successively provide fractions of the phase-shifted signals, so that the divider receives a signal having an average period equal to a real fraction of the period of the phase-shifted signals.
摘要翻译：一种锁相环，包括比较器，其产生取决于参考信号和反馈信号之间的相移的控制电压，由控制电压控制的振荡器，产生相同周期的多个相移信号，其中之一形成输出信号的多路复用器，能够将任何相移信号提供给分频器的输入，分频器的输出形成反馈信号，以及控制多路复用器的装置，以连续地提供相位的分数转换信号，使得分频器接收具有等于相移信号的周期的实际分数的平均周期的信号。

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