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1. 发明授权

US06914304B2 Electronic component protected against electrostatic discharges 有权
标题翻译：电子元件防止静电放电
公开(公告)号：US06914304B2
公开(公告)日：2005-07-05
申请号：US10867285
申请日：2004-06-14
申请人： Pierre Busson , Pierre-Olivier Jouffre , Bernard Louis-Gavet
发明人： Pierre Busson , Pierre-Olivier Jouffre , Bernard Louis-Gavet
IPC分类号： H01L23/36 , H01L23/60 , H01L23/62 , H02H9/00
CPC分类号： H01L23/60 , H01L24/48 , H01L2224/05553 , H01L2224/05599 , H01L2224/45099 , H01L2224/48237 , H01L2224/85399 , H01L2924/00014 , H01L2924/01057 , H01L2924/01079 , H01L2924/10161 , H01L2924/10253 , H01L2924/1305 , H01L2924/14 , H01L2924/181 , H01L2924/3011 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： The electronic component, comprises an integrated circuit incorporating several separate functional blocks within a semiconductor substrate, and electrostatic discharge protection means. These electrostatic discharge protection means comprise several separate metal discharge rails (GNDi) placed above the substrate (SB) and respectively associated with the plurality of functional blocks (CRi), all these metal discharge rails being mutually unconnected electrically within the integrated circuit (CI) but connected electrically via an electrical connection (FLi) external to the integrated circuit to one and the same ground plane (SLG) forming a ground reference for the electrostatic discharges, this ground plane (SLG) being located outside the integrated circuit (CI), and possibly being a heat slug.
摘要翻译：该电子部件包括在半导体衬底内并入几个单独功能块的集成电路和静电放电保护装置。这些静电放电保护装置包括放置在衬底（SB）上方并分别与多个功能块（CRi）分别相关联的多个单独的金属放电导轨（GNDi），所有这些金属放电导轨在集成电路（CI）内都是电连接的，但是通过集成电路外部的电连接（FLi）电连接到形成用于静电放电的接地基准的同一接地平面（SLG），该接地平面（SLG）位于集成电路（CI）外部，并可能是一个热塞。

2. 发明申请

US20050024799A1 Electronic component protected against elelctrostatic discharges 有权
标题翻译：保护电子元件免受静电放电
公开(公告)号：US20050024799A1
公开(公告)日：2005-02-03
申请号：US10867285
申请日：2004-06-14
申请人： Pierre Busson , Pierre-Olivier Jouffre , Bernard Louis-Gavet
发明人： Pierre Busson , Pierre-Olivier Jouffre , Bernard Louis-Gavet
IPC分类号： H01L23/36 , H01L23/60 , H01L23/62 , H02H9/00
CPC分类号： H01L23/60 , H01L24/48 , H01L2224/05553 , H01L2224/05599 , H01L2224/45099 , H01L2224/48237 , H01L2224/85399 , H01L2924/00014 , H01L2924/01057 , H01L2924/01079 , H01L2924/10161 , H01L2924/10253 , H01L2924/1305 , H01L2924/14 , H01L2924/181 , H01L2924/3011 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： The electronic component, comprises an integrated circuit incorporating several separate functional blocks within a semiconductor substrate, and electrostatic discharge protection means. These electrostatic discharge protection means comprise several separate metal discharge rails (GNDi) placed above the substrate (SB) and respectively associated with the plurality of functional blocks (CRi), all these metal discharge rails being mutually unconnected electrically within the integrated circuit (CI) but connected electrically via an electrical connection (FLi) external to the integrated circuit to one and the same ground plane (SLG) forming a ground reference for the electrostatic discharges, this ground plane (SLG) being located outside the integrated circuit (CI), and possibly being a heat slug.
摘要翻译：该电子部件包括在半导体衬底内并入几个单独功能块的集成电路和静电放电保护装置。这些静电放电保护装置包括放置在衬底（SB）上方并分别与多个功能块（CRi）分别相关联的多个单独的金属放电导轨（GNDi），所有这些金属放电导轨在集成电路（CI）内都是电连接的，但是通过集成电路外部的电连接（FLi）电连接到形成用于静电放电的接地基准的同一接地平面（SLG），该接地平面（SLG）位于集成电路（CI）外部，并可能是一个热塞。

3. 发明授权

US08483644B2 Electronic component allowing the decoding of a radiofrequency transmission channel conveying coded digital information, in particular for satellite digital telebroadcasting 有权
公开(公告)号：US08483644B2
公开(公告)日：2013-07-09
申请号：US10150524
申请日：2002-05-17
申请人： Pierre Busson , Bernard Louis-Gavet , Pierre-Olivier Jouffre
发明人： Pierre Busson , Bernard Louis-Gavet , Pierre-Olivier Jouffre
IPC分类号： H04B1/10
CPC分类号： H04N21/6143 , H04L27/06 , H04N7/20
摘要： The component, fully integrated onto a monolithic substrate, includes a tuner, a demodulator, and a channel decoder. The overall filtering is carried out in two parts, a baseband analog filtering and a digital Nyquist filtering removing the information of adjacent channels. It outputs a stream of MPEG data.

4. 发明授权

US07643634B2 Electronic component allowing the decoding of satellite digital television signals 有权
标题翻译：允许对卫星数字电视信号进行解码的电子元件
公开(公告)号：US07643634B2
公开(公告)日：2010-01-05
申请号：US10814818
申请日：2004-03-31
申请人： Pierre Busson , Pierre-Oliver Jouffre , Bernard Louis-Gavet
发明人： Pierre Busson , Pierre-Oliver Jouffre , Bernard Louis-Gavet
IPC分类号： H04N7/167 , H04L25/00 , H04L27/00
CPC分类号： H04N7/20 , H04L27/148
摘要： An integrated circuit is embodied on a monolithic substrate and incorporates a tuning module of the direct sampling type that is able to receive satellite digital television analog signals composed of several channels, as well as several channel decoding digital modules connected at the output of the tuning module so as to deliver respectively simultaneously several streams of data packets corresponding to several different selected channels.
摘要翻译：集成电路体现在单片基板上，并且包括能够接收由几个通道组成的卫星数字电视模拟信号的直接采样类型的调谐模块，以及连接在调谐模块的输出端的多个通道解码数字模块以便分别同时传送与若干不同选择的信道相对应的若干数据分组流。

5. 发明授权

US06584523B1 Device for organizing the access to a memory bus 有权
标题翻译：用于组织对存储器总线访问的设备
公开(公告)号：US06584523B1
公开(公告)日：2003-06-24
申请号：US09478600
申请日：2000-01-06
申请人： Claude Athenes , Bernard Louis-Gavet
发明人： Claude Athenes , Bernard Louis-Gavet
IPC分类号： G06F1300
CPC分类号： G06F13/18
摘要： This invention relates to a device for organizing access to a bus connecting a memory to at least two entities asynchronous binary signals representing requests for access to the bus. The device supplies binary signals to authorize the access to an entity based on a priority determination between the different requests and includes a priority decoder in wired logic associated with an input register. A loading of the state of the access request signals happens, if an access request is present while a read or write cycle of the memory is executed, upon the arrival of a pulse on a signal issued by a memory controller associated with the memory and indicative of the end of a memory cycle.
摘要翻译：本发明涉及一种用于组织对总线的访问的设备，该总线将存储器连接到表示对总线访问的请求的至少两个实体的异步二进制信号。该设备提供二进制信号以根据不同请求之间的优先级确定授权对实体的访问，并且包括与输入寄存器相关联的有线逻辑中的优先级解码器。当存储器的读或写周期执行时存在访问请求信号的状态的加载，当脉冲到由存储器关联的存储器控制器发出的信号和指示的记忆周期结束。

6. 发明授权

US5892760A Device for binary data transfer between a time-division multiplex and a memory 失效
标题翻译：用于在时分多路复用和存储器之间进行二进制数据传输的装置
公开(公告)号：US5892760A
公开(公告)日：1999-04-06
申请号：US690927
申请日：1996-08-01
申请人： Claude Athenes , Jean-Claude Audrix , Bernard Louis-Gavet
发明人： Claude Athenes , Jean-Claude Audrix , Bernard Louis-Gavet
IPC分类号： H04Q11/08 , H04J3/00 , H04L12/52
CPC分类号： H04Q11/08
摘要： A device for transferring binary data between a time-division multiplex and a RAM includes circuitry for assigning, for each time slot of the multiplex, a logical channel number. This enables two HDLC controllers, respectively for transmission and reception, to be shared between all the channels of the multiplex.
摘要翻译：用于在时分复用和RAM之间传送二进制数据的装置包括用于为多路复用的每个时隙分配逻辑信道号的电路。这使得两个HDLC控制器分别用于传输和接收，在多路复用的所有通道之间共享。

7. 发明授权

US6101564A Device for organizing the access to a memory bus 失效
标题翻译：用于组织对存储器总线访问的设备
公开(公告)号：US6101564A
公开(公告)日：2000-08-08
申请号：US690985
申请日：1996-08-01
申请人： Claude Athenes , Bernard Louis-Gavet
发明人： Claude Athenes , Bernard Louis-Gavet
IPC分类号： G06F13/18 , G06F13/00
CPC分类号： G06F13/18
摘要： This invention relates to a device for organizing access to a bus connecting a memory to at least two entities issuing asynchronous binary signals representing requests for access to the bus. The device supplies binary signals to authorize the access to an entity based on a priority determination between the different requests and includes a priority decoder in wired logic associated with an input register. A loading of the state of the access request signals happens, if an access request is present while a read or write cycle of the memory is executed, upon the arrival of a pulse on a signal issued by a memory controller associated with the memory and indicative of the end of a memory cycle.
摘要翻译：本发明涉及一种用于组织对总线的访问的设备，该总线将存储器连接到发出表示对总线访问的请求的异步二进制信号的至少两个实体。该设备提供二进制信号以根据不同请求之间的优先级确定授权对实体的访问，并且包括与输入寄存器相关联的有线逻辑中的优先级解码器。当存储器的读或写周期执行时存在访问请求信号的状态的加载，当脉冲到由存储器关联的存储器控制器发出的信号和指示的记忆周期结束。

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