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1. 发明授权

US06943598B2 Reduced-size integrated phase-locked loop 有权
标题翻译：减小尺寸的集成锁相环
公开(公告)号：US06943598B2
公开(公告)日：2005-09-13
申请号：US10776931
申请日：2004-02-11
申请人： Mostafa Ghazali , Pierre-Olivier Jouffre
发明人： Mostafa Ghazali , Pierre-Olivier Jouffre
IPC分类号： H03L7/089 , H03L7/099 , H03L7/18 , H03L7/06
CPC分类号： H03L7/18 , H03L7/0891 , H03L7/0996
摘要： A phase-locked loop comprising a comparator generating a control voltage depending on the phase-shift between a reference signal and a feedback signal, an oscillator controlled by the control voltage, generating several phase-shifted signals of same period, one of which forms the output signal of the phase-locked loop, a multiplexer capable of providing any of the phase-shifted signals to the input of a divider, the output of which forms the feedback signal, and a means controlling the multiplexer to successively provide fractions of the phase-shifted signals, so that the divider receives a signal having an average period equal to a real fraction of the period of the phase-shifted signals.
摘要翻译：一种锁相环，包括比较器，其产生取决于参考信号和反馈信号之间的相移的控制电压，由控制电压控制的振荡器，产生相同周期的多个相移信号，其中之一形成输出信号的多路复用器，能够将任何相移信号提供给分频器的输入，分频器的输出形成反馈信号，以及控制多路复用器的装置，以连续地提供相位的分数转换信号，使得分频器接收具有等于相移信号的周期的实际分数的平均周期的信号。

2. 发明申请

US20060030285A1 Frequency synthesizer architecture 有权
标题翻译：频率合成器架构
公开(公告)号：US20060030285A1
公开(公告)日：2006-02-09
申请号：US11196492
申请日：2005-08-03
申请人： Mostafa Ghazali , Jouffre Pierre-Olivier
发明人： Mostafa Ghazali , Jouffre Pierre-Olivier
IPC分类号： H04B1/40 , H04B7/00
CPC分类号： H03L7/0996 , H03L7/081 , H03L7/18
摘要： A frequency synthesizer is provided with a PLL, including a divider by N circuit and a phase generation circuit which is connected to the output of the VCO of the PLL. The phase generation circuit generates a predetermined number of phases synchronized on the frequency of the VCO and at intervals from each other equal to a time difference representative of a phase error measured by a phase comparator of the PLL. A signal generation circuit provides an intermediate signal starting from the phases, the period of which is dependent on the time difference and a first adjustment parameter. The intermediate signal is applied to the divider by N circuit. A correction circuit determines the phase error accumulated during N−1 periods of the intermediate signal and makes a correction of the intermediate signal every N periods of the intermediate signal as a function of the accumulated phase error such that the loop becomes stable.
摘要翻译：频率合成器具有PLL，包括N电路的除法器和连接到PLL的VCO的输出的相位产生电路。相位产生电路产生在VCO的频率上同步的预定数量的相位，并且彼此间隔等于表示由PLL的相位比较器测量的相位误差的时间差。信号发生电路提供从相位开始的中间信号，其周期取决于时间差和第一调整参数。中间信号由N电路施加到除法器。校正电路确定在中间信号的N-1个周期期间累积的相位误差，并且作为累积的相位误差的函数对中间信号的每N个周期进行中间信号的校正，使得环路变得稳定。

3. 发明授权

US07298218B2 Frequency synthesizer architecture 有权
标题翻译：频率合成器架构
公开(公告)号：US07298218B2
公开(公告)日：2007-11-20
申请号：US11196492
申请日：2005-08-03
申请人： Mostafa Ghazali , Jouffre Pierre-Olivier
发明人： Mostafa Ghazali , Jouffre Pierre-Olivier
IPC分类号： H03L7/00
CPC分类号： H03L7/0996 , H03L7/081 , H03L7/18
摘要： A frequency synthesizer is provided with a PLL, including a divider by N circuit and a phase generation circuit which is connected to the output of the VCO of the PLL. The phase generation circuit generates a predetermined number of phases synchronized on the frequency of the VCO and at intervals from each other equal to a time difference representative of a phase error measured by a phase comparator of the PLL. A signal generation circuit provides an intermediate signal starting from the phases, the period of which is dependent on the time difference and a first adjustment parameter. The intermediate signal is applied to the divider by N circuit. A correction circuit determines the phase error accumulated during N−1 periods of the intermediate signal and makes a correction of the intermediate signal every N periods of the intermediate signal as a function of the accumulated phase error such that the loop becomes stable.
摘要翻译：频率合成器具有PLL，包括N电路的除法器和连接到PLL的VCO的输出的相位产生电路。相位产生电路产生在VCO的频率上同步的预定数量的相位，并且彼此间隔等于表示由PLL的相位比较器测量的相位误差的时间差。信号发生电路提供从相位开始的中间信号，其周期取决于时间差和第一调整参数。中间信号由N电路施加到除法器。校正电路确定在中间信号的N-1个周期期间累积的相位误差，并且作为累积的相位误差的函数对中间信号的每N个周期进行中间信号的校正，使得环路变得稳定。

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