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1. 发明申请

US20060223305A1 Etch process for CD reduction of arc material 有权
标题翻译：电弧材料的CD还原蚀刻工艺
公开(公告)号：US20060223305A1
公开(公告)日：2006-10-05
申请号：US11098049
申请日：2005-04-04
申请人： Phillip Jones , Mark Chang , Scott Bell
发明人： Phillip Jones , Mark Chang , Scott Bell
IPC分类号： H01L21/4763
CPC分类号： H01L21/32139 , H01L21/3088 , H01L21/31144
摘要： A method of reducing critical dimensions of a feature in a anti-reflective coating layer structure can utilize a polymerizing agent. The anti-reflective coating structure can be utilized to form various integrated circuit structures. The anti-reflective coating can be utilized to form gate stacks comprised of polysilicon and a dielectric layer, conductive lines, or other IC structure. The polymerizing agent can include carbon, hydrogen and fluorine.
摘要翻译：降低抗反射涂层结构中的特征的关键尺寸的方法可以利用聚合剂。抗反射涂层结构可用于形成各种集成电路结构。抗反射涂层可用于形成由多晶硅和电介质层，导电线或其它IC结构组成的栅叠层。聚合剂可以包括碳，氢和氟。

2. 发明授权

US08035153B2 Self-aligned patterning method by using non-conformal film and etch for flash memory and other semiconductor applications 有权
标题翻译：通过使用非保形膜和蚀刻用于闪存和其他半导体应用的自对准图案化方法
公开(公告)号：US08035153B2
公开(公告)日：2011-10-11
申请号：US12788177
申请日：2010-05-26
申请人： Shenqing Fang , Jihwan Choi , Calvin Gabriel , Fei Wang , Angela Hui , Alexander Nickel , Zubin Patel , Phillip Jones , Mark Chang , Minh-Van Ngo
发明人： Shenqing Fang , Jihwan Choi , Calvin Gabriel , Fei Wang , Angela Hui , Alexander Nickel , Zubin Patel , Phillip Jones , Mark Chang , Minh-Van Ngo
IPC分类号： H01L29/788
CPC分类号： H01L21/28282 , H01L27/11568
摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.
摘要翻译：公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于结垢。在本发明中，在电荷俘获层上沉积非保形膜，以在芯源极/漏极区域的顶部形成厚膜，并在STI沟槽顶部形成夹断和空隙或窄通道。在非保形膜上进行蚀刻以打开夹断或在非保形状态下加宽窄通道。然后在核心单元之间完全或部分蚀刻捕获层。去除非保形膜。并形成顶部氧化物。如果捕获层被部分蚀刻，则顶部氧化物将剩余的陷阱层转化为氧化物，并且因此隔离陷阱层。

3. 发明申请

US20100230743A1 SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH FOR FLASH MEMORY AND OTHER SEMICONDUCTOR APPLICATIONS 有权
标题翻译：通过使用非一致性膜和闪存存储器和其他半导体应用的自对准图形方法
公开(公告)号：US20100230743A1
公开(公告)日：2010-09-16
申请号：US12788177
申请日：2010-05-26
申请人： Shenqing Fang , Jihwan Choi , Calvin Gabriel , Fei Wang , Angela Hui , Alexander Nickel , Zubin Patel , Phillip Jones , Mark Chang , Minh-Van Ngo
发明人： Shenqing Fang , Jihwan Choi , Calvin Gabriel , Fei Wang , Angela Hui , Alexander Nickel , Zubin Patel , Phillip Jones , Mark Chang , Minh-Van Ngo
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , H01L27/11568
摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.
摘要翻译：公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于缩放。在本发明中，在电荷俘获层上沉积非保形膜，以在芯源极/漏极区域的顶部形成厚膜，并在STI沟槽顶部形成夹断和空隙或窄通道。在非保形膜上进行蚀刻以打开夹断或在非保形状态下加宽窄通道。然后在核心单元之间完全或部分蚀刻捕获层。去除非保形膜。并形成顶部氧化物。如果捕获层被部分蚀刻，则顶部氧化物将剩余的陷阱层转化为氧化物，并且因此隔离陷阱层。

4. 发明授权

US07732276B2 Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications 有权
标题翻译：通过使用非保形膜的自对准图案化方法，并对闪存和其他半导体应用进行回蚀
公开(公告)号：US07732276B2
公开(公告)日：2010-06-08
申请号：US11796582
申请日：2007-04-26
申请人： Shenqing Fang , Jihwan Choi , Calvin Gabriel , Fei Wang , Angela Hui , Alexander Nickel , Zubin Patel , Phillip Jones , Mark Chang , Minh-Van Ngo
发明人： Shenqing Fang , Jihwan Choi , Calvin Gabriel , Fei Wang , Angela Hui , Alexander Nickel , Zubin Patel , Phillip Jones , Mark Chang , Minh-Van Ngo
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , H01L27/11568
摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.
摘要翻译：公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于缩放。在本发明中，在电荷俘获层上沉积非保形膜，以在芯源极/漏极区域的顶部形成厚膜，并在STI沟槽顶部形成夹断和空隙或窄通道。在非保形膜上进行蚀刻以打开夹断或在非保形状态下加宽窄通道。然后在核心单元之间完全或部分蚀刻捕获层。去除非保形膜。并形成顶部氧化物。如果捕获层被部分蚀刻，则顶部氧化物将剩余的陷阱层转化为氧化物，并且因此隔离陷阱层。

5. 发明申请

US20050092983A1 Sidewall formation for high density polymer memory element array 有权
标题翻译：用于高密度聚合物存储元件阵列的侧壁形成
公开(公告)号：US20050092983A1
公开(公告)日：2005-05-05
申请号：US10699903
申请日：2003-11-03
申请人： Christopher Lyons , Mark Chang , Sergey Lopatin , Ramkumar Subramanian , Patrick Cheung , Minh Ngo , Jane Oglesby
发明人： Christopher Lyons , Mark Chang , Sergey Lopatin , Ramkumar Subramanian , Patrick Cheung , Minh Ngo , Jane Oglesby
IPC分类号： G11C11/56 , G11C13/02 , H01L27/115 , H01L27/28 , H01L29/68 , H01L45/00 , H01L51/00 , H01L29/73
CPC分类号： G11C11/5664 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L27/285 , H01L51/0595
摘要： Systems and methodologies are disclosed for increasing the number of memory cells associated with a lithographic feature. The systems comprise memory elements that are formed on the sidewalls of the lithographic feature by employing various depositing and etching processes. The side wall memory cells can have a bit line of the wafer as the first electrode and operate with a second formed electrode to activate a portion of an organic matter that is formed there between.
摘要翻译：公开了用于增加与光刻特征相关联的存储单元的数量的系统和方法。这些系统包括通过采用各种沉积和蚀刻工艺在光刻特征的侧壁上形成的记忆元件。侧壁存储单元可以具有作为第一电极的晶片的位线，并且与第二形成的电极一起操作以激活在其间形成的有机物的一部分。

6. 发明授权

US06399446B1 Process for fabricating high density memory cells using a metallic hard mask 有权
标题翻译：使用金属硬掩模制造高密度记忆单元的方法
公开(公告)号：US06399446B1
公开(公告)日：2002-06-04
申请号：US09429722
申请日：1999-10-29
申请人： Bharath Rangarajan , David K. Foote , Fei Wang , Dawn M. Hopper , Stephen K. Park , Jack Thomas , Mark Chang , Mark Ramsbey
发明人： Bharath Rangarajan , David K. Foote , Fei Wang , Dawn M. Hopper , Stephen K. Park , Jack Thomas , Mark Chang , Mark Ramsbey
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115 , Y10S438/945
摘要： A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is made from tungsten, titanium, or titanium nitride. The process further includes doping the semiconductor substrate with boron causing p-type regions to form in the semiconductor substrate, and doping the semiconductor substrate with n-type dopants, such as arsenic, causing n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate, and a bit-line oxide region is formed overlying the semiconductor substrate. The hard mask is then stripped, preferably using an H2O2 solution.
摘要翻译：一种用于在二位EEPROM器件中制造存储单元的方法，包括形成覆盖在半导体衬底上的ONO层，沉积覆盖在ONO层上的硬掩模，以及对该硬掩模进行构图。硬掩模由钨，钛或氮化钛制成。该工艺还包括用硼掺杂导致在半导体衬底中形成p型区域的半导体衬底，并且用诸如砷的n型掺杂剂掺杂半导体衬底，从而在半导体衬底中形成n型区域。然后对暴露的ONO层进行蚀刻以暴露半导体衬底的一部分，并且在半导体衬底上形成位线氧化物区域。然后将硬掩模剥离，优选使用H 2 O 2溶液。

7. 发明授权

US5494271A Transmission system for a document feeder 失效
标题翻译：文件传送系统
公开(公告)号：US5494271A
公开(公告)日：1996-02-27
申请号：US257570
申请日：1994-06-10
申请人： Jeffrey Wun , Steven Chiu , Mark Chang
发明人： Jeffrey Wun , Steven Chiu , Mark Chang
IPC分类号： B65H3/06 , B65H5/06
CPC分类号： B65H3/0669 , Y10T74/19172 , Y10T74/1921
摘要： An improved transmission system for a document feeder, in which a constant one-way-rotating gear train is mounted in an output zone so as to cause a transmission shaft in the output zone to rotate in one direction only to send out a sheet of document no matter the driving gear rotates clockwise or counter-clockwise; therefore, as soon as a first sheet of document moves out of the scanning line without moving out of the output zone, the driving gear will change its rotation clockwise so as to have a next sheet of document fed into the scanning zone; therefore, the feeding distance between two sheets of document will be reduced, and consequently the whole feeding time for a document will be reduced, too.
摘要翻译：一种用于文件馈送器的改进的传输系统，其中恒定的单向旋转齿轮系安装在输出区域中，以便使得输出区域中的传动轴在一个方向上旋转，仅发出一张文件无论主动齿轮顺时针还是逆时针旋转; 因此，只要第一张原稿从扫描线移出而不移出输出区域，驱动齿轮将顺时针转动其旋转，以便将下一张原稿送入扫描区域; 因此，两纸张之间的进纸距离将减小，因此文件的整个进纸时间也将减少。

8. 发明申请

US20100099249A1 SELECTIVE SILICIDE FORMATION USING RESIST ETCH BACK 有权
标题翻译：选择性硅胶形成使用耐蚀蚀回填
公开(公告)号：US20100099249A1
公开(公告)日：2010-04-22
申请号：US12644457
申请日：2009-12-22
申请人： Kyunghoon Min , Angela Hui , Hiroyuki Kinoshita , Ning Cheng , Mark Chang
发明人： Kyunghoon Min , Angela Hui , Hiroyuki Kinoshita , Ning Cheng , Mark Chang
IPC分类号： H01L21/285 , H01L21/3205
CPC分类号： H01L27/115 , H01L21/28518 , H01L21/31144 , H01L27/105 , H01L27/1052 , H01L27/11534 , H01L27/11568 , H01L29/665
摘要： Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.
摘要翻译：提供了在存储器件上选择性地形成金属硅化物的方法。所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。

9. 发明授权

US07691751B2 Selective silicide formation using resist etchback 有权
标题翻译：使用抗蚀剂回蚀的选择性硅化物形成
公开(公告)号：US07691751B2
公开(公告)日：2010-04-06
申请号：US11924823
申请日：2007-10-26
申请人： Kyunghoon Min , Angela Hui , Hiroyuki Kinoshita , Ning Cheng , Mark Chang
发明人： Kyunghoon Min , Angela Hui , Hiroyuki Kinoshita , Ning Cheng , Mark Chang
IPC分类号： H01L21/4763
CPC分类号： H01L27/115 , H01L21/28518 , H01L21/31144 , H01L27/105 , H01L27/1052 , H01L27/11534 , H01L27/11568 , H01L29/665
摘要： Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.
摘要翻译：提供了在存储器件上选择性地形成金属硅化物的方法。所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。

10. 发明申请

US20080061359A1 Dual charge storage node with undercut gate oxide for deep sub-micron memory cell 审中-公开
标题翻译：具有底切栅极氧化物的双电荷存储节点用于深亚微米存储单元
公开(公告)号：US20080061359A1
公开(公告)日：2008-03-13
申请号：US11702847
申请日：2007-02-05
申请人： Chungho Lee , Hiroyuki Kinoshita , Zoran Krivokapic , Wei Zheng , Mark Chang , Rinji Sugino , Chi Chang
发明人： Chungho Lee , Hiroyuki Kinoshita , Zoran Krivokapic , Wei Zheng , Mark Chang , Rinji Sugino , Chi Chang
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , H01L27/11521 , H01L29/40114 , H01L29/40117 , H01L29/42332 , H01L29/42348 , H01L29/7885 , H01L29/7887 , H01L29/792 , H01L29/7923
摘要： An embodiment of the present invention is directed to a memory cell. The memory cell includes a stack formed over a substrate. The stack includes a gate oxide layer and an overlying polycrystalline silicon layer. The stack further includes first and second undercut regions formed under the polycrystalline silicon layer and adjacent to the gate oxide layer. The memory cell further includes a first charge storage element formed in the first undercut region and a second charge storage element formed in the second undercut region.
摘要翻译：本发明的实施例涉及存储单元。存储单元包括形成在衬底上的堆叠。堆叠包括栅极氧化物层和上覆的多晶硅层。堆叠还包括形成在多晶硅层下方并与栅极氧化物层相邻的第一和第二底切区域。存储单元还包括形成在第一底切区域中的第一电荷存储元件和形成在第二底切区域中的第二电荷存储元件。

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