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1. 发明授权

US07567464B2 Non-volatile memory device with periodic refresh and method of programming such a device 有权
标题翻译：具有周期性刷新的非易失性存储器件及其编程方法
公开(公告)号：US07567464B2
公开(公告)日：2009-07-28
申请号：US11654383
申请日：2007-01-15
申请人： Philippe Gendrier , Philippe Candelier , Jean-Marc Tessier
发明人： Philippe Gendrier , Philippe Candelier , Jean-Marc Tessier
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G06F11/1008 , G11C16/3431 , G11C16/3459 , G11C2216/10
摘要： A non-volatile memory device includes a network of non-volatile memory cells, each comprising a floating-gate transistor, said network of cells being intended to store data in the form of a set of data words. The device includes a circuit which detects loss of charges stored in the cells and then reprograms the cells for which a loss of charges has been detected so as to restore the level of stored charges.
摘要翻译：非易失性存储器件包括非易失性存储器单元的网络，每个非易失性存储器单元包括浮栅晶体管，所述单元网络旨在以一组数据字的形式存储数据。该装置包括检测存储在单元中的电荷损失的电路，然后对已检测到电荷损失的单元进行重新编程，以恢复存储电荷的电平。

2. 发明申请

US20070183196A1 Non-volatile memory device with periodic refresh and method of programming such a device 有权
标题翻译：具有周期性刷新的非易失性存储器件及其编程方法
公开(公告)号：US20070183196A1
公开(公告)日：2007-08-09
申请号：US11654383
申请日：2007-01-15
申请人： Philippe Gendrier , Philippe Candelier , Jean-Marc Tessier
发明人： Philippe Gendrier , Philippe Candelier , Jean-Marc Tessier
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G06F11/1008 , G11C16/3431 , G11C16/3459 , G11C2216/10
摘要： A non-volatile memory device includes a network of non-volatile memory cells, each comprising a floating-gate transistor, said network of cells being intended to store data in the form of a set of data words. The device includes a circuit which detects loss of charges stored in the cells and then reprograms the cells for which a loss of charges has been detected so as to restore the level of stored charges.
摘要翻译：非易失性存储器件包括非易失性存储器单元的网络，每个非易失性存储器单元包括浮栅晶体管，所述单元网络旨在以一组数据字的形式存储数据。该装置包括检测存储在单元中的电荷损失的电路，然后对已检测到电荷损失的单元进行重新编程，以恢复存储电荷的电平。

3. 发明申请

US20070069278A1 Non-volatile reprogrammable memory 有权
标题翻译：非易失性可编程存储器
公开(公告)号：US20070069278A1
公开(公告)日：2007-03-29
申请号：US11525529
申请日：2006-09-22
申请人： Rachid Bouchakour , Virginie Bidal , Philippe Candelier , Richard Fournel , Philippe Gendrier , Romain Laffont , Pascal Masson , Jean-Michel Mirabel , Arnaud Regnier
发明人： Rachid Bouchakour , Virginie Bidal , Philippe Candelier , Richard Fournel , Philippe Gendrier , Romain Laffont , Pascal Masson , Jean-Michel Mirabel , Arnaud Regnier
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , H01L29/42324
摘要： A non-volatile memory point including a floating gate placed above a semiconductor substrate, the floating gate comprising active portions insulated from the substrate by thin insulating layers, and inactive portions insulated from the substrate by thick insulating layers that do not conduct electrons, the active portions being principally P-type doped, and the inactive portions comprising at least one N-type doped area forming a portion of a PN junction.
摘要翻译：一种非易失性存储点，包括放置在半导体衬底之上的浮动栅极，浮置栅极包括通过薄绝缘层与衬底绝缘的有源部分，以及由不导电的厚绝缘层与衬底绝缘的非活性部分，活性部分主要是P型掺杂的，而非活性部分包括形成PN结的一部分的至少一个N型掺杂区。

4. 发明授权

US07675106B2 Non-volatile reprogrammable memory 有权
标题翻译：非易失性可编程存储器
公开(公告)号：US07675106B2
公开(公告)日：2010-03-09
申请号：US11525529
申请日：2006-09-22
申请人： Rachid Bouchakour , Virginie Bidal , Philippe Candelier , Richard Fournel , Philippe Gendrier , Romain Laffont , Pascal Masson , Jean-Michel Mirabel , Arnaud Regnier
发明人： Rachid Bouchakour , Virginie Bidal , Philippe Candelier , Richard Fournel , Philippe Gendrier , Romain Laffont , Pascal Masson , Jean-Michel Mirabel , Arnaud Regnier
IPC分类号： H01L29/423
CPC分类号： H01L29/7883 , H01L29/42324
摘要： A non-volatile memory point including a floating gate placed above a semiconductor substrate, the floating gate comprising active portions insulated from the substrate by thin insulating layers, and inactive portions insulated from the substrate by thick insulating layers that do not conduct electrons, the active portions being principally P-type doped, and the inactive portions comprising at least one N-type doped area forming a portion of a PN junction.
摘要翻译：一种非易失性存储点，包括放置在半导体衬底之上的浮动栅极，浮置栅极包括通过薄绝缘层与衬底绝缘的有源部分，以及由不导电的厚绝缘层与衬底绝缘的非活性部分，活性部分主要是P型掺杂的，而非活性部分包括形成PN结的一部分的至少一个N型掺杂区。

5. 发明申请

US20050219912A1 Electrically erasable and programmable, non-volatile semiconductor memory device having a single layer of gate material, and corresponding memory plane 有权
标题翻译：具有单层栅极材料的电可擦除和可编程的非易失性半导体存储器件以及相应的存储器平面
公开(公告)号：US20050219912A1
公开(公告)日：2005-10-06
申请号：US10511712
申请日：2003-01-31
申请人： Philippe Gendrier , Cyrille Dray , Richard Fournel , Sebastien Poirier , Daniel Caspar , Philippe Candelier
发明人： Philippe Gendrier , Cyrille Dray , Richard Fournel , Sebastien Poirier , Daniel Caspar , Philippe Candelier
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control gate. The source, drain and channel regions of the floating-gate transistor form the control gate. Moreover, the memory cell includes a dielectric zone lying between a first part of the layer of gate material and a first semiconductor active zone electrically isolated from a second active zone incorporating the control gate. This dielectric zone then forms a tunnel zone for transferring, during erasure of the cell, the charges stored in the floating gate to the first active zone.
摘要翻译：半导体存储器件包括具有单层栅极材料并且包括浮栅晶体管和控制栅的电可擦除可编程非易失性存储单元。浮栅晶体管的源极，漏极和沟道区域形成控制栅极。此外，存储单元包括位于栅极材料层的第一部分和与结合有控制栅极的第二有源区电隔离的第一半导体有源区之间的介电区。该介电区随后形成隧道区，用于在电池擦除期间将存储在浮动栅极中的电荷转移到第一活性区。

6. 发明授权

US07333362B2 Electrically erasable and programmable, non-volatile semiconductor memory device having a single layer of gate material, and corresponding memory plane 有权
标题翻译：具有单层栅极材料的电可擦除和可编程的非易失性半导体存储器件以及相应的存储器平面
公开(公告)号：US07333362B2
公开(公告)日：2008-02-19
申请号：US10511712
申请日：2003-01-31
申请人： Philippe Gendrier , Cyrille Dray , Richard Fournel , Sébastien Poirier , Daniel Caspar , Philippe Candelier
发明人： Philippe Gendrier , Cyrille Dray , Richard Fournel , Sébastien Poirier , Daniel Caspar , Philippe Candelier
IPC分类号： G11C16/04
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control gate. The source, drain and channel regions of the floating-gate transistor form the control gate. Moreover, the memory cell includes a dielectric zone lying between a first part of the layer of gate material and a first semiconductor active zone electrically isolated from a second active zone incorporating the control gate. This dielectric zone then forms a tunnel zone for transferring, during erasure of the cell, the charges stored in the floating gate to the first active zone.
摘要翻译：半导体存储器件包括具有单层栅极材料并且包括浮栅晶体管和控制栅的电可擦除可编程非易失性存储单元。浮栅晶体管的源极，漏极和沟道区域形成控制栅极。此外，存储单元包括位于栅极材料层的第一部分和与结合有控制栅极的第二有源区电隔离的第一半导体有源区之间的介电区。该介电区随后形成隧道区，用于在电池擦除期间将存储在浮动栅极中的电荷转移到第一活性区。

7. 发明申请

US20060075320A1 Method of detecting and correcting errors for a memory and corresponding integrated circuit 有权
公开(公告)号：US20060075320A1
公开(公告)日：2006-04-06
申请号：US11220515
申请日：2005-09-07
申请人： Philippe Gendrier , Philippe Candelier , Richard Fournel
发明人： Philippe Gendrier , Philippe Candelier , Richard Fournel
IPC分类号： G11C29/00
CPC分类号： H03M13/37 , H03M13/09 , H03M13/19 , H03M13/35
摘要： A method is for detecting and correcting errors for a memory storing at least one code block including information data and control data. The method includes reading and decoding each element of the at least one code block to deliver an information item representative of a number of errors in the at least one code block. The method further includes, when the number of errors exceeds one, modifying a parameter of the read by a chosen value, and performing a reading and decoding of the at least one code block again to obtain a new error information item.

8. 发明申请

US20090250737A1 SECURE MEMORY DEVICE OF THE ONE-TIME PROGRAMMABLE TYPE 审中-公开
标题翻译：一次性可编程类型的安全存储器件
公开(公告)号：US20090250737A1
公开(公告)日：2009-10-08
申请号：US12419921
申请日：2009-04-07
申请人： Philippe Candelier , Philippe Gendrier , Joel Damiens , Elise Le Roux
发明人： Philippe Candelier , Philippe Gendrier , Joel Damiens , Elise Le Roux
IPC分类号： H01L29/94 , H01L29/00
CPC分类号： G11C17/16 , G11C7/24
摘要： The integrated circuit includes a memory device of the irreversibly electrically programmable type. This device includes several memory cells, each memory cell having a dielectric zone positioned between a first electrode and a second electrode. Each memory cell is further associated with an access transistor. At least one first electrically conductive link electrically couples to the first electrodes of at least two memory cells, these first two electrodes being coupled to one and the same bias voltage. The first electrically conductive link is positioned in substantially a same plane as the first electrodes of the two memory cells.
摘要翻译：集成电路包括不可逆电可编程类型的存储器件。该装置包括几个存储单元，每个存储单元具有位于第一电极和第二电极之间的介电区。每个存储单元还与存取晶体管相关联。至少一个第一导电链路电耦合到至少两个存储器单元的第一电极，这些前两个电极耦合到同一偏置电压。第一导电连接件位于与两个存储单元的第一电极基本相同的平面中。

9. 发明授权

US07502985B2 Method of detecting and correcting errors for a memory and corresponding integrated circuit 有权
标题翻译：检测和校正存储器和相应集成电路的误差的方法
公开(公告)号：US07502985B2
公开(公告)日：2009-03-10
申请号：US11220515
申请日：2005-09-07
申请人： Philippe Gendrier , Philippe Candelier , Richard Fournel
发明人： Philippe Gendrier , Philippe Candelier , Richard Fournel
IPC分类号： G11C16/26 , G11C29/00
CPC分类号： H03M13/37 , H03M13/09 , H03M13/19 , H03M13/35
摘要： A method is for detecting and correcting errors for a memory storing at least one code block including information data and control data. The method includes reading and decoding each element of the at least one code block to deliver an information item representative of a number of errors in the at least one code block. The method further includes, when the number of errors exceeds one, modifying a parameter of the read by a chosen value, and performing a reading and decoding of the at least one code block again to obtain a new error information item.
摘要翻译：一种用于检测和校正存储至少一个包括信息数据和控制数据的代码块的存储器的错误的方法。该方法包括读取和解码至少一个代码块的每个元素，以传递表示至少一个代码块中的多个错误的信息项。该方法还包括当错误数超过1时，通过选择的值修改读取的参数，并且再次执行至少一个代码块的读取和解码以获得新的错误信息项。

10. 发明申请

US20070114596A1 Integrated electronic circuit incorporating a capacitor 有权
标题翻译：集成电子电路
公开(公告)号：US20070114596A1
公开(公告)日：2007-05-24
申请号：US11600584
申请日：2006-11-15
申请人： Philippe Candelier , Thierry Devoivre , Emmanuel Josse , Sebastien Lefebvre
发明人： Philippe Candelier , Thierry Devoivre , Emmanuel Josse , Sebastien Lefebvre
IPC分类号： H01L29/792
CPC分类号： H01L27/0207 , H01L27/112 , H01L27/11206 , H01L27/11246
摘要： A non-volatile memory element includes a transistor for selecting the element and a capacitor for recording a binary value by electrical breakdown of an insulating layer (13) of the capacitor. A structure of the memory element is modified in order to allow a higher degree of integration of the element within an electronic circuit of the MOS type. In addition, the memory element is made more robust with respect to a high electrical voltage (VDD) used for recording the binary value. The transistor includes a drain in the substrate with electric field drift in a longitudinal direction extending towards the capacitor. The electric field drift region for the drain includes a first extension underneath the gate of the transistor opposite the source and a second extension underneath the insulating layer of the capacitor. Doping of the substrate for the electric field drift region is limited to a region substantially corresponding to a distance between the gate and an electrode of the capacitor.
摘要翻译：非易失性存储元件包括用于选择元件的晶体管和用于通过电容器的绝缘层（13）的电击穿记录二进制值的电容器。修改存储元件的结构，以便允许元件在MOS类型的电子电路内更高程度的集成。此外，存储元件相对于用于记录二进制值的高电压（VDD）更加鲁棒。该晶体管包括在衬底中的漏极，该漏极沿朝向该电容器延伸的纵向方向具有电场漂移。用于漏极的电场漂移区域包括与源极相对的晶体管的栅极下面的第一延伸部分和在电容器的绝缘层下方的第二延伸部分。用于电场漂移区域的衬底的掺杂限于基本上对应于电容器的栅极和电极之间的距离的区域。

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