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1. 发明申请

US20070069278A1 Non-volatile reprogrammable memory 有权
标题翻译：非易失性可编程存储器
公开(公告)号：US20070069278A1
公开(公告)日：2007-03-29
申请号：US11525529
申请日：2006-09-22
申请人： Rachid Bouchakour , Virginie Bidal , Philippe Candelier , Richard Fournel , Philippe Gendrier , Romain Laffont , Pascal Masson , Jean-Michel Mirabel , Arnaud Regnier
发明人： Rachid Bouchakour , Virginie Bidal , Philippe Candelier , Richard Fournel , Philippe Gendrier , Romain Laffont , Pascal Masson , Jean-Michel Mirabel , Arnaud Regnier
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , H01L29/42324
摘要： A non-volatile memory point including a floating gate placed above a semiconductor substrate, the floating gate comprising active portions insulated from the substrate by thin insulating layers, and inactive portions insulated from the substrate by thick insulating layers that do not conduct electrons, the active portions being principally P-type doped, and the inactive portions comprising at least one N-type doped area forming a portion of a PN junction.
摘要翻译：一种非易失性存储点，包括放置在半导体衬底之上的浮动栅极，浮置栅极包括通过薄绝缘层与衬底绝缘的有源部分，以及由不导电的厚绝缘层与衬底绝缘的非活性部分，活性部分主要是P型掺杂的，而非活性部分包括形成PN结的一部分的至少一个N型掺杂区。

2. 发明申请

US20050219912A1 Electrically erasable and programmable, non-volatile semiconductor memory device having a single layer of gate material, and corresponding memory plane 有权
标题翻译：具有单层栅极材料的电可擦除和可编程的非易失性半导体存储器件以及相应的存储器平面
公开(公告)号：US20050219912A1
公开(公告)日：2005-10-06
申请号：US10511712
申请日：2003-01-31
申请人： Philippe Gendrier , Cyrille Dray , Richard Fournel , Sebastien Poirier , Daniel Caspar , Philippe Candelier
发明人： Philippe Gendrier , Cyrille Dray , Richard Fournel , Sebastien Poirier , Daniel Caspar , Philippe Candelier
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control gate. The source, drain and channel regions of the floating-gate transistor form the control gate. Moreover, the memory cell includes a dielectric zone lying between a first part of the layer of gate material and a first semiconductor active zone electrically isolated from a second active zone incorporating the control gate. This dielectric zone then forms a tunnel zone for transferring, during erasure of the cell, the charges stored in the floating gate to the first active zone.
摘要翻译：半导体存储器件包括具有单层栅极材料并且包括浮栅晶体管和控制栅的电可擦除可编程非易失性存储单元。浮栅晶体管的源极，漏极和沟道区域形成控制栅极。此外，存储单元包括位于栅极材料层的第一部分和与结合有控制栅极的第二有源区电隔离的第一半导体有源区之间的介电区。该介电区随后形成隧道区，用于在电池擦除期间将存储在浮动栅极中的电荷转移到第一活性区。

3. 发明授权

US07675106B2 Non-volatile reprogrammable memory 有权
标题翻译：非易失性可编程存储器
公开(公告)号：US07675106B2
公开(公告)日：2010-03-09
申请号：US11525529
申请日：2006-09-22
申请人： Rachid Bouchakour , Virginie Bidal , Philippe Candelier , Richard Fournel , Philippe Gendrier , Romain Laffont , Pascal Masson , Jean-Michel Mirabel , Arnaud Regnier
发明人： Rachid Bouchakour , Virginie Bidal , Philippe Candelier , Richard Fournel , Philippe Gendrier , Romain Laffont , Pascal Masson , Jean-Michel Mirabel , Arnaud Regnier
IPC分类号： H01L29/423
CPC分类号： H01L29/7883 , H01L29/42324
摘要： A non-volatile memory point including a floating gate placed above a semiconductor substrate, the floating gate comprising active portions insulated from the substrate by thin insulating layers, and inactive portions insulated from the substrate by thick insulating layers that do not conduct electrons, the active portions being principally P-type doped, and the inactive portions comprising at least one N-type doped area forming a portion of a PN junction.
摘要翻译：一种非易失性存储点，包括放置在半导体衬底之上的浮动栅极，浮置栅极包括通过薄绝缘层与衬底绝缘的有源部分，以及由不导电的厚绝缘层与衬底绝缘的非活性部分，活性部分主要是P型掺杂的，而非活性部分包括形成PN结的一部分的至少一个N型掺杂区。

4. 发明授权

US07502985B2 Method of detecting and correcting errors for a memory and corresponding integrated circuit 有权
标题翻译：检测和校正存储器和相应集成电路的误差的方法
公开(公告)号：US07502985B2
公开(公告)日：2009-03-10
申请号：US11220515
申请日：2005-09-07
申请人： Philippe Gendrier , Philippe Candelier , Richard Fournel
发明人： Philippe Gendrier , Philippe Candelier , Richard Fournel
IPC分类号： G11C16/26 , G11C29/00
CPC分类号： H03M13/37 , H03M13/09 , H03M13/19 , H03M13/35
摘要： A method is for detecting and correcting errors for a memory storing at least one code block including information data and control data. The method includes reading and decoding each element of the at least one code block to deliver an information item representative of a number of errors in the at least one code block. The method further includes, when the number of errors exceeds one, modifying a parameter of the read by a chosen value, and performing a reading and decoding of the at least one code block again to obtain a new error information item.
摘要翻译：一种用于检测和校正存储至少一个包括信息数据和控制数据的代码块的存储器的错误的方法。该方法包括读取和解码至少一个代码块的每个元素，以传递表示至少一个代码块中的多个错误的信息项。该方法还包括当错误数超过1时，通过选择的值修改读取的参数，并且再次执行至少一个代码块的读取和解码以获得新的错误信息项。

5. 发明授权

US07333362B2 Electrically erasable and programmable, non-volatile semiconductor memory device having a single layer of gate material, and corresponding memory plane 有权
标题翻译：具有单层栅极材料的电可擦除和可编程的非易失性半导体存储器件以及相应的存储器平面
公开(公告)号：US07333362B2
公开(公告)日：2008-02-19
申请号：US10511712
申请日：2003-01-31
申请人： Philippe Gendrier , Cyrille Dray , Richard Fournel , Sébastien Poirier , Daniel Caspar , Philippe Candelier
发明人： Philippe Gendrier , Cyrille Dray , Richard Fournel , Sébastien Poirier , Daniel Caspar , Philippe Candelier
IPC分类号： G11C16/04
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control gate. The source, drain and channel regions of the floating-gate transistor form the control gate. Moreover, the memory cell includes a dielectric zone lying between a first part of the layer of gate material and a first semiconductor active zone electrically isolated from a second active zone incorporating the control gate. This dielectric zone then forms a tunnel zone for transferring, during erasure of the cell, the charges stored in the floating gate to the first active zone.
摘要翻译：半导体存储器件包括具有单层栅极材料并且包括浮栅晶体管和控制栅的电可擦除可编程非易失性存储单元。浮栅晶体管的源极，漏极和沟道区域形成控制栅极。此外，存储单元包括位于栅极材料层的第一部分和与结合有控制栅极的第二有源区电隔离的第一半导体有源区之间的介电区。该介电区随后形成隧道区，用于在电池擦除期间将存储在浮动栅极中的电荷转移到第一活性区。

6. 发明申请

US20060075320A1 Method of detecting and correcting errors for a memory and corresponding integrated circuit 有权
公开(公告)号：US20060075320A1
公开(公告)日：2006-04-06
申请号：US11220515
申请日：2005-09-07
申请人： Philippe Gendrier , Philippe Candelier , Richard Fournel
发明人： Philippe Gendrier , Philippe Candelier , Richard Fournel
IPC分类号： G11C29/00
CPC分类号： H03M13/37 , H03M13/09 , H03M13/19 , H03M13/35
摘要： A method is for detecting and correcting errors for a memory storing at least one code block including information data and control data. The method includes reading and decoding each element of the at least one code block to deliver an information item representative of a number of errors in the at least one code block. The method further includes, when the number of errors exceeds one, modifying a parameter of the read by a chosen value, and performing a reading and decoding of the at least one code block again to obtain a new error information item.

7. 发明申请

US20060139990A1 Pre-written volatile memory cell 有权
标题翻译：预写易失性存储单元
公开(公告)号：US20060139990A1
公开(公告)日：2006-06-29
申请号：US11261396
申请日：2005-10-25
申请人： Philippe Candelier , Jean Lasseuguette , Richard Fournel
发明人： Philippe Candelier , Jean Lasseuguette , Richard Fournel
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A memory cell of the SRAM type Is provided that is capable of storing one datum in a non-volatile manner. The memory cell includes two inverters (20 and 21) configured as a flip-flop for storing one bit. Each inverter includes a transistor (24 or 26) of a first type and a transistor (25 or 27) of a second type. The concentration of carriers in the conduction channel of the transistor (24) of the first type of one of the inverters (20) is different from the concentration of carriers in the conduction channel of the transistor (26) of the first type of the other inverter (21) so that the inverters have different threshold voltages.
摘要翻译：提供了SRAM类型的存储单元，其能够以非易失性方式存储一个数据。存储单元包括配置为用于存储一位的触发器的两个反相器（20和21）。每个反相器包括第一类型的晶体管（24或26）和第二类型的晶体管（25或27）。第一类型的反相器（20）中的第一类型的晶体管（24）的导通通道中的载流子的浓度不同于第一类型的另一个的另一个的晶体管（26）的导通通道中的载流子的浓度逆变器（21），使逆变器具有不同的阈值电压。

8. 发明授权

US06977840B2 Storage element with a defined number of write cycles 有权
标题翻译：具有定义写入周期数的存储元件
公开(公告)号：US06977840B2
公开(公告)日：2005-12-20
申请号：US10453466
申请日：2003-06-03
申请人： Richard Fournel , Jean-Pierre Schoellkopf , Philippe Candelier
发明人： Richard Fournel , Jean-Pierre Schoellkopf , Philippe Candelier
IPC分类号： G11C8/12 , G11C16/08 , G11C11/34
CPC分类号： G11C8/12 , G11C16/08
摘要： A few times programmable (FTP) storage element is provided. The FTP storage element includes a set of N elementary memory units and multiple selection circuits. Each of the elementary memory units includes an address bus for connection to a main address bus and a data bus for connection to a main data bus. The selection circuits generate successive selection signals for successively selecting one of the elementary memory units in order to give exclusive access to the one selected elementary memory unit. The selection circuits operate so as to automatically select a next one of the elementary memory units upon detection of a predetermined condition. In preferred embodiments, each of the elementary memory units is programmable.
摘要翻译：提供了几次可编程（FTP）存储元件。 FTP存储元件包括一组N个基本存储器单元和多个选择电路。每个基本存储器单元包括用于连接到主地址总线的地址总线和用于连接到主数据总线的数据总线。选择电路产生连续的选择信号，用于连续选择一个基本存储器单元，以给予对所选择的一个基本存储单元的独占访问。选择电路工作，以便在检测到预定条件时自动选择下一个基本存储器单元。在优选实施例中，每个基本存储器单元是可编程的。

9. 发明授权

US07289355B2 Pre-written volatile memory cell 有权
标题翻译：预写易失性存储单元
公开(公告)号：US07289355B2
公开(公告)日：2007-10-30
申请号：US11261396
申请日：2005-10-25
申请人： Philippe Candelier , Jean Lasseuguette , Richard Fournel
发明人： Philippe Candelier , Jean Lasseuguette , Richard Fournel
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A memory cell of the SRAM type is provided that is capable of storing one datum in a non-volatile manner. The memory cell includes two inverters (20 and 21) configured as a flip-flop for storing one bit. Each inverter includes a transistor (24 or 26) of a first type and a transistor (25 or 27) of a second type. The concentration of carriers in the conduction channel of the transistor (24) of the first type of one of the inverters (20) is different from the concentration of carriers in the conduction channel of the transistor (26) of the first type of the other inverter (21) so that the inverters have different threshold voltages.
摘要翻译：提供了SRAM类型的存储单元，其能够以非易失性方式存储一个数据。存储单元包括配置为用于存储一位的触发器的两个反相器（20和21）。每个反相器包括第一类型的晶体管（24或26）和第二类型的晶体管（25或27）。第一类型的反相器（20）中的第一类型的晶体管（24）的导通通道中的载流子的浓度不同于第一类型的另一个的另一个的晶体管（26）的导通通道中的载流子的浓度逆变器（21），使逆变器具有不同的阈值电压。

10. 发明授权

US07184299B2 Nonvolatile SRAM memory cell 有权
标题翻译：非易失SRAM存储单元
公开(公告)号：US07184299B2
公开(公告)日：2007-02-27
申请号：US10726263
申请日：2003-12-02
申请人： Richard Fournel , Emmanuel Vincent , Sylvie Bruyere , Philippe Candelier , Francois Jacquet
发明人： Richard Fournel , Emmanuel Vincent , Sylvie Bruyere , Philippe Candelier , Francois Jacquet
IPC分类号： G11C11/00
CPC分类号： G11C14/00 , G11C17/14
摘要： An SRAM memory cell includes first and second inverters (14, 16) interconnected between first and second data nodes. Each inverter is formed from complementary MOS transistors (18, 20, 18′, 20′) connected in series between a DC voltage supply source and a grounding circuit (22). A circuit (28, 30) programs the MOS transistors by causing an irreversible degradation of a gate oxide layer of at least some of the transistors (18, 18′).
摘要翻译： SRAM存储单元包括在第一和第二数据节点之间互连的第一和第二反相器（14,16）。每个反相器由串联连接在DC电压源和接地电路（22）之间的互补MOS晶体管（18,20,18'，20'）形成。电路（28,30）通过使至少一些晶体管（18,18'）的栅极氧化层不可逆地退化来对MOS晶体管进行编程。

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