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1. 发明申请

US20060062155A1 METHOD FOR IP CHARACTERIZATION AND PATH FINDING, AND COMPUTER READABLE RECORDING MEDIUM FOR STORING PROGRAM THEREOF 失效
标题翻译： IP特征和路径查找方法及其存储程序的计算机可读记录介质
公开(公告)号：US20060062155A1
公开(公告)日：2006-03-23
申请号：US10711472
申请日：2004-09-21
申请人： Peter Hanping Chen , Chih-Fu Chien , Jyh-Herng Wang , Hsu-Hui Tsai
发明人： Peter Hanping Chen , Chih-Fu Chien , Jyh-Herng Wang , Hsu-Hui Tsai
IPC分类号： H04J1/16
CPC分类号： G01R31/318371
摘要： IP characterization and for path finding methods, and a computer readable recording medium for storing program are provided. First, an Intellectual Property (IP) component is provided. Then, a plurality of test patterns for all paths in the IP component is automatically generated. The test patterns are then sequentially input into the IP component for simulation, and a plurality of corresponding simulation results is generated. Finally, an IP characteristic library is generated based on the simulation results.
摘要翻译： IP表征和路径查找方法，以及用于存储程序的计算机可读记录介质。首先，提供知识产权（IP）组件。然后，自动生成IP分量中的所有路径的多个测试模式。然后将测试模式顺序地输入到IP组件中用于模拟，并且生成多个相应的模拟结果。最后，根据仿真结果生成IP特征库。

2. 发明授权

US07516058B2 Method for IP characterization and path finding, and computer readable recording medium for storing program thereof 失效
标题翻译：用于IP表征和路径查找的方法，以及用于存储其程序的计算机可读记录介质
公开(公告)号：US07516058B2
公开(公告)日：2009-04-07
申请号：US10711472
申请日：2004-09-21
申请人： Peter Hanping Chen , Chih-Fu Chien , Jyh-Herng Wang , Hsu-Hui Tsai
发明人： Peter Hanping Chen , Chih-Fu Chien , Jyh-Herng Wang , Hsu-Hui Tsai
IPC分类号： G06F17/50
CPC分类号： G01R31/318371
摘要： IP characterization and for path finding methods, and a computer readable recording medium for storing program are provided. First, an Intellectual Property (IP) component is provided. Then, a plurality of test patterns for all paths in the IP component is automatically generated. The test patterns are then sequentially input into the IP component for simulation, and a plurality of corresponding simulation results is generated. Finally, an IP characteristic library is generated based on the simulation results.
摘要翻译： IP表征和路径查找方法，以及用于存储程序的计算机可读记录介质。首先，提供知识产权（IP）组件。然后，自动生成IP分量中的所有路径的多个测试模式。然后将测试模式顺序地输入到IP组件中用于模拟，并且生成多个相应的模拟结果。最后，根据仿真结果生成IP特征库。

3. 发明申请

US20060271889A1 METHOD OF FINDING DRIVING STRENGTH AND COMPUTER ACCESSIBLE RECORD MEDIUM TO STORE PROGRAM THEREOF 失效
标题翻译：发现驱动力的方法和计算机可访问记录介质存储其程序
公开(公告)号：US20060271889A1
公开(公告)日：2006-11-30
申请号：US10908748
申请日：2005-05-25
申请人： Peter H. Chen , Chih-Fu Chien , Han-chi Liu , Jyh-Herng Wang
发明人： Peter H. Chen , Chih-Fu Chien , Han-chi Liu , Jyh-Herng Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method of finding a driving strength and a record medium accessible by a computer to store a program thereof are provided. The method is adapted to find the driving strength of an output pin of a target cell. Wherein, the driving strength of the output pin of the target cell is provided from the driving strength of a corresponding last level device. In this method, at least one candidate standard cell is searched in a standard cell library according to the last level device. Then, the driving strength of the target cell is interpolated between the driving strengths of the candidate standard cells to obtain the driving strength of the output pin of the target cell.
摘要翻译：提供了一种找到驱动强度的方法和一种可由计算机访问以存储其程序的记录介质。该方法适于找出目标单元的输出引脚的驱动强度。其中，从相应的最后一级装置的驱动强度提供目标单元的输出引脚的驱动强度。在该方法中，根据最后一级设备在标准单元库中搜索至少一个候选标准单元。然后，在候选标准单元的驱动强度之间插入目标单元的驱动强度，以获得目标单元的输出引脚的驱动强度。

4. 发明授权

US07389488B2 Method of finding driving strength and computer accessible record medium to store program thereof 失效
标题翻译：寻找驾驶强度的方法和计算机可访问记录介质来存储其程序
公开(公告)号：US07389488B2
公开(公告)日：2008-06-17
申请号：US10908748
申请日：2005-05-25
申请人： Peter H. Chen , Chih-Fu Chien , Han-chi Liu , Jyh-Herng Wang
发明人： Peter H. Chen , Chih-Fu Chien , Han-chi Liu , Jyh-Herng Wang
IPC分类号： G06F17/50 , H03K19/00
CPC分类号： G06F17/5036
摘要： A method of finding a driving strength and a record medium accessible by a computer to store a program thereof are provided. The method is adapted to find the driving strength of an output pin of a target cell. Wherein, the driving strength of the output pin of the target cell is provided from the driving strength of a corresponding last level device. In this method, at least one candidate standard cell is searched in a standard cell library according to the last level device. Then, the driving strength of the target cell is interpolated between the driving strengths of the candidate standard cells to obtain the driving strength of the output pin of the target cell.
摘要翻译：提供了一种找到驱动强度的方法和一种可由计算机访问以存储其程序的记录介质。该方法适于找出目标单元的输出引脚的驱动强度。其中，从相应的最后一级装置的驱动强度提供目标单元的输出引脚的驱动强度。在该方法中，根据最后一级设备在标准单元库中搜索至少一个候选标准单元。然后，在候选标准单元的驱动强度之间插入目标单元的驱动强度，以获得目标单元的输出引脚的驱动强度。

5. 发明授权

US06380788B1 Programmable clock trunk architecture 失效
标题翻译：可编程时钟中继架构
公开(公告)号：US06380788B1
公开(公告)日：2002-04-30
申请号：US09853179
申请日：2001-05-09
申请人： Chen-Teng Fan , Jyh-Herng Wang , Yu-Wen Tsai , Peng-Chuan Huang
发明人： Chen-Teng Fan , Jyh-Herng Wang , Yu-Wen Tsai , Peng-Chuan Huang
IPC分类号： H03K300
CPC分类号： H03K19/1774 , G06F1/10 , H03K5/15013 , H03K19/1778
摘要： A clock architecture including a clock source, a multi-phase clock signal generator, a control bus, a number of clock signal lines, and at least one circuit block. The clock source generates a global clock signal, which is then transferred to the multi-phase clock signal generator connected to the clock source. Upon receipt of global clock signal, the multi-phase clock signal generator, which is connected to a control bus, generates clock signals of different phases according to the signals from the control bus. Each of the clock signal branches transfers one of the clock signals of different phases, wherein each of the clock signal branches is individually connected to the circuit block through an electrical switch. Only one switch is at an on state at one time, so that the clock signal of a corresponding phase is transferred to the circuit block. The driving forces applied on the clock buffer connected to the clock source and the clock buffers on the branches are adjustable for reducing clock skew. Alternately, programmable delay buffers can be used for achieving the same goal.
摘要翻译：一种时钟架构，包括时钟源，多相时钟信号发生器，控制总线，多个时钟信号线以及至少一个电路块。时钟源产生一个全局时钟信号，然后传输到连接到时钟源的多相时钟信号发生器。在接收到全局时钟信号时，连接到控制总线的多相时钟信号发生器根据来自控制总线的信号产生不同相位的时钟信号。每个时钟信号分支传送不同相位的时钟信号中的一个，其中每个时钟信号分支通过电开关单独连接到电路块。一次只有一个开关处于导通状态，使相应相位的时钟信号传送到电路块。连接到时钟源的时钟缓冲器和分支上的时钟缓冲器的驱动力可调，以减少时钟偏移。或者，可以使用可编程延迟缓冲器来实现相同的目标。

6. 发明申请

US20070033547A1 Input capacitance characterization method in IP library 失效
标题翻译： IP库中的输入电容表征方法
公开(公告)号：US20070033547A1
公开(公告)日：2007-02-08
申请号：US11197820
申请日：2005-08-05
申请人： Peter Chen , Han-Chi Liu , Chih-Yang Peng , Jyh-Herng Wang , Chia-Nan Hong
发明人： Peter Chen , Han-Chi Liu , Chih-Yang Peng , Jyh-Herng Wang , Chia-Nan Hong
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A methodology for characterization of an IP (Intellectual Property) component is provided. Digital pins are recognized by skipping analog pins and special IO pins. First two layers of the IP component are classified in response to connection of the input pins. Partial circuits of the IP component are extracted for simulation. Three corners of IP library are generated. Therefore, input capacitance of the IP component is simulated.
摘要翻译：提供了一个用于表征知识产权（知识产权）组件的方法。通过跳过模拟引脚和特殊IO引脚可识别数字引脚。响应于输入引脚的连接，将IP组件的前两层分类。提取IP组件的部分电路进行仿真。生成IP库的三个角落。因此，模拟IP组件的输入电容。

7. 发明申请

US20070214438A1 METHOD FOR STATIC POWER CHARACTERIZATION OF AN INTEGRATED CIRCUIT 审中-公开
标题翻译：用于集成电路静态功率表征的方法
公开(公告)号：US20070214438A1
公开(公告)日：2007-09-13
申请号：US11308154
申请日：2006-03-09
申请人： Peter H. Chen Hanping Chen , Jyh-Herng Wang , Chih-Yang Peng , Han-Chi Liu , Hsin-Hung Chen , Kun-Cheng Wu
发明人： Peter H. Chen Hanping Chen , Jyh-Herng Wang , Chih-Yang Peng , Han-Chi Liu , Hsin-Hung Chen , Kun-Cheng Wu
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method for static power characterization of an analog integrated circuit includes detecting whether each of a plurality of input pins is electrically connected to a specific circuit; selecting a plurality of test benches of the static power characterization according to a number of the input pins electrically connected to the specific circuit; and processing the plurality of selected test benches of the static power characterization.
摘要翻译：一种用于模拟集成电路的静态功率表征的方法包括检测多个输入引脚中的每一个是否电连接到特定电路; 根据电连接到特定电路的输入引脚的数量来选择静态功率表征的多个测试台; 以及处理静态功率表征的多个选定测试台。

8. 发明授权

US06404222B1 Chip capacitance measurement circuit 失效
标题翻译：片式电容测量电路
公开(公告)号：US06404222B1
公开(公告)日：2002-06-11
申请号：US09631342
申请日：2000-08-02
申请人： Chen-Teng Fan , Jyh-Herng Wang
发明人： Chen-Teng Fan , Jyh-Herng Wang
IPC分类号： G01R3126
CPC分类号： G01R27/2605 , G01R31/2639
摘要： A silicon chip capacitance measurement circuit including three pairs of completely matched MOS transistors divided into two symmetrical circuits. Capacitance of a capacitor within the silicon chip is measured using the difference in average charging current flowing from the measurement circuit via a left and a right capacitor. A power supply provides a constant voltage source to the measurement circuit. A current measuring device measures the current flowing from the power supply to the measurement circuit. A signal generator provides a group of three-phase non-overlapping signals to the measurement circuit. The capacitance measurement circuit is able to limit measurement error due to the return of different size negative currents leading to the transient switching of MOS transistors in the current measurement device so that accuracy of capacitance measurement improves.
摘要翻译：一种硅芯片电容测量电路，包括三对完全匹配的MOS晶体管，分为两个对称电路。使用从测量电路经由左右电容器流出的平均充电电流的差异来测量硅芯片内的电容器的电容。电源为测量电路提供恒定电压源。电流测量装置测量从电源流向测量电路的电流。信号发生器向测量电路提供一组三相不重叠的信号。电容测量电路能够限制由于不同尺寸的负电流的返回导致的测量误差，导致电流测量装置中的MOS晶体管的瞬态切换，从而提高了电容测量的精度。

9. 发明授权

US07530035B2 Automatic power grid synthesis method and computer readable recording medium for storing program thereof 失效
标题翻译：自动电网合成方法和用于存储其程序的计算机可读记录介质
公开(公告)号：US07530035B2
公开(公告)日：2009-05-05
申请号：US11212295
申请日：2005-08-25
申请人： Jyh-Herng Wang
发明人： Jyh-Herng Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/78 , Y02E60/76 , Y04S40/22
摘要： An automatic power grid synthesis method and a computer readable recording medium for storing a program thereof for synthesizing power grid in a circuit area are provided. The circuit area has at least one power consuming module therein and at least one power pin disposed around the circuit area. The method includes the following steps. First, select at least one representative point in each power consuming module. The circuit area is divided into a plurality of regions according to the positions of the representative point(s) and the power pin. An overall power grid density of each region is calculated in accordance with the position of each power pin and the power consumption or current requirement at each representative point. Finally, the power grid synthesis is performed in each region according to the corresponding overall power grid density of the region.
摘要翻译：提供一种自动电网合成方法和用于存储其用于在电路区域中合成电网的程序的计算机可读记录介质。电路区域中至少有一个功耗模块和设置在电路区域周围的至少一个电源引脚。该方法包括以下步骤。首先，在每个耗电模块中选择至少一个代表点。电路区域根据代表点和电源引脚的位置被分成多个区域。根据每个电源引脚的位置和每个代表点的功耗或电流要求计算每个区域的整体电网密度。最后，根据该区域的相应总体电网密度，在每个区域进行电网综合。

10. 发明授权

US07516427B2 Input capacitance characterization method in IP library 失效
标题翻译： IP库中的输入电容表征方法
公开(公告)号：US07516427B2
公开(公告)日：2009-04-07
申请号：US11197820
申请日：2005-08-05
申请人： Peter H. Chen , Han-Chi Liu , Chih-Yang Peng , Jyh-Herng Wang , Chia-Nan Hong
发明人： Peter H. Chen , Han-Chi Liu , Chih-Yang Peng , Jyh-Herng Wang , Chia-Nan Hong
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A methodology for characterization of an IP (Intellectual Property) component is provided. Digital pins are recognized by skipping analog pins and special IO pins. First two layers of the IP component are classified in response to connection of the input pins. Partial circuits of the IP component are extracted for simulation. Three corners of IP library are generated. Therefore, input capacitance of the IP component is simulated.
摘要翻译：提供了一个用于表征知识产权（知识产权）组件的方法。通过跳过模拟引脚和特殊IO引脚可识别数字引脚。响应于输入引脚的连接，IP组件的前两层被分类。提取IP组件的部分电路进行仿真。生成IP库的三个角落。因此，模拟IP组件的输入电容。

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