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1. 发明申请

US20060261439A1 CAPACITOR STRUCTURE 审中-公开
标题翻译：电容结构
公开(公告)号：US20060261439A1
公开(公告)日：2006-11-23
申请号：US10908552
申请日：2005-05-17
申请人： Chih-Fu Chien , Chao-Chi Lee , Cheng-Chung Chou
发明人： Chih-Fu Chien , Chao-Chi Lee , Cheng-Chung Chou
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L23/49822 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A capacitor structure including a first electrode set and a second electrode set is provided. The first electrode set comprises a plurality of first stripe electrodes, which are parallel to each other, and a first coupling circuit. The first coupling circuit is coupled to a part of stripe electrodes, wherein the coupled first stripe electrodes and the uncoupled first stripe electrodes are alternately arranged. In addition, the second electrode set comprises a plurality of second stripe electrodes, which are parallel to each other, and a second coupling circuit. The second coupling circuit is coupled to a part of the second stripe electrodes, wherein the coupled second stripe electrodes and the uncoupled second stripe electrodes are alternately arranged. Furthermore, the coupled first stripe electrodes are coupled to the coupled second stripe electrodes, and the uncoupled first stripe electrodes are coupled to the uncoupled second stripe electrodes.
摘要翻译：提供了包括第一电极组和第二电极组的电容器结构。第一电极组包括彼此平行的多个第一条形电极和第一耦合电路。第一耦合电路耦合到条形电极的一部分，其中耦合的第一条形电极和非耦合的第一条形电极交替排列。此外，第二电极组包括彼此平行的多个第二条形电极和第二耦合电路。第二耦合电路耦合到第二条形电极的一部分，其中耦合的第二条形电极和非耦合的第二条形电极交替布置。此外，耦合的第一条形电极耦合到耦合的第二条形电极，并且非耦合的第一条形电极耦合到非耦合的第二条形电极。

2. 发明授权

US06538868B2 Electrostatic discharge protective circuit 失效
公开(公告)号：US06538868B2
公开(公告)日：2003-03-25
申请号：US10236821
申请日：2002-09-06
申请人： Hung-Yi Chang , Yi-Hua Chang , Chih-Fu Chien
发明人： Hung-Yi Chang , Yi-Hua Chang , Chih-Fu Chien
IPC分类号： H02H900
CPC分类号： H01L27/0266
摘要： An electrostatic discharge protective circuit can receive a pre-stage driver output and involve a first PMOS transistor, a first NMOS transistor and a second NMOS transistor and all connect in series. More particularly, a source region of the first PMOS transistor connects to a system power source; and a drain region connects to a conductive pad, and a gate receives the pre-stage driver output. A gate of the first NMOS transistor connects to a first node A, a gate of the second NMOS transistor connects to a third node C and a source region connects to a grounded node. The third node C also can receive the pre-stage driver output. There is a first resistor between the first node A and the system power source. There is a second PMOS transistor in between the first node A and the third node C and connect with two source/drain regions. And the substrate of the second PMOS transistor also connects with the first node A. Also, a gate of the second PMOS transistor connects with a second node B. There is a second resistor between the second node B and the system power source, and there is a capacitor between the second node B and the grounded node.

3. 发明授权

US06469560B1 Electrostatic discharge protective circuit 失效
标题翻译：静电放电保护电路
公开(公告)号：US06469560B1
公开(公告)日：2002-10-22
申请号：US09895551
申请日：2001-06-28
申请人： Hung-Yi Chang , Yi-Hua Chang , Chih-Fu Chien
发明人： Hung-Yi Chang , Yi-Hua Chang , Chih-Fu Chien
IPC分类号： H03K508
CPC分类号： H01L27/0266
摘要： An electrostatic discharge protective circuit can receive a pre-stage driver output and involve a first PMOS transistor, a first NMOS transistor and a second NMOS transistor and all connect in series. More particularly, a source region of the first PMOS transistor connects to a system power source; and a drain region connects to a conductive pad, and a gate receives the pre-stage driver output. A gate of the first NMOS transistor connects to a first node A, a gate of the second NMOS transistor connects to a third node C and a source region connects to a grounded node. The third node C also can receive the pre-stage driver output. There is a first resistor between the first node A and the system power source. There is a second PMOS transistor in between the first node A and the third node C and connect with two source/drain regions. And the substrate of the second PMOS transistor also connects with the first node A. Also, a gate of the second PMOS transistor connects with a second node B. There is a second resistor between the second node B and the system power source, and there is a capacitor between the second node B and the grounded node.
摘要翻译：静电放电保护电路可以接收前级驱动器输出并涉及第一PMOS晶体管，第一NMOS晶体管和第二NMOS晶体管，并且全部串联连接。更具体地，第一PMOS晶体管的源极区域连接到系统电源; 并且漏极区域连接到导电焊盘，并且栅极接收前级驱动器输出。第一NMOS晶体管的栅极连接到第一节点A，第二NMOS晶体管的栅极连接到第三节点C，源极区域连接到接地节点。第三节点C也可以接收前级驱动器的输出。第一个节点A和系统电源之间有一个第一个电阻。在第一节点A和第三节点C之间存在第二PMOS晶体管，并与两个源极/漏极区域连接。并且第二PMOS晶体管的衬底也与第一节点A连接。另外，第二PMOS晶体管的栅极与第二节点B连接。在第二节点B和系统电源之间存在第二电阻器，并且在那里是第二节点B和接地节点之间的电容器。

4. 发明授权

US06456115B2 Clock gate buffering circuit 失效
标题翻译：时钟门缓冲电路
公开(公告)号：US06456115B2
公开(公告)日：2002-09-24
申请号：US09779398
申请日：2001-02-08
申请人： Guo-Wei Li , Jeng-Huang Wu , Chih-Fu Chien
发明人： Guo-Wei Li , Jeng-Huang Wu , Chih-Fu Chien
IPC分类号： H03K19096
CPC分类号： H03K19/0963 , H03K19/0013
摘要： A clock gate buffering circuit is having a functional circuit without a latch that receives a clock and an enable signal. A logic voltage of an enable signal sends a corresponding clock gate signal to provide the other circuit when the clock of the functional circuit is in a rising edge. Also, the logical voltage of the enable signal sends a corresponding clock gate signal to provide the other circuit when this functional circuit is also in falling edge.
摘要翻译：时钟门缓冲电路具有没有接收时钟和使能信号的锁存器的功能电路。当功能电路的时钟处于上升沿时，使能信号的逻辑电压发送相应的时钟门信号以提供另一电路。此外，当该功能电路也处于下降沿时，使能信号的逻辑电压发送相应的时钟门信号以提供另一电路。

5. 发明授权

US07516058B2 Method for IP characterization and path finding, and computer readable recording medium for storing program thereof 失效
标题翻译：用于IP表征和路径查找的方法，以及用于存储其程序的计算机可读记录介质
公开(公告)号：US07516058B2
公开(公告)日：2009-04-07
申请号：US10711472
申请日：2004-09-21
申请人： Peter Hanping Chen , Chih-Fu Chien , Jyh-Herng Wang , Hsu-Hui Tsai
发明人： Peter Hanping Chen , Chih-Fu Chien , Jyh-Herng Wang , Hsu-Hui Tsai
IPC分类号： G06F17/50
CPC分类号： G01R31/318371
摘要： IP characterization and for path finding methods, and a computer readable recording medium for storing program are provided. First, an Intellectual Property (IP) component is provided. Then, a plurality of test patterns for all paths in the IP component is automatically generated. The test patterns are then sequentially input into the IP component for simulation, and a plurality of corresponding simulation results is generated. Finally, an IP characteristic library is generated based on the simulation results.
摘要翻译： IP表征和路径查找方法，以及用于存储程序的计算机可读记录介质。首先，提供知识产权（IP）组件。然后，自动生成IP分量中的所有路径的多个测试模式。然后将测试模式顺序地输入到IP组件中用于模拟，并且生成多个相应的模拟结果。最后，根据仿真结果生成IP特征库。

6. 发明授权

US07339225B2 Capacitor structure 失效
标题翻译：电容结构
公开(公告)号：US07339225B2
公开(公告)日：2008-03-04
申请号：US10908639
申请日：2005-05-20
申请人： Chih-Fu Chien , Chao-Chi Lee , Cheng-Chung Chou
发明人： Chih-Fu Chien , Chao-Chi Lee , Cheng-Chung Chou
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L28/60 , H01L23/50 , H01L23/5223 , H01L27/1085 , H01L2924/0002 , H01L2924/00
摘要： A capacitor structure is provided. The capacitor structure is configured in a substrate. The capacitor structure includes a plurality of electrode sets, at least a first conductive plug and at least a second conductive plug. The electrode sets correspond with each other and are disposed in different layers of the substrate. Each electrode set comprises a first electrode and a second electrode surrounding the former. In addition, the first conductive plug and the second conductive plug are disposed between two adjacent electrode sets. First electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the first conductive plug. Similarly, second electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the second conductive plug.
摘要翻译：提供电容器结构。电容器结构配置在基板中。电容器结构包括多个电极组，至少第一导电插头和至少第二导电插头。电极组彼此对应并且设置在衬底的不同层中。每个电极组包括第一电极和围绕前者的第二电极。此外，第一导电插塞和第二导电插头设置在两个相邻的电极组之间。两个相邻电极组的第一电极彼此对应并且通过第一导电插塞彼此电连接。类似地，两个相邻电极组的第二电极彼此对应并且通过第二导电插塞彼此电连接。

7. 发明授权

US07046055B2 Voltage detection circuit 失效
公开(公告)号：US07046055B2
公开(公告)日：2006-05-16
申请号：US11250733
申请日：2005-10-14
申请人： Chao-Chi Lee , Yu-Tong Lin , Chih-Fu Chien
发明人： Chao-Chi Lee , Yu-Tong Lin , Chih-Fu Chien
IPC分类号： H03L7/00
CPC分类号： H03K17/223
摘要： A voltage detection circuit for detecting the voltage level of a first power source. A first transistor includes a first gate, a first source, and a first drain coupled to the first gate. A second transistor includes a second gate, a second source, and a second drain coupled to the second gate. A comparator includes a first input terminal, a second input terminal coupled to the second drain, and an output terminal. A first resistor is coupled between the first input terminal and the first drain. A second resistor is coupled to the first power source. A third resistor is coupled between the second resistor and the first input terminal. A fourth resistor is coupled between the second resistor and input terminal. A fifth resistor is coupled between the first source, and a second power source. A resistive device is coupled between the first source, and the first power source.

8. 发明授权

US07389488B2 Method of finding driving strength and computer accessible record medium to store program thereof 失效
标题翻译：寻找驾驶强度的方法和计算机可访问记录介质来存储其程序
公开(公告)号：US07389488B2
公开(公告)日：2008-06-17
申请号：US10908748
申请日：2005-05-25
申请人： Peter H. Chen , Chih-Fu Chien , Han-chi Liu , Jyh-Herng Wang
发明人： Peter H. Chen , Chih-Fu Chien , Han-chi Liu , Jyh-Herng Wang
IPC分类号： G06F17/50 , H03K19/00
CPC分类号： G06F17/5036
摘要： A method of finding a driving strength and a record medium accessible by a computer to store a program thereof are provided. The method is adapted to find the driving strength of an output pin of a target cell. Wherein, the driving strength of the output pin of the target cell is provided from the driving strength of a corresponding last level device. In this method, at least one candidate standard cell is searched in a standard cell library according to the last level device. Then, the driving strength of the target cell is interpolated between the driving strengths of the candidate standard cells to obtain the driving strength of the output pin of the target cell.
摘要翻译：提供了一种找到驱动强度的方法和一种可由计算机访问以存储其程序的记录介质。该方法适于找出目标单元的输出引脚的驱动强度。其中，从相应的最后一级装置的驱动强度提供目标单元的输出引脚的驱动强度。在该方法中，根据最后一级设备在标准单元库中搜索至少一个候选标准单元。然后，在候选标准单元的驱动强度之间插入目标单元的驱动强度，以获得目标单元的输出引脚的驱动强度。

9. 发明申请

US20070090429A1 CAPACITOR STRUCTURE 失效
标题翻译：电容结构
公开(公告)号：US20070090429A1
公开(公告)日：2007-04-26
申请号：US11561416
申请日：2006-11-19
申请人： Chih-Fu Chien , Chao-Chi Lee , Cheng-Chung Chou
发明人： Chih-Fu Chien , Chao-Chi Lee , Cheng-Chung Chou
IPC分类号： H01L29/94
CPC分类号： H01L28/60 , H01L23/50 , H01L23/5223 , H01L27/1085 , H01L2924/0002 , H01L2924/00
摘要： A capacitor structure is provided. The capacitor structure is configured in a substrate. The capacitor structure includes a plurality of electrode sets, at least a first conductive plug and at least a second conductive plug. The electrode sets correspond with each other and are disposed in different layers of the substrate. Each electrode set comprises a first electrode and a second electrode surrounding the former. In addition, the first conductive plug and the second conductive plug are disposed between two adjacent electrode sets. First electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the first conductive plug. Similarly, second electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the second conductive plug.
摘要翻译：提供电容器结构。电容器结构配置在基板中。电容器结构包括多个电极组，至少第一导电插头和至少第二导电插头。电极组彼此对应并且设置在衬底的不同层中。每个电极组包括第一电极和围绕前者的第二电极。此外，第一导电插塞和第二导电插头设置在两个相邻的电极组之间。两个相邻电极组的第一电极彼此对应并且通过第一导电插塞彼此电连接。类似地，两个相邻电极组的第二电极彼此对应并且通过第二导电插塞彼此电连接。

10. 发明申请

US20060062155A1 METHOD FOR IP CHARACTERIZATION AND PATH FINDING, AND COMPUTER READABLE RECORDING MEDIUM FOR STORING PROGRAM THEREOF 失效
标题翻译： IP特征和路径查找方法及其存储程序的计算机可读记录介质
公开(公告)号：US20060062155A1
公开(公告)日：2006-03-23
申请号：US10711472
申请日：2004-09-21
申请人： Peter Hanping Chen , Chih-Fu Chien , Jyh-Herng Wang , Hsu-Hui Tsai
发明人： Peter Hanping Chen , Chih-Fu Chien , Jyh-Herng Wang , Hsu-Hui Tsai
IPC分类号： H04J1/16
CPC分类号： G01R31/318371
摘要： IP characterization and for path finding methods, and a computer readable recording medium for storing program are provided. First, an Intellectual Property (IP) component is provided. Then, a plurality of test patterns for all paths in the IP component is automatically generated. The test patterns are then sequentially input into the IP component for simulation, and a plurality of corresponding simulation results is generated. Finally, an IP characteristic library is generated based on the simulation results.
摘要翻译： IP表征和路径查找方法，以及用于存储程序的计算机可读记录介质。首先，提供知识产权（IP）组件。然后，自动生成IP分量中的所有路径的多个测试模式。然后将测试模式顺序地输入到IP组件中用于模拟，并且生成多个相应的模拟结果。最后，根据仿真结果生成IP特征库。

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